from:"Daniel Kiss via Phabricator via cfe\-commits"

[PATCH] D150262: Disable sanitizer's on ifunc resolvers.

2023-08-14 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1ef3de6b09f6: Disable sanitizers on ifunc resolvers. 
(authored by danielkiss).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

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Files:
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/ifunc.c


Index: clang/test/CodeGen/ifunc.c
===
--- clang/test/CodeGen/ifunc.c
+++ clang/test/CodeGen/ifunc.c
@@ -1,5 +1,8 @@
 // RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm -o - %s | 
FileCheck %s
 // RUN: %clang_cc1 -triple i386-unknown-linux-gnu -O2 -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=thread -O2 
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=address -O2 
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=memory -O2 
-emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
 
 int foo(int) __attribute__ ((ifunc("foo_ifunc")));
 
@@ -39,3 +42,11 @@
 
 // CHECK: call i32 @foo(i32
 // CHECK: call void @goo()
+
+// SAN: define internal nonnull ptr @foo_ifunc() #[[#FOO_IFUNC:]] {
+
+// SAN: define dso_local noalias ptr @goo_ifunc() #[[#GOO_IFUNC:]] {
+
+// SAN-DAG: attributes #[[#FOO_IFUNC]] = {{{.*}} 
disable_sanitizer_instrumentation {{.*}}
+
+// SAN-DAG: attributes #[[#GOO_IFUNC]] = {{{.*}} 
disable_sanitizer_instrumentation {{.*}}
Index: clang/lib/CodeGen/CodeGenModule.cpp
===
--- clang/lib/CodeGen/CodeGenModule.cpp
+++ clang/lib/CodeGen/CodeGenModule.cpp
@@ -5832,7 +5832,9 @@
 Entry->eraseFromParent();
   } else
 GIF->setName(MangledName);
-
+  if (auto *F = dyn_cast(Resolver)) {
+F->addFnAttr(llvm::Attribute::DisableSanitizerInstrumentation);
+  }
   SetCommonAttributes(GD, GIF);
 }
 


Index: clang/test/CodeGen/ifunc.c
===
--- clang/test/CodeGen/ifunc.c
+++ clang/test/CodeGen/ifunc.c
@@ -1,5 +1,8 @@
 // RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -triple i386-unknown-linux-gnu -O2 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=thread -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=address -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -fsanitize=memory -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=SAN
 
 int foo(int) __attribute__ ((ifunc("foo_ifunc")));
 
@@ -39,3 +42,11 @@
 
 // CHECK: call i32 @foo(i32
 // CHECK: call void @goo()
+
+// SAN: define internal nonnull ptr @foo_ifunc() #[[#FOO_IFUNC:]] {
+
+// SAN: define dso_local noalias ptr @goo_ifunc() #[[#GOO_IFUNC:]] {
+
+// SAN-DAG: attributes #[[#FOO_IFUNC]] = {{{.*}} disable_sanitizer_instrumentation {{.*}}
+
+// SAN-DAG: attributes #[[#GOO_IFUNC]] = {{{.*}} disable_sanitizer_instrumentation {{.*}}
Index: clang/lib/CodeGen/CodeGenModule.cpp
===
--- clang/lib/CodeGen/CodeGenModule.cpp
+++ clang/lib/CodeGen/CodeGenModule.cpp
@@ -5832,7 +5832,9 @@
 Entry->eraseFromParent();
   } else
 GIF->setName(MangledName);
-
+  if (auto *F = dyn_cast(Resolver)) {
+F->addFnAttr(llvm::Attribute::DisableSanitizerInstrumentation);
+  }
   SetCommonAttributes(GD, GIF);
 }
 
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[PATCH] D150867: [AArch64][FMV] Prevent target attribute using for multiversioning.

2023-05-23 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D150800: [AArch64][FMV] Fix name mangling.

2023-05-23 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D135652: [AArch64] Add preserve_all calling convention.

2023-04-28 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd75e70d7ae1f: [AArch64] Add preserve_all calling convention. 
(authored by danielkiss).
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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/AttrDocs.td
  llvm/docs/LangRef.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Target/AArch64/AArch64CallingConvention.td
  llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
  llvm/test/CodeGen/AArch64/preserve.ll
  llvm/test/CodeGen/AArch64/tailcall-ccmismatch2.ll

Index: llvm/test/CodeGen/AArch64/tailcall-ccmismatch2.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/tailcall-ccmismatch2.ll
@@ -0,0 +1,25 @@
+; RUN: llc -o - %s | FileCheck %s
+; RUN: llc -global-isel -verify-machineinstrs -o - %s | FileCheck %s
+target triple="aarch64--"
+
+declare void @somefunc()
+define preserve_allcc void @test_ccmismatch_notail() {
+; Ensure that no tail call is used here, as the called function somefunc does
+; not preserve enough registers for preserve_allcc.
+; CHECK-LABEL: test_ccmismatch_notail:
+; CHECK-NOT: b somefunc
+; CHECK: bl somefunc
+  tail call void @somefunc()
+  ret void
+}
+
+declare preserve_allcc void @some_preserve_all_func()
+define void @test_ccmismatch_tail() {
+; We can perform a tail call here, because some_preserve_all_func preserves
+; all registers necessary for test_ccmismatch_tail.
+; CHECK-LABEL: test_ccmismatch_tail:
+; CHECK-NOT: bl some_preserve_all_func
+; CHECK: b some_preserve_all_func
+  tail call preserve_allcc void @some_preserve_all_func()
+  ret void
+}
Index: llvm/test/CodeGen/AArch64/preserve.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/preserve.ll
@@ -0,0 +1,22 @@
+
+; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
+
+target triple = "aarch64-unknown-unknown"
+declare void @bar1()
+define preserve_mostcc void @baz() #0 {
+; CHECK: baz Clobbered Registers: $ffr $fpcr $nzcv $sp $vg $wsp $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $b16 $b17 $b18 $b19 $b20 $b21 $b22 $b23 $b24 $b25 $b26 $b27 $b28 $b29 $b30 $b31 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $h16 $h17 $h18 $h19 $h20 $h21 $h22 $h23 $h24 $h25 $h26 $h27 $h28 $h29 $h30 $h31 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $q16 $q17 $q18 $q19 $q20 $q21 $q22 $q23 $q24 $q25 $q26 $q27 $q28 $q29 $q30 $q31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 $s28 $s29 $s30 $s31 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $z0_hi $z1_hi $z2_hi $z3_hi $z4_hi $z5_hi $z6_hi $z7_hi $z8_hi $z9_hi $z10_hi $z11_hi $z12_hi $z13_hi $z14_hi $z15_hi $z16_hi $z17_hi $z18_hi $z19_hi $z20_hi $z21_hi $z22_hi $z23_hi $z24_hi $z25_hi $z26_hi $z27_hi $z28_hi $z29_hi $z30_hi $z31_hi $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15

[PATCH] D142265: [AArch64] Function multi-versioning release notes added. NFC.

2023-01-23 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

LGTM Thanks


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[PATCH] D134719: [AArch64] Enable libm vectorized functions via SLEEF

2023-01-20 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc4fa504f797f: [AArch64] Enable libm vectorized functions via 
SLEEF (authored by danielkiss).
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Files:
  clang/include/clang/Basic/CodeGenOptions.h
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/autocomplete.c
  clang/test/Driver/fveclib.c
  llvm/include/llvm/Analysis/TargetLibraryInfo.h
  llvm/include/llvm/Analysis/VecFuncs.def
  llvm/lib/Analysis/TargetLibraryInfo.cpp
  llvm/test/Transforms/LoopVectorize/AArch64/sleef-calls-aarch64.ll

Index: llvm/test/Transforms/LoopVectorize/AArch64/sleef-calls-aarch64.ll
===
--- /dev/null
+++ llvm/test/Transforms/LoopVectorize/AArch64/sleef-calls-aarch64.ll
@@ -0,0 +1,1076 @@
+; Do NOT use -O3. It will lower exp2 to ldexp, and the test will fail.
+; RUN: opt -vector-library=sleefgnuabi -replace-with-veclib -loop-unroll -loop-vectorize -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+declare double @acos(double) #0
+declare float @acosf(float) #0
+declare double @llvm.acos.f64(double) #0
+declare float @llvm.acos.f32(float) #0
+
+define void @acos_f64(double* nocapture %varray) {
+  ; CHECK-LABEL: @acos_f64(
+  ; CHECK:[[TMP5:%.*]] = call <2 x double> @_ZGVnN2v_acos(<2 x double> [[TMP4:%.*]])
+  ; CHECK:ret void
+  ;
+  entry:
+  br label %for.body
+
+  for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @acos(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 8
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+  for.end:
+  ret void
+}
+
+define void @acos_f32(float* nocapture %varray) {
+  ; CHECK-LABEL: @acos_f32(
+  ; CHECK:[[TMP5:%.*]] = call <4 x float> @_ZGVnN4v_acosf(<4 x float> [[TMP4:%.*]])
+  ; CHECK:ret void
+  ;
+  entry:
+  br label %for.body
+
+  for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @acosf(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+  for.end:
+  ret void
+}
+
+declare double @asin(double) #0
+declare float @asinf(float) #0
+declare double @llvm.asin.f64(double) #0
+declare float @llvm.asin.f32(float) #0
+
+define void @asin_f64(double* nocapture %varray) {
+  ; CHECK-LABEL: @asin_f64(
+  ; CHECK:[[TMP5:%.*]] = call <2 x double> @_ZGVnN2v_asin(<2 x double> [[TMP4:%.*]])
+  ; CHECK:ret void
+  ;
+  entry:
+  br label %for.body
+
+  for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @asin(double %conv)
+  %arrayidx = getelementptr inbounds double, double* %varray, i64 %iv
+  store double %call, double* %arrayidx, align 8
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+  for.end:
+  ret void
+}
+
+define void @asin_f32(float* nocapture %varray) {
+  ; CHECK-LABEL: @asin_f32(
+  ; CHECK:[[TMP5:%.*]] = call <4 x float> @_ZGVnN4v_asinf(<4 x float> [[TMP4:%.*]])
+  ; CHECK:ret void
+  ;
+  entry:
+  br label %for.body
+
+  for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to float
+  %call = tail call float @asinf(float %conv)
+  %arrayidx = getelementptr inbounds float, float* %varray, i64 %iv
+  store float %call, float* %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body
+
+  for.end:
+  ret void
+}
+
+declare double @atan(double) #0
+declare float @atanf(float) #0
+declare double @llvm.atan.f64(double) #0
+declare float @llvm.atan.f32(float) #0
+
+define void @atan_f64(double* nocapture %varray) {
+  ; CHECK-LABEL: @atan_f64(
+  ; CHECK:[[TMP5:%.*]] = call <2 x double> @_ZGVnN2v_atan(<2 x double> [[TMP4:%.*]])
+  ; CHECK:ret void
+  ;
+  entry:
+  br label %for.body
+
+  for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp =

[PATCH] D138792: [AArch64] Improve TargetParser API

2023-01-13 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:532
 getTargetDefinesARMV81A(Opts, Builder);
-break;
-  case llvm::AArch64::ArchKind::ARMV8_2A:
+  if (*ArchInfo == llvm::AArch64::ARMV8_2A)
 getTargetDefinesARMV82A(Opts, Builder);





Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:172
+   *ArchInfo == llvm::AArch64::ARMV9_1A ||
+   *ArchInfo == llvm::AArch64::ARMV9_2A)) {
 Features.push_back("+sve");

Would be nice to add a custom operator to `ArchInfo` to say `*ArchInfo >= 
llvm::AArch64::ARMV9A`
because it looks to me here the `llvm::AArch64::ARMV9_3A` and 
`llvm::AArch64::ARMV9_4A` are missing.


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[PATCH] D127812: [AArch64] FMV support and necessary target features dependencies.

2022-12-09 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

just small comment, thanks @ilinpv
LGTM, just let others to chime in.




Comment at: clang/lib/Basic/Targets/AArch64.cpp:652
+  // AARCH64_ARCH_EXT_NAME feature with top priority must be taken.
+  return multiVersionSortPriority("sme2");
+}

wondering if we could use `FEAT_MAX` (or similar) here to avoid error as add 
features later. maybe a comment in `AArch64TargetParser.def` is the solution.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:771-790
+  HasRDM = false;
+  HasDIT = false;
+  HasCCPP = false;
+  HasCCDP = false;
+  HasFRInt3264 = false;
+  HasFlagM = false;
+  HasAlternativeNZCV = false;

Please note the initialisation moved, see D139622. 
Sorry , but hopefully an easy rebase.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:1010-1011
+
+  if (HasNoNeon)
+FPU &= ~NeonMode;
+  if (HasNoSVE)

maybe we need do disable SVE too here?


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[PATCH] D139622: [AArch64][NFC] Move hasFeature fields initiations to the declaration

2022-12-09 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG218b77c85057: [AArch64][NFC] Move hasFeature fields 
initiations to the declaration (authored by danielkiss).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D139622

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h

Index: clang/lib/Basic/Targets/AArch64.h
===
--- clang/lib/Basic/Targets/AArch64.h
+++ clang/lib/Basic/Targets/AArch64.h
@@ -27,36 +27,36 @@
 
   enum FPUModeEnum { FPUMode, NeonMode = (1 << 0), SveMode = (1 << 1) };
 
-  unsigned FPU;
-  bool HasCRC;
-  bool HasAES;
-  bool HasSHA2;
-  bool HasSHA3;
-  bool HasSM4;
-  bool HasUnaligned;
-  bool HasFullFP16;
-  bool HasDotProd;
-  bool HasFP16FML;
-  bool HasMTE;
-  bool HasTME;
-  bool HasPAuth;
-  bool HasLS64;
-  bool HasRandGen;
-  bool HasMatMul;
-  bool HasSVE2;
-  bool HasSVE2AES;
-  bool HasSVE2SHA3;
-  bool HasSVE2SM4;
-  bool HasSVE2BitPerm;
-  bool HasMatmulFP64;
-  bool HasMatmulFP32;
-  bool HasLSE;
-  bool HasFlagM;
-  bool HasMOPS;
-  bool HasD128;
-  bool HasRCPC;
-
-  llvm::AArch64::ArchKind ArchKind;
+  unsigned FPU = FPUMode;
+  bool HasCRC = false;
+  bool HasAES = false;
+  bool HasSHA2 = false;
+  bool HasSHA3 = false;
+  bool HasSM4 = false;
+  bool HasUnaligned = true;
+  bool HasFullFP16 = false;
+  bool HasDotProd = false;
+  bool HasFP16FML = false;
+  bool HasMTE = false;
+  bool HasTME = false;
+  bool HasPAuth = false;
+  bool HasLS64 = false;
+  bool HasRandGen = false;
+  bool HasMatMul = false;
+  bool HasSVE2 = false;
+  bool HasSVE2AES = false;
+  bool HasSVE2SHA3 = false;
+  bool HasSVE2SM4 = false;
+  bool HasSVE2BitPerm = false;
+  bool HasMatmulFP64 = false;
+  bool HasMatmulFP32 = false;
+  bool HasLSE = false;
+  bool HasFlagM = false;
+  bool HasMOPS = false;
+  bool HasD128 = false;
+  bool HasRCPC = false;
+
+  llvm::AArch64::ArchKind ArchKind = llvm::AArch64::ArchKind::INVALID;
 
   static const Builtin::Info BuiltinInfo[];
 
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -579,37 +579,6 @@
 
 bool AArch64TargetInfo::handleTargetFeatures(std::vector ,
  DiagnosticsEngine ) {
-  FPU = FPUMode;
-  HasCRC = false;
-  HasAES = false;
-  HasSHA2 = false;
-  HasSHA3 = false;
-  HasSM4 = false;
-  HasUnaligned = true;
-  HasFullFP16 = false;
-  HasDotProd = false;
-  HasFP16FML = false;
-  HasMTE = false;
-  HasTME = false;
-  HasLS64 = false;
-  HasRandGen = false;
-  HasMatMul = false;
-  HasBFloat16 = false;
-  HasSVE2 = false;
-  HasSVE2AES = false;
-  HasSVE2SHA3 = false;
-  HasSVE2SM4 = false;
-  HasSVE2BitPerm = false;
-  HasMatmulFP64 = false;
-  HasMatmulFP32 = false;
-  HasLSE = false;
-  HasMOPS = false;
-  HasD128 = false;
-  HasRCPC = false;
-  HasPAuth = false;
-
-  ArchKind = llvm::AArch64::ArchKind::INVALID;
-
   for (const auto  : Features) {
 if (Feature == "+neon")
   FPU |= NeonMode;
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[PATCH] D139503: [Headers][ARM] Allow `struct _Unwind_Exception` in unwind.h

2022-12-07 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

Wondering if we could deduplicate the headers?


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[PATCH] D139445: [AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH

2022-12-07 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcfd44221e3e1: [AArch64] Add __ARM_FEATURE_BTI and 
__ARM_FEATURE_PAUTH (authored by danielkiss).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/test/Preprocessor/aarch64-target-features.c


Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -461,6 +461,7 @@
 // == Check Pointer Authentication Extension (PAuth).
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - 
| FileCheck -check-prefix=CHECK-PAUTH-OFF %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a -x c -E -dM %s -o 
- | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth 
-mbranch-protection=none -x c -E -dM %s -o - | FileCheck 
-check-prefix=CHECK-PAUTH-ON %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a 
-mbranch-protection=none -x c -E -dM %s -o - | FileCheck 
-check-prefix=CHECK-PAUTH-OFF %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a 
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck 
-check-prefix=CHECK-PAUTH-OFF %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a 
-mbranch-protection=standard -x c -E -dM %s -o - | FileCheck 
-check-prefix=CHECK-PAUTH %s
@@ -473,6 +474,7 @@
 // CHECK-PAUTH-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
 // CHECK-PAUTH-ALL:  #define __ARM_FEATURE_PAC_DEFAULT 5
 // CHECK-PAUTH-BKEY-ALL: #define __ARM_FEATURE_PAC_DEFAULT 6
+// CHECK-PAUTH-ON:   #define __ARM_FEATURE_PAUTH 1
 
 // == Check Branch Target Identification (BTI).
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - 
| FileCheck -check-prefix=CHECK-BTI-OFF %s
@@ -560,10 +562,12 @@
 // RUN: %clang -target aarch64-arm-none-eabi -march=armv9.2-a -x c -E -dM %s 
-o - | FileCheck 
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
 // RUN: %clang -target aarch64-arm-none-eabi -march=armv9.3-a -x c -E -dM %s 
-o - | FileCheck 
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
 // CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
+// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
 // CHECK-V83-OR-LATER: __ARM_FEATURE_COMPLEX 1
 // CHECK-V81-OR-LATER: __ARM_FEATURE_CRC32 1
 // CHECK-V85-OR-LATER: __ARM_FEATURE_FRINT 1
 // CHECK-V83-OR-LATER: __ARM_FEATURE_JCVT 1
+// CHECK-V83-OR-LATER: __ARM_FEATURE_PAUTH 1
 // CHECK-V81-OR-LATER: __ARM_FEATURE_QRDMX 1
 // CHECK-BEFORE-V83-NOT: __ARM_FEATURE_COMPLEX 1
 // CHECK-BEFORE-V83-NOT: __ARM_FEATURE_JCVT 1
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -199,6 +199,7 @@
 MacroBuilder ) const {
   Builder.defineMacro("__ARM_FEATURE_COMPLEX", "1");
   Builder.defineMacro("__ARM_FEATURE_JCVT", "1");
+  Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
   // Also include the Armv8.2 defines
   getTargetDefinesARMV82A(Opts, Builder);
 }
@@ -212,6 +213,7 @@
 void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions ,
 MacroBuilder ) const {
   Builder.defineMacro("__ARM_FEATURE_FRINT", "1");
+  Builder.defineMacro("__ARM_FEATURE_BTI", "1");
   // Also include the Armv8.4 defines
   getTargetDefinesARMV84A(Opts, Builder);
 }
@@ -385,6 +387,9 @@
 Builder.defineMacro("__ARM_FEATURE_SM4", "1");
   }
 
+  if (HasPAuth)
+Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
+
   if (HasUnaligned)
 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
 


Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -461,6 +461,7 @@
 // == Check Pointer Authentication Extension (PAuth).
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-ON %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=none -x c -E -dM %s -o - | FileCheck

[PATCH] D127812: [AArch64] FMV support and necessary target features dependencies.

2022-11-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:7305
 
+  if (Args.hasArg(options::OPT_mno_fmv)) {
+CmdArgs.push_back("-target-feature");

maybe we need to add a check here for compiler-rt as rt-lib because today 
libgcc is not yet has the __aarch64_cpu_features.



Comment at: compiler-rt/lib/builtins/cpu_model.c:1311
+  // CPU features already initialized.
+  if (__aarch64_cpu_features.features)
+return;

I'd add a init value for the declaration to be sure it is properly initialised. 


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[PATCH] D136062: [AArch64] Make ACLE intrinsics always available part MTE

2022-10-18 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG09aaf190d933: [AArch64] Make ACLE intrinsics always 
available part MTE (authored by danielkiss).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm64-mte.c
  clang/test/Sema/builtins-arm64-mte.c

Index: clang/test/Sema/builtins-arm64-mte.c
===
--- clang/test/Sema/builtins-arm64-mte.c
+++ clang/test/Sema/builtins-arm64-mte.c
@@ -1,8 +1,10 @@
 // RUN: %clang_cc1 -triple arm64-arm-eabi %s -target-feature +mte -fsyntax-only -verify
 // RUN: %clang_cc1 -triple arm64-arm-eabi %s -target-feature +mte -x c++ -fsyntax-only -verify
+// RUN: %clang_cc1 -triple arm64-arm-eabi %s -DNO_MTE -x c++ -S -emit-llvm  -verify
 #include 
 #include 
 
+#ifndef NO_MTE
 int  *create_tag1(int a, unsigned b) {
   // expected-error@+1 {{first argument of MTE builtin function must be a pointer ('int' invalid)}}
   return __arm_mte_create_random_tag(a,b);
@@ -134,3 +136,10 @@
   return __arm_mte_ptrdiff(nullptr, nullptr);
 }
 #endif
+
+#else
+int *create_tag1(int *a, unsigned b) {
+  // expected-error@+1 {{'__builtin_arm_irg' needs target feature mte}}
+  return __arm_mte_create_random_tag(a,b);
+}
+#endif
\ No newline at end of file
Index: clang/test/CodeGen/arm64-mte.c
===
--- clang/test/CodeGen/arm64-mte.c
+++ clang/test/CodeGen/arm64-mte.c
@@ -1,9 +1,17 @@
 // Test memory tagging extension intrinsics
 // RUN: %clang_cc1 -triple aarch64-none-linux-eabi -target-feature +mte -O3 -S -emit-llvm -o - %s  | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-eabi -DMTE -O3 -S -emit-llvm -o - %s  | FileCheck %s
 #include 
 #include 
 
+#ifdef MTE
+#define attribute  __attribute__((target("mte")))
+#else
+#define attribute
+#endif
+
 // CHECK-LABEL: define{{.*}} ptr @create_tag1
+attribute
 int *create_tag1(int *a, unsigned b) {
 // CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
 // CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -11,6 +19,7 @@
 }
 
 // CHECK-LABEL: define{{.*}} ptr @create_tag2
+attribute
 short *create_tag2(short *a, unsigned b) {
 // CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
 // CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -18,6 +27,7 @@
 }
 
 // CHECK-LABEL: define{{.*}} ptr @create_tag3
+attribute
 char *create_tag3(char *a, unsigned b) {
 // CHECK: [[T1:%[0-9]+]] = zext i32 %b to i64
 // CHECK: [[T2:%[0-9]+]] = tail call ptr @llvm.aarch64.irg(ptr %a, i64 [[T1]])
@@ -26,18 +36,21 @@
 }
 
 // CHECK-LABEL: define{{.*}} ptr @increment_tag1
+attribute
 char *increment_tag1(char *a) {
 // CHECK: call ptr @llvm.aarch64.addg(ptr %a, i64 3)
 return __arm_mte_increment_tag(a,3);
 }
 
 // CHECK-LABEL: define{{.*}} ptr @increment_tag2
+attribute
 short *increment_tag2(short *a) {
 // CHECK: [[T1:%[0-9]+]] = tail call ptr @llvm.aarch64.addg(ptr %a, i64 3)
 return __arm_mte_increment_tag(a,3);
 }
 
 // CHECK-LABEL: define{{.*}} i32 @exclude_tag
+attribute
 unsigned exclude_tag(int *a, unsigned m) {
 // CHECK: [[T0:%[0-9]+]] = zext i32 %m to i64
 // CHECK: [[T2:%[0-9]+]] = tail call i64 @llvm.aarch64.gmi(ptr %a, i64 [[T0]])
@@ -46,24 +59,28 @@
 }
 
 // CHECK-LABEL: define{{.*}} ptr @get_tag1
+attribute
 int *get_tag1(int *a) {
 // CHECK: [[T1:%[0-9]+]] = tail call ptr @llvm.aarch64.ldg(ptr %a, ptr %a)
return __arm_mte_get_tag(a);
 }
 
 // CHECK-LABEL: define{{.*}} ptr @get_tag2
+attribute
 short *get_tag2(short *a) {
 // CHECK: [[T1:%[0-9]+]] = tail call ptr @llvm.aarch64.ldg(ptr %a, ptr %a)
return __arm_mte_get_tag(a);
 }
 
 // CHECK-LABEL: define{{.*}} void @set_tag1
+attribute
 void set_tag1(int *a) {
 // CHECK: tail call void @llvm.aarch64.stg(ptr %a, ptr %a)
__arm_mte_set_tag(a);
 }
 
 // CHECK-LABEL: define{{.*}} i64 @subtract_pointers
+attribute
 ptrdiff_t subtract_pointers(int *a, int *b) {
 // CHECK: [[T2:%[0-9]+]] = tail call i64 @llvm.aarch64.subp(ptr %a, ptr %b)
 // CHECK: ret i64 [[T2]]
@@ -71,6 +88,7 @@
 }
 
 // CHECK-LABEL: define{{.*}} i64 @subtract_pointers_null_1
+attribute
 ptrdiff_t subtract_pointers_null_1(int *a) {
 // CHECK: [[T1:%[0-9]+]] = tail call i64 @llvm.aarch64.subp(ptr %a, ptr null)
 // CHECK: ret i64 [[T1]]
@@ -78,6 +96,7 @@
 }
 
 // CHECK-LABEL: define{{.*}} i64 @subtract_pointers_null_2
+attribute
 ptrdiff_t subtract_pointers_null_2(int *a) {
 // CHECK: [[T1:%[0-9]+]] = tail call i64 @llvm.aarch64.subp(ptr null, ptr %a)
 // CHECK: ret i64 [[T1]]
@@ -86,6 +105,7 @@
 
 // Check arithmetic promotion on return type
 // CHECK-LABEL: define{{.*}} i32

[PATCH] D133359: [AArch64] Make ACLE intrinsics always available part1

2022-10-14 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG30b67c677c6b: [AArch64] Make ACLE intrinsics always 
available part1 (authored by danielkiss).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
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Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/CodeGen/builtins-arm64.c

Index: clang/test/CodeGen/builtins-arm64.c
===
--- clang/test/CodeGen/builtins-arm64.c
+++ clang/test/CodeGen/builtins-arm64.c
@@ -59,6 +59,7 @@
   // CHECK: call {{.*}} @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0)
 }
 
+__attribute__((target("v8.5a")))
 int32_t jcvt(double v) {
   //CHECK-LABEL: @jcvt(
   //CHECK: call i32 @llvm.aarch64.fjcvtzs
@@ -133,6 +134,7 @@
 // CHECK-NEXT:[[TMP3:%.*]] = zext i1 [[TMP2]] to i32
 // CHECK-NEXT:ret i32 [[TMP3]]
 //
+__attribute__((target("rand")))
 int rndr(uint64_t *__addr) {
   return __builtin_arm_rndr(__addr);
 }
@@ -146,6 +148,7 @@
 // CHECK-NEXT:[[TMP3:%.*]] = zext i1 [[TMP2]] to i32
 // CHECK-NEXT:ret i32 [[TMP3]]
 //
+__attribute__((target("rand")))
 int rndrrs(uint64_t *__addr) {
   return __builtin_arm_rndrrs(__addr);
 }
Index: clang/test/CodeGen/arm_acle.c
===
--- clang/test/CodeGen/arm_acle.c
+++ clang/test/CodeGen/arm_acle.c
@@ -124,7 +124,7 @@
   __sevl();
 }
 
-#if __ARM_32BIT_STATE
+#ifdef __ARM_32BIT_STATE
 // AArch32-LABEL: @test_dbg(
 // AArch32-NEXT:  entry:
 // AArch32-NEXT:call void @llvm.arm.dbg(i32 0)
@@ -1646,7 +1646,7 @@
 #endif
 }
 
-#ifdef __ARM_64BIT_STATE
+#if defined(__ARM_64BIT_STATE) && defined(__ARM_FEATURE_JCVT)
 // AArch6483-LABEL: @test_jcvt(
 // AArch6483-NEXT:  entry:
 // AArch6483-NEXT:[[TMP0:%.*]] = call i32 @llvm.aarch64.fjcvtzs(double [[V:%.*]])
@@ -1658,7 +1658,7 @@
 #endif
 
 
-#if __ARM_64BIT_STATE && defined(__ARM_FEATURE_RNG)
+#if defined(__ARM_64BIT_STATE) && defined(__ARM_FEATURE_RNG)
 
 // AArch6485-LABEL: @test_rndr(
 // AArch6485-NEXT:  entry:
Index: clang/lib/Headers/arm_acle.h
===
--- clang/lib/Headers/arm_acle.h
+++ clang/lib/Headers/arm_acle.h
@@ -589,122 +589,123 @@
 #endif
 
 /* 9.7 CRC32 intrinsics */
-#if defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+#if (defined(__ARM_FEATURE_CRC32) && __ARM_FEATURE_CRC32) ||   \
+(defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE)
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32b(uint32_t __a, uint8_t __b) {
   return __builtin_arm_crc32b(__a, __b);
 }
 
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32h(uint32_t __a, uint16_t __b) {
   return __builtin_arm_crc32h(__a, __b);
 }
 
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32w(uint32_t __a, uint32_t __b) {
   return __builtin_arm_crc32w(__a, __b);
 }
 
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32d(uint32_t __a, uint64_t __b) {
   return __builtin_arm_crc32d(__a, __b);
 }
 
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32cb(uint32_t __a, uint8_t __b) {
   return __builtin_arm_crc32cb(__a, __b);
 }
 
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32ch(uint32_t __a, uint16_t __b) {
   return __builtin_arm_crc32ch(__a, __b);
 }
 
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32cw(uint32_t __a, uint32_t __b) {
   return __builtin_arm_crc32cw(__a, __b);
 }
 
-static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
+static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__, target("crc")))
 __crc32cd(uint32_t __a, uint64_t __b) {
   return __builtin_arm_crc32cd(__a, __b);
 }
 #endif
 
 /* Armv8.3-A Javascript conversion intrinsic */
-#if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE && defined(__ARM_FEATURE_JCVT)
-static __inline__ int32_t __attribute__((__always_inline__,

[PATCH] D134353: [AArch64] Add all predecessor archs in target info

2022-09-27 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG712de9d1716c: [AArch64] Add all predecessor archs in target 
info (authored by danielkiss).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D134353?vs=462842=463142#toc

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https://reviews.llvm.org/D134353

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/test/CodeGen/aarch64-subarch-compatbility.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -1584,6 +1584,27 @@
   }
 }
 
+TEST(TargetParserTest, AArch64ArchV9toV8Conversion) {
+  for (auto AK : AArch64::ArchKinds) {
+if (AK == AArch64::ArchKind::INVALID)
+  EXPECT_EQ(AK, AArch64::convertV9toV8(AK));
+else if (AK < AArch64::ArchKind::ARMV9A)
+  EXPECT_EQ(AK, AArch64::convertV9toV8(AK));
+else if (AK >= AArch64::ArchKind::ARMV8R)
+  EXPECT_EQ(AArch64::ArchKind::INVALID, AArch64::convertV9toV8(AK));
+else
+  EXPECT_TRUE(AArch64::convertV9toV8(AK) < AArch64::ArchKind::ARMV9A);
+  }
+  EXPECT_EQ(AArch64::ArchKind::ARMV8_5A,
+  AArch64::convertV9toV8(AArch64::ArchKind::ARMV9A));
+  EXPECT_EQ(AArch64::ArchKind::ARMV8_6A,
+  AArch64::convertV9toV8(AArch64::ArchKind::ARMV9_1A));
+  EXPECT_EQ(AArch64::ArchKind::ARMV8_7A,
+  AArch64::convertV9toV8(AArch64::ArchKind::ARMV9_2A));
+  EXPECT_EQ(AArch64::ArchKind::ARMV8_8A,
+  AArch64::convertV9toV8(AArch64::ArchKind::ARMV9_3A));
+}
+
 TEST(TargetParserTest, AArch64ArchExtFeature) {
   const char *ArchExt[][4] = {
   {"crc", "nocrc", "+crc", "-crc"},
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -59,6 +59,15 @@
   .Default(ArchKind::INVALID);
 }
 
+AArch64::ArchKind AArch64::getSubArchArchKind(StringRef SubArch) {
+  return StringSwitch(SubArch)
+#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU,\
+ ARCH_BASE_EXT)\
+  .Case(SUB_ARCH, ArchKind::ID)
+#include "../../include/llvm/Support/AArch64TargetParser.def"
+  .Default(ArchKind::INVALID);
+}
+
 bool AArch64::getExtensionFeatures(uint64_t Extensions,
std::vector ) {
   if (Extensions == AArch64::AEK_INVALID)
@@ -123,6 +132,19 @@
   return StringRef();
 }
 
+AArch64::ArchKind AArch64::convertV9toV8(AArch64::ArchKind AK) {
+  if (AK == AArch64::ArchKind::INVALID)
+return AK;
+  if (AK < AArch64::ArchKind::ARMV9A)
+return AK;
+  if (AK >= AArch64::ArchKind::ARMV8R)
+return AArch64::ArchKind::INVALID;
+  unsigned AK_v8 = static_cast(AArch64::ArchKind::ARMV8_5A);
+  AK_v8 += static_cast(AK) -
+   static_cast(AArch64::ArchKind::ARMV9A);
+  return static_cast(AK_v8);
+}
+
 StringRef AArch64::getDefaultCPU(StringRef Arch) {
   ArchKind AK = parseArch(Arch);
   if (AK == ArchKind::INVALID)
Index: llvm/include/llvm/Support/AArch64TargetParser.h
===
--- llvm/include/llvm/Support/AArch64TargetParser.h
+++ llvm/include/llvm/Support/AArch64TargetParser.h
@@ -113,6 +113,17 @@
 #include "AArch64TargetParser.def"
 };
 
+inline ArchKind (ArchKind ) {
+  if ((Kind == ArchKind::INVALID) || (Kind == ArchKind::ARMV8A) ||
+  (Kind == ArchKind::ARMV9A) || (Kind == ArchKind::ARMV8R))
+Kind = ArchKind::INVALID;
+  else {
+unsigned KindAsInteger = static_cast(Kind);
+Kind = static_cast(--KindAsInteger);
+  }
+  return Kind;
+}
+
 // FIXME: These should be moved to TargetTuple once it exists
 bool getExtensionFeatures(uint64_t Extensions,
   std::vector );
@@ -124,12 +135,14 @@
 StringRef getSubArch(ArchKind AK);
 StringRef getArchExtName(unsigned ArchExtKind);
 StringRef getArchExtFeature(StringRef ArchExt);
+ArchKind convertV9toV8(ArchKind AK);
 
 // Information by Name
 unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
 uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK);
 StringRef getDefaultCPU(StringRef Arch);
 ArchKind getCPUArchKind(StringRef CPU);
+ArchKind getSubArchArchKind(StringRef SubArch);
 
 // Parser
 ArchKind parseArch(StringRef Arch);
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
---

[PATCH] D134349: [Arm][AArch64] Make getArchFeatures to use TargetParser.def

2022-09-23 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7e1a87387209: [Arm][AArch64] Make getArchFeatures to use 
TargetParser.def (authored by danielkiss).
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Files:
  clang/test/Driver/arch.c
  clang/test/Driver/arm-cortex-cpus-1.c
  clang/test/Driver/arm-cortex-cpus-2.c
  clang/test/Driver/arm-features.c
  clang/test/Driver/arm-target-as-march-mcpu.s
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/include/llvm/Support/AArch64TargetParser.h
  llvm/include/llvm/Support/ARMTargetParser.def
  llvm/include/llvm/Support/ARMTargetParser.h
  llvm/lib/Support/AArch64TargetParser.cpp
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -483,7 +483,7 @@
   testARMArch("armv7e-m", "cortex-m4", "v7em",
   ARMBuildAttrs::CPUArch::v7E_M));
   EXPECT_TRUE(
-  testARMArch("armv8-a", "generic", "v8",
+  testARMArch("armv8-a", "generic", "v8a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(
   testARMArch("armv8.1-a", "generic", "v8.1a",
@@ -1308,7 +1308,7 @@
 }
 
 TEST(TargetParserTest, testAArch64Arch) {
-  EXPECT_TRUE(testAArch64Arch("armv8-a", "cortex-a53", "v8",
+  EXPECT_TRUE(testAArch64Arch("armv8-a", "cortex-a53", "v8a",
   ARMBuildAttrs::CPUArch::v8_A));
   EXPECT_TRUE(testAArch64Arch("armv8.1-a", "generic", "v8.1a",
   ARMBuildAttrs::CPUArch::v8_A));
Index: llvm/lib/Support/AArch64TargetParser.cpp
===
--- llvm/lib/Support/AArch64TargetParser.cpp
+++ llvm/lib/Support/AArch64TargetParser.cpp
@@ -78,36 +78,11 @@
 
 bool AArch64::getArchFeatures(AArch64::ArchKind AK,
   std::vector ) {
-  if (AK == ArchKind::ARMV8A)
-Features.push_back("+v8a");
-  if (AK == ArchKind::ARMV8_1A)
-Features.push_back("+v8.1a");
-  if (AK == ArchKind::ARMV8_2A)
-Features.push_back("+v8.2a");
-  if (AK == ArchKind::ARMV8_3A)
-Features.push_back("+v8.3a");
-  if (AK == ArchKind::ARMV8_4A)
-Features.push_back("+v8.4a");
-  if (AK == ArchKind::ARMV8_5A)
-Features.push_back("+v8.5a");
-  if (AK == AArch64::ArchKind::ARMV8_6A)
-Features.push_back("+v8.6a");
-  if (AK == AArch64::ArchKind::ARMV8_7A)
-Features.push_back("+v8.7a");
-  if (AK == AArch64::ArchKind::ARMV8_8A)
-Features.push_back("+v8.8a");
-  if (AK == AArch64::ArchKind::ARMV9A)
-Features.push_back("+v9a");
-  if (AK == AArch64::ArchKind::ARMV9_1A)
-Features.push_back("+v9.1a");
-  if (AK == AArch64::ArchKind::ARMV9_2A)
-Features.push_back("+v9.2a");
-  if (AK == AArch64::ArchKind::ARMV9_3A)
-Features.push_back("+v9.3a");
-  if(AK == AArch64::ArchKind::ARMV8R)
-Features.push_back("+v8r");
-
-  return AK != ArchKind::INVALID;
+  if (AK == ArchKind::INVALID)
+return false;
+  Features.push_back(
+  AArch64ARCHNames[static_cast(AK)].getArchFeature());
+  return true;
 }
 
 StringRef AArch64::getArchName(AArch64::ArchKind AK) {
Index: llvm/include/llvm/Support/ARMTargetParser.h
===
--- llvm/include/llvm/Support/ARMTargetParser.h
+++ llvm/include/llvm/Support/ARMTargetParser.h
@@ -216,7 +216,14 @@
   StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
 
   // Sub-Arch name.
-  StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
+  StringRef getSubArch() const {
+return getArchFeature().substr(1, SubArchLength);
+  }
+
+  // Arch Feature name.
+  StringRef getArchFeature() const {
+return StringRef(SubArchCStr, SubArchLength);
+  }
 };
 
 static const ArchNames ARCHNames[] = {
@@ -224,7 +231,7 @@
  ARCH_BASE_EXT)\
   {NAME, sizeof(NAME) - 1, \
CPU_ATTR, sizeof(CPU_ATTR) - 1, \
-   SUB_ARCH, sizeof(SUB_ARCH) - 1, \
+   "+" SUB_ARCH, sizeof(SUB_ARCH), \
ARCH_FPU, ARCH_BASE_EXT,\
ArchKind::ID, ARCH_ATTR},
 #include "llvm/Support/ARMTargetParser.def"
Index: llvm/include/llvm/Support/ARMTargetParser.def
===
--- llvm/include/llvm/Support/ARMTargetParser.def
+++ llvm/include/llvm/Support/ARMTargetParser.def
@@

[PATCH] D127812: [AArch64] Function multiversioning support added.

2022-07-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss requested changes to this revision.
danielkiss added a comment.
This revision now requires changes to proceed.

Please find the thread on the GCC mailing list here: 
https://gcc.gnu.org/pipermail/gcc/2022-July/239134.html 
Feedback there sounds positive to me.
All received feedback added to this PR.
https://github.com/ARM-software/acle/pull/211

@ilinpv Could you please update the patch accordingly?

(I'm on vacation until September, please expect slow responses.)


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[PATCH] D130145: [AArch64] Simplify BTI/PAC-RET module flags

2022-07-26 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

AutoUpgrade is added due to similar issue at a user.
LGTM.


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[PATCH] D130145: [AArch64] Simplify BTI/PAC-RET module flags

2022-07-25 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: llvm/lib/IR/AutoUpgrade.cpp:4415-4430
-// Upgrade branch protection and return address signing module flags. The
-// module flag behavior for these fields were Error and now they are Min.
-if (ID->getString() == "branch-target-enforcement" ||
-ID->getString().startswith("sign-return-address")) {
-  if (auto *Behavior =
-  mdconst::dyn_extract_or_null(Op->getOperand(0))) {
-if (Behavior->getLimitedValue() == Module::Error) {

MaskRay wrote:
> danielkiss wrote:
> > In a full LTO build the linker will complain about the mis match between 
> > the flags if one of the objects compiled with an older compiler that 
> > emitted `Module:Error` for these flags.
> The new approach doesnot emit a flag for 0 value, so there won't be an error 
> even with old bitcode files using `Error`.
older compiler could emit `Module:Error` with 0 and with this patch we emit 1 
with `min` so the linker will stop with 
`ld.lld: error: linking module flags 'branch-target-enforcement': IDs have 
conflicting behaviors in 'foo.o' and 'ld-temp.o'`

```
clang++-13 -flto=full -c foo.cpp -o foo.o
../build/bin/clang++ -flto=full -c main.cpp -o main.o 
-mbranch-protection=standard
../build/bin/clang++ -fuse-ld=lld main.o foo.o -o a.out
```



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[PATCH] D130145: [AArch64] Simplify BTI/PAC-RET module flags

2022-07-22 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: llvm/lib/IR/AutoUpgrade.cpp:4415-4430
-// Upgrade branch protection and return address signing module flags. The
-// module flag behavior for these fields were Error and now they are Min.
-if (ID->getString() == "branch-target-enforcement" ||
-ID->getString().startswith("sign-return-address")) {
-  if (auto *Behavior =
-  mdconst::dyn_extract_or_null(Op->getOperand(0))) {
-if (Behavior->getLimitedValue() == Module::Error) {

In a full LTO build the linker will complain about the mis match between the 
flags if one of the objects compiled with an older compiler that emitted 
`Module:Error` for these flags.


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[PATCH] D129135: [doc][ReleaseNotes] Document AArch64 SVE ABI fix from D127209

2022-07-05 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D127812: [AArch64] Function multiversioning support added.

2022-06-28 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

In D127812#3602688 , @aaron.ballman 
wrote:

> In D127812#3602645 , @erichkeane 
> wrote:
>
>> In D127812#3601476 , @danielkiss 
>> wrote:
>>
>>> Your understanding is correct. `target` attribute has two usage model. One 
>>> is just redefine the to be used codegen options, this is used already 
>>> widely for Arm and AArch64. The other use of the `target` attribute is the 
>>> multi versioning and the rational for the `target_version` attribute is the 
>>> easier distinction between the two usage mode, also not to break any code 
>>> out there by changing the behaviour of an attribute.
>>
>> I don't think differentiating the uses here is a good idea.  I think it 
>> would have been a GREAT idea about 10 years ago, but that ship has already 
>> sailed once GCC started using it that way however.  We should be keeping the 
>> current behavior, otherwise we're going to have a horrible mix of 
>> target/target_version working inconsistently between platforms.
>
> That largely is my concern as well. The existing behavior of `target` is just 
> that -- the existing behavior. I think deviating from that existing behavior 
> will be confusing in practice. Adding additional attributes doesn't improve 
> that confusion because users then have to know to decide between two very 
> similar attributes, which means they then need to educate themselves on the 
> differences between them. If we're going to push them towards the 
> documentation to correctly use the attribute anyway, that's basically the 
> same situation they're in today with the confusing dual behavior of `target`.

We started with the ACLE to be sure the platforms and compilers will implement 
the same for Arm targets so make the developers life easier with a consistent 
behaviour on Arm platforms. Users of the attributes anyway need to aware of the 
architecture differences. Like `-mtune` is different between Arm/AArch64 and 
x86.

I have some hope others may see the benefits of the new semantics (e.g. make 
the `"default"` optional for `target_clones` ) will be picked up by other 
architectures.


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[PATCH] D127812: [AArch64] Function multiversioning support added.

2022-06-22 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

In D127812#3599530 , @aaron.ballman 
wrote:

> In D127812#3587223 , @ilinpv wrote:
>
>> In D127812#3585249 , @erichkeane 
>> wrote:
>>
>>> I'm concerned as to the design of this addition, I don't particularly 
>>> appreciate the reasons for making 'target_clones' different, nor the 
>>> purpose for adding a new attribute instead of using 'target' for what seems 
>>> like exactly that?  IF the new spelling is THAT necessary, we perhaps don't 
>>> need a whole new attribute for it either.
>>
>> Thank you for fair concern, "target_clones" for AArch64 has different 
>> format, semantic, e.g. "default" is not required.  Therefore it diverges 
>> with X86 in these parts.
>
> Is it *necessary* that it diverges like this? (Is there some published 
> standards document you're trying to conform to, is there an implementation 
> difficulty with not diverging, something else?)

In ACLE there are a few rules/behaviour documented around what should be the 
behaviour of the "default" for example. Making for example "default" optional 
hopefully makes the adation of multi versioning seamless as possible. Compilers 
won't support from day one these attributes therefore the goal was to make the 
whole addition of a multi versioned function as less distributive as possible 
while the code is still compiled with older compilers too.

  // this is the original code
  // mandating __attribute__ ((target ("default"))) would not work with the 
today's compilers
  void foo(){}
  
  // new backward compatible code
  #ifdef __ARM_FEATURE_FUNCTION_MULTI_VERSIONING
  __attribute__ ((target_version("fancy_feature")))
  void foo(){}
  #endif

if the "default" is not mandated here, it felt not right to mandate it for the 
`target_clones` either.

>> "target" attribute has been already used and supported on AArch64 in a 
>> different sense, like target("arm"), target("dotprod"), 
>> target("branch-protection=bti"). The intention of creating new 
>> "target_version" attribute is not to overlap with that. It also has 
>> different format, mangling and semantic, e.g. treating function without 
>> attribute as "default", and option to disable attribute droping function 
>> multi versions. Do these explanations dispel your concern?
>
> Do I understand correctly that AArch64 was using an attribute named `target` 
> which does not behave like the attribute with the same name in GCC and Clang 
> on other architectures, and now you'd like to introduce a new attribute which 
> does behave like `target` but under a different name? If I have that correct, 
> I don't think that's reasonable -- there's far too much possibility for 
> confusion with that situation already, and adding a new attribute only 
> increases the confusion. I'm not certain where the technical debt came from, 
> but we shouldn't increase the burden on users here; I think `target` and 
> `target_clones` should be made to work consistently across architectures if 
> at all possible.

Your understanding is correct. `target` attribute has two usage model. One is 
just redefine the to be used codegen options, this is used already widely for 
Arm and AArch64. The other use of the `target` attribute is the multi 
versioning and the rational for the `target_version` attribute is the easier 
distinction between the two usage mode, also not to break any code out there by 
changing the behaviour of an attribute.


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[PATCH] D123493: Support the min of module flags when linking, use for AArch64 BTI/PAC-RET

2022-06-11 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

In D123493#3569025 , @MaskRay wrote:

> This behavior requires that all participating modules have the module flag. 
> In the absence of the module flag, what should be behavior be?
>
> For module flags like `"sign-return-address"`, I see that you just emit the 
> flag unconditionally (which can be zero).

Absence of the `"branch-target-enforcement" and `"sign-return-address"` means 
features are off. So the flag merger will take an existing flag and the feature 
could be turned on, which is bad.
AutoUpdater should insert the attributes with zero value if they are missing.

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[PATCH] D123493: Support the min of module flags when linking, use for AArch64 BTI/PAC-RET

2022-04-13 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb0343a38a591: Support the min of module flags when linking, 
use for AArch64 BTI/PAC-RET (authored by danielkiss).
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Files:
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  clang/test/CodeGen/aarch64-sign-return-address.c
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  llvm/include/llvm/IR/Module.h
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Linker/IRMover.cpp
  llvm/test/Bitcode/upgrade-branch-protection.ll
  llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
  llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
  llvm/test/CodeGen/AArch64/memsize-remarks.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
  llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll
  llvm/test/CodeGen/AArch64/setjmp-bti-no-enforcement.ll
  llvm/test/CodeGen/AArch64/setjmp-bti-outliner.ll
  llvm/test/CodeGen/AArch64/setjmp-bti.ll
  llvm/test/CodeGen/ARM/pacbti-module-attrs.ll
  llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
  llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
  llvm/test/CodeGen/Thumb2/bti-const-island-multiple-jump-tables.mir
  llvm/test/CodeGen/Thumb2/bti-const-island.mir
  llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll
  llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
  llvm/test/CodeGen/Thumb2/bti-jump-table.mir
  llvm/test/CodeGen/Thumb2/bti-outliner-1.ll
  llvm/test/CodeGen/Thumb2/bti-outliner-2.ll
  llvm/test/CodeGen/Thumb2/bti-outliner-cost-1.ll
  llvm/test/CodeGen/Thumb2/bti-outliner-cost-2.ll
  llvm/test/CodeGen/Thumb2/bti-pac-replace-1.mir
  llvm/test/CodeGen/Thumb2/bti-pac-replace-2.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-indirect-tail-call.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-2.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-5.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-overalign.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-unsupported-arch.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-varargs-1.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-varargs-2.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll
  llvm/test/DebugInfo/AArch64/debugline-endsequence.ll
  llvm/test/Instrumentation/InstrProfiling/debug-info-correlate-coverage.ll
  llvm/test/Instrumentation/InstrProfiling/debug-info-correlate.ll
  llvm/test/LTO/AArch64/Inputs/foo.ll
  llvm/test/LTO/AArch64/link-branch-target-enforcement.ll
  llvm/test/LTO/AArch64/lit.local.cfg
  llvm/test/Verifier/module-flags-1.ll

Index: llvm/test/Verifier/module-flags-1.ll
===
--- llvm/test/Verifier/module-flags-1.ll
+++ llvm/test/Verifier/module-flags-1.ll
@@ -45,6 +45,10 @@
 ; CHECK: invalid value for 'max' module flag (expected constant integer)
 !19 = !{i32 7, !"max", !"max"}
 
+; Check that any 'min' module flags are valid.
+; CHECK: invalid value for 'min' module flag (expected constant integer)
+!20 = !{i32 8, !"min", !"min"}
+
 ; Check that any 'require' module flags are valid.
 ; CHECK: invalid requirement on flag, flag is not present in module
 !11 = !{i32 3, !"bar", !{!"no-such-flag", i32 52}}
@@ -58,4 +62,4 @@
 
 !llvm.module.flags = !{
   !0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15,
-  !16, !17, !18, !19 }
+  !16, !17, !18, !19, !20 }
Index: llvm/test/LTO/AArch64/lit.local.cfg
===
--- /dev/null
+++ llvm/test/LTO/AArch64/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'AArch64' in config.root.targets:
+  config.unsupported = True
Index: llvm/test/LTO/AArch64/link-branch-target-enforcement.ll
===
--- /dev/null
+++ llvm/test/LTO/AArch64/link-branch-target-enforcement.ll
@@ -0,0 +1,38 @@
+; Testcase to check that module with different branch-target-enforcement can
+; be mixed.
+;
+; RUN: llvm-as %s -o %t1.bc
+; RUN: llvm-as %p/Inputs/foo.ll -o %t2.bc
+; RUN: llvm-lto -exported-symbol main \
+; RUN:  -exported-symbol foo \
+; RUN:  -filetype=obj \
+; RUN:   %t1.bc %t2.bc \
+; RUN:   -o %t1.exe 2>&1 | FileCheck --allow-empty %s
+; RUN: llvm-objdump -d %t1.exe |

[PATCH] D121707: [llvm][AArch64] Insert "bti j" after call to setjmp

2022-03-21 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

Add to the commit message `Fixes #4` to make the connection on github.

LGTM




Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:480-481
+ SDNPVariadic]>;
+
+
 def AArch64call_rvmarker: SDNode<"AArch64ISD::CALL_RVMARKER",




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[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2021-12-10 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: clang/lib/Basic/Targets/ARM.cpp:372
+  if (Arch.empty())
+return true;
+

I'd play safe and return false here.


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[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

2021-12-07 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

In D115140#3176800 , @stuij wrote:

> @danielkiss Yes that needs to be addressed, but we are doing that in another 
> patch that will (hopefully) cover all permutations of architecture and branch 
> protection values on both the cmdline and as function attributes.

sound good, Thanks!

LGTM.


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[PATCH] D115140: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT

2021-12-06 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

I think rejecting\warning the `b-key` from the command line maybe a more 
developer friendly way.


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[PATCH] D109856: [libunwind][ARM] Handle end of stack during unwind

2021-11-26 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG632acec73776: [libunwind][ARM] Handle end of stack during 
unwind (authored by danielkiss).
Herald added projects: libc++abi, libunwind.
Herald added 1 blocking reviewer(s): libc++abi.

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Files:
  libcxxabi/src/cxa_personality.cpp
  libcxxabi/test/forced_unwind3.pass.cpp
  libunwind/src/Unwind-EHABI.cpp

Index: libunwind/src/Unwind-EHABI.cpp
===
--- libunwind/src/Unwind-EHABI.cpp
+++ libunwind/src/Unwind-EHABI.cpp
@@ -187,9 +187,14 @@
   if (result != _URC_CONTINUE_UNWIND)
 return result;
 
-  if (__unw_step(reinterpret_cast(context)) != UNW_STEP_SUCCESS)
+  switch (__unw_step(reinterpret_cast(context))) {
+  case UNW_STEP_SUCCESS:
+return _URC_CONTINUE_UNWIND;
+  case UNW_STEP_END:
+return _URC_END_OF_STACK;
+  default:
 return _URC_FAILURE;
-  return _URC_CONTINUE_UNWIND;
+  }
 }
 
 // Generates mask discriminator for _Unwind_VRS_Pop, e.g. for _UVRSC_CORE /
@@ -678,12 +683,13 @@
 unwind_phase2_forced(unw_context_t *uc, unw_cursor_t *cursor,
  _Unwind_Exception *exception_object, _Unwind_Stop_Fn stop,
  void *stop_parameter) {
+  bool endOfStack = false;
   // See comment at the start of unwind_phase1 regarding VRS integrity.
   __unw_init_local(cursor, uc);
   _LIBUNWIND_TRACE_UNWINDING("unwind_phase2_force(ex_ojb=%p)",
  static_cast(exception_object));
   // Walk each frame until we reach where search phase said to stop
-  while (true) {
+  while (!endOfStack) {
 // Update info about this frame.
 unw_proc_info_t frameInfo;
 if (__unw_get_proc_info(cursor, ) != UNW_ESUCCESS) {
@@ -756,6 +762,14 @@
 // We may get control back if landing pad calls _Unwind_Resume().
 __unw_resume(cursor);
 break;
+  case _URC_END_OF_STACK:
+_LIBUNWIND_TRACE_UNWINDING("unwind_phase2_forced(ex_ojb=%p): "
+   "personality returned "
+   "_URC_END_OF_STACK",
+   (void *)exception_object);
+// Personalty routine did the step and it can't step forward.
+endOfStack = true;
+break;
   default:
 // Personality routine returned an unknown result code.
 _LIBUNWIND_TRACE_UNWINDING("unwind_phase2_forced(ex_ojb=%p): "
@@ -1133,9 +1147,14 @@
 __gnu_unwind_frame(_Unwind_Exception *exception_object,
struct _Unwind_Context *context) {
   unw_cursor_t *cursor = (unw_cursor_t *)context;
-  if (__unw_step(cursor) != UNW_STEP_SUCCESS)
+  switch (__unw_step(cursor)) {
+  case UNW_STEP_SUCCESS:
+return _URC_OK;
+  case UNW_STEP_END:
+return _URC_END_OF_STACK;
+  default:
 return _URC_FAILURE;
-  return _URC_OK;
+  }
 }
 
 #endif  // defined(_LIBUNWIND_ARM_EHABI)
Index: libcxxabi/test/forced_unwind3.pass.cpp
===
--- /dev/null
+++ libcxxabi/test/forced_unwind3.pass.cpp
@@ -0,0 +1,79 @@
+//===--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// Let's run ForcedUnwind until it reaches end of the stack, this test simulates
+// what pthread_cancel does.
+
+// UNSUPPORTED: c++03
+// UNSUPPORTED: libcxxabi-no-threads
+// UNSUPPORTED: no-exceptions
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include <__cxxabi_config.h>
+
+// TODO: dump version back to 14 once clang is updated on the CI.
+#if defined(_LIBCXXABI_ARM_EHABI) && defined(__clang__) && __clang_major__ < 15
+// _Unwind_ForcedUnwind is not available or broken before version 14.
+int main(int, char**) { return 0; }
+
+#else
+static bool destructorCalled = false;
+
+struct myClass {
+  myClass() {}
+  ~myClass() {
+assert(destructorCalled == false);
+destructorCalled = true;
+  };
+};
+
+template 
+struct Stop;
+
+template 
+struct Stop {
+  // The third argument of _Unwind_Stop_Fn is uint64_t in Itanium C++ ABI/LLVM
+  // libunwind while _Unwind_Exception_Class in libgcc.
+  typedef typename std::tuple_element<2, std::tuple>::type type;
+
+  static _Unwind_Reason_Code stop(int, _Unwind_Action actions, type, struct _Unwind_Exception*, struct _Unwind_Context*,
+  void*) {
+if (actions & _UA_END_OF_STACK) {
+  assert(destructorCalled == true);
+  exit(0);
+}
+return _URC_NO_REASON;
+  }
+};
+
+static void forced_unwind() {
+

[PATCH] D109856: [libunwind][ARM] Handle end of stack during unwind

2021-11-26 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

In D109856#3154763 , @mstorsjo wrote:

> Looks reasonable I think. Is this a deficiency in the EHABI implementation 
> only, i.e. this aspect works as it should in the regular dwarf implementation?

Yes, it works on dwarf already ( also the test pass on X86/Aarch64 ).


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[PATCH] D112430: [ARM][libunwind] add PACBTI-M support for libunwind

2021-11-15 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.

LGTM, Thanks.


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[PATCH] D51650: Implement target_clones multiversioning

2021-11-12 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: clang/lib/Sema/SemaDeclAttr.cpp:3290-3296
+  // Ensure we don't combine these with themselves, since that causes some
+  // confusing behavior.
+  if (const auto *Other = D->getAttr()) {
+S.Diag(AL.getLoc(), diag::err_disallowed_duplicate_attribute) << AL;
+S.Diag(Other->getLocation(), diag::note_conflicting_attribute);
+return;
+  }

This caused the breakage. This check could be dropped for the reland.
target attributes seems can be combined, others shouldn't.


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[PATCH] D51650: Implement target_clones multiversioning

2021-11-11 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.
This revision is now accepted and ready to land.

In D51650#3121789 , @erichkeane wrote:

> But nit made.

NIT: clang-format issues still present. Maybe you need to update your local 
clang-format.

In D51650#3121789 , @erichkeane wrote:

> For the rest of multiversioning we count on the optimizer to remove variants 
> made irrelevant, but I'm not sure opt can do anything like that yet :)

I think removing the duplicated in opt is harder than just eliminate them here. 
At the end maybe the function does not need ifunc.

LGTM

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[PATCH] D51650: Implement target_clones multiversioning

2021-11-10 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

Thanks for the rebase!

Looks got to me,

`-march` may make the default same as one of the clone, in this case maybe we 
don't need to create two versions of the function. This could be solved later 
IMHO.




Comment at: clang/lib/Sema/SemaDecl.cpp:10662
+  return false;
+  break;
+}




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[PATCH] D51650: Implement target_clones multiversioning

2021-11-05 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

In D51650#3096487 , @erichkeane wrote:

> This needs rebasing/probably some cleanup, plus code review.  If you have 
> active/proficient CFE code reviewers who could take a look, I'd be willing to 
> spend some time rebasing.

Thanks you, I will help with the review and ask around here for more eyes.


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[PATCH] D112421: [clang][ARM] PACBTI-M frontend support

2021-11-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:134-135
  StringRef ) const {
-  llvm::AArch64::ParsedBranchProtection PBP;
-  if (!llvm::AArch64::parseBranchProtection(Spec, PBP, Err))
+  llvm::ARM::ParsedBranchProtection PBP;
+  if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
 return false;

aaron.ballman wrote:
> chill wrote:
> > vhscampos wrote:
> > > aaron.ballman wrote:
> > > > This change surprises me. Why should AArch64TargetInfo prefer calling 
> > > > into ARM instead?
> > > Since that particular function ended up identical in both ARM and 
> > > AArch64, we removed the AArch64 specific function and kept only one under 
> > > ARM. You can spot the removal further down the patch.
> > > 
> > > The ARM namespace under ARMTargetParser.h already had code used in 
> > > AArch64TargetParser, so we did not introduce new cross dependencies.
> > It's the unfortunate overload of "ARM" used to denote the backend and the 
> > organisation.
> Ah, that's good to know, thank you for the explanation. (And yeah, that is an 
> unfortunate overload of the term.)
Wondering will this link when the `LLVM_TARGETS_TO_BUILD` does not contains ARM 
but AArch64?


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[PATCH] D51650: Implement target_clones multiversioning

2021-10-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

Hi @erichkeane,

At Arm we are going to add the multiversioning support for Arm targets[1]. It 
would be nice to land this change because we could build top of it.
Please let me know how can I help.

[1]. https://github.com/ARM-software/acle/pull/21


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[PATCH] D112430: [ARM][libunwind] add PACBTI-M support for libunwind

2021-10-25 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: libunwind/src/Registers.hpp:2245-2246
 
+  if (regNum == UNW_ARM_RA_AUTH_CODE)
+return true;
+

Maybe we could gate this on __ARM_FEATURE_PAUTH because it won't work anyway 
without the feature enabled for libunwind.



Comment at: libunwind/src/Registers.hpp:2274-2275
 
+  if (regNum == UNW_ARM_RA_AUTH_CODE)
+return _pseudo_registers.__pac;
+

ditto, maybe better to run into a `_LIBUNWIND_ABORT` instead debugging a 
silently skipping the authentication.


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[PATCH] D100546: [ARM][AArch64] SLSHardening: make non-comdat thunks possible

2021-05-20 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
danielkiss marked an inline comment as done.
Closed by commit rG801ab71032e1: [ARM][AArch64] SLSHardening: make non-comdat 
thunks possible (authored by danielkiss).
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Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/ARM.cpp
  clang/test/Driver/sls-hardening-options.c
  llvm/include/llvm/CodeGen/IndirectThunks.h
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/ARM/ARM.td
  llvm/lib/Target/ARM/ARMSLSHardening.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll
  llvm/test/CodeGen/ARM/speculation-hardening-sls.ll

Index: llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
===
--- llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
+++ llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
@@ -1,15 +1,23 @@
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,ISBDSB -dump-input-context=100
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB -dump-input-context=100
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,SB -dump-input-context=100
-; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,SB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,HARDEN-COMDAT,ISBDSB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,HARDEN-COMDAT,ISBDSB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,HARDEN-COMDAT,SB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,HARDEN-COMDAT,SB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=harden-sls-nocomdat -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,HARDEN-COMDAT-OFF,ISBDSB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=harden-sls-nocomdat -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,HARDEN-COMDAT-OFF,ISBDSB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=harden-sls-nocomdat -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,HARDEN-COMDAT-OFF,SB -dump-input-context=100
+; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=harden-sls-nocomdat -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,HARDEN-COMDAT-OFF,SB -dump-input-context=100
 ; RUN: llc -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,NOHARDENARM -dump-input-context=100
 ; RUN: llc -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,NOHARDENTHUMB
-; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,ISBDSB
-; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB
+; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,HARDEN-COMDAT,ISBDSB
+; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr

[PATCH] D93428: [AArch64] Add bti note property when compiling asm files with -mbranch-protection=bti

2020-12-17 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

In D93428#2461343 , @apazos wrote:

> Thanks Daniel for the explanation.

No problem at all.

In D93428#2461343 , @apazos wrote:

> Was the support added for GNU assembler as well? Is it the same flag name?

Not yet, I requested the same flag from our GNU team when the flag is added to 
Clang.


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[PATCH] D93428: [AArch64] Add bti note property when compiling asm files with -mbranch-protection=bti

2020-12-17 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

> Is there a reason why assembly files have a different flag (i.e. 
> -mmark-bti-property) to create the .note.gnu.property with the BTI entry?

In assembly the compiler can't guarantee the landing pads are in place, 
therefore it doesn't add it automatically.
The original concept was this the developers should add the landing pads 
wherever needed and by adding the note they mark the file is compatible with 
BTI.
After adding BTI to many assembly code it was clear the note is error prone and 
cumbersome to handle and I thing it provides zero protection against regression 
issues , so the `-mmark-bti-property` is introduced. 
The developers still should add the landing pads but optionally they could mark 
the files in the build system instead of the assembly files. 
The worry is if the assembly file would be marked automatically the produces 
binary probably won't run correctly.


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[PATCH] D93428: [AArch64] Add bti note property when compiling asm files with -mbranch-protection=bti

2020-12-17 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

The `.note.gnu.property` is already generated when C/C++ files are compiled 
with `-mbranch-protection=bti`.  
`-mmark-bti-property` is only for assembly file where the `.note.gnu.property` 
should be added manually otherwise.

Do you have any reproducer where C/C++ behaves unexpectedly?


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[PATCH] D89834: FileManager: Improve the FileEntryRef API and customize its OptionalStorage

2020-10-30 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.
Herald added a subscriber: ormris.



Comment at: clang/include/clang/Basic/FileEntry.h:186
+
+  constexpr bool hasValue() const noexcept {
+return MaybeRef.hasOptionalValue();

This broke the build, `constexpr` could be dropped IMHO.
FileEntry.h(186):  error C3615: constexpr function 
'llvm::optional_detail::OptionalStorage::hasValue' 
cannot result in a constant expression
FileEntry.h(187): note: failure was caused by call of undefined function or one 
not declared 'constexpr'
FileEntry.h(187): note: see usage of 'clang::FileEntryRef::hasOptionalValue'


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[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-09-28 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa48f6079f288: [AArch64] Generate .note.gnu.property based on 
module flags. (authored by danielkiss).

Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  %r = tail call i32 @g()
-  ret i32 %r
-}
-
-declare dso_local i32 @g()
-
-attributes #0 = { "branch-target-enforcement"="true" }
-
-; Declarations don't prevent setting BTI
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
-
-; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "branch-target-enforcement"="true" }
-
-; No common attribute, no note section
-; ASM: warning: not setting BTI in feature flags
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="none" }
-
-; No common attribute, no note section
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "branch-target-enforcement"="true" "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="all" }
-
-; Only the common atttribute (PAC)
-; ASM: warning: not setting BTI in feature flags
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	2
-
-; OBJ: Properties: aarch64 feature: PAC
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -1,7 +1,5 @@
 ; RUN: llc -mtriple=aarch64-linux %s   -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
 
 define dso_local i32 @f() #0 {
 entry:
@@ -17,9 +15,12 @@
 
 attributes #1 = { "branch-target-enforcement"="true" }
 
-; Only the common atttribute (BTI)
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1

[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-09-25 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 294284.

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Files:
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  %r = tail call i32 @g()
-  ret i32 %r
-}
-
-declare dso_local i32 @g()
-
-attributes #0 = { "branch-target-enforcement"="true" }
-
-; Declarations don't prevent setting BTI
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
-
-; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "branch-target-enforcement"="true" }
-
-; No common attribute, no note section
-; ASM: warning: not setting BTI in feature flags
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="none" }
-
-; No common attribute, no note section
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "branch-target-enforcement"="true" "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="all" }
-
-; Only the common atttribute (PAC)
-; ASM: warning: not setting BTI in feature flags
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	2
-
-; OBJ: Properties: aarch64 feature: PAC
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -1,7 +1,5 @@
 ; RUN: llc -mtriple=aarch64-linux %s   -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
 
 define dso_local i32 @f() #0 {
 entry:
@@ -17,9 +15,12 @@
 
 attributes #1 = { "branch-target-enforcement"="true" }
 
-; Only the common atttribute (BTI)
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
+!llvm.module.flags = !{!0, !1, !2, !3}
 
-; OBJ: Properties: aarch64 feature: BTI
+!0 = !{i32 1, !"branch-target-enforcement", i32 0}
+!1 = !{i32 1, !"sign-return-address", i32 0}
+!2 = !{i32 1,

[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-09-24 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2a96f47c5ffc: [AArch64] __builtin_return_address for PAuth. 
(authored by danielkiss).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75044/new/

https://reviews.llvm.org/D75044

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
  llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
  llvm/test/CodeGen/AArch64/arm64_32.ll
  llvm/test/CodeGen/AArch64/returnaddr.ll

Index: llvm/test/CodeGen/AArch64/returnaddr.ll
===
--- llvm/test/CodeGen/AArch64/returnaddr.ll
+++ llvm/test/CodeGen/AArch64/returnaddr.ll
@@ -3,6 +3,7 @@
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
 ; CHECK-LABEL: rt0:
+; CHECK: hint #7
 ; CHECK: mov x0, x30
   %0 = tail call i8* @llvm.returnaddress(i32 0)
   ret i8* %0
@@ -13,7 +14,9 @@
 ; CHECK-LABEL: rt2:
 ; CHECK: ldr x[[reg:[0-9]+]], [x29]
 ; CHECK: ldr x[[reg]], [x[[reg]]]
-; CHECK: ldr x0, [x[[reg]], #8]
+; CHECK: ldr x30, [x[[reg]], #8]
+; CHECK: hint #7
+; CHECK: mov x0, x30
   %0 = tail call i8* @llvm.returnaddress(i32 2)
   ret i8* %0
 }
Index: llvm/test/CodeGen/AArch64/arm64_32.ll
===
--- llvm/test/CodeGen/AArch64/arm64_32.ll
+++ llvm/test/CodeGen/AArch64/arm64_32.ll
@@ -253,7 +253,9 @@
 define i8* @test_deep_returnaddr() {
 ; CHECK-LABEL: test_deep_returnaddr:
 ; CHECK: ldr x[[FRAME_REC:[0-9]+]], [x29]
-; CHECK-OPT: ldr x0, [x[[FRAME_REC]], #8]
+; CHECK-OPT: ldr x30, [x[[FRAME_REC]], #8]
+; CHECK-OPT: hint #7
+; CHECK-OPT: mov x0, x30
 ; CHECK-FAST: ldr [[TMP:x[0-9]+]], [x[[FRAME_REC]], #8]
 ; CHECK-FAST: and x0, [[TMP]], #0x
   %val = call i8* @llvm.returnaddress(i32 1)
Index: llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
===
--- llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
+++ llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
@@ -3,6 +3,7 @@
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
 ; CHECK-LABEL: rt0:
+; CHECK: hint #7
 ; CHECK: mov x0, x30
 ; CHECK: ret
   %0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -16,7 +17,9 @@
 ; CHECK: mov x29, sp
 ; CHECK: ldr x[[REG:[0-9]+]], [x29]
 ; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]]
-; CHECK: ldr x0, [x[[REG2]], #8]
+; CHECK: ldr x30, [x[[REG2]], #8]
+; CHECK: hint #7
+; CHECK: mov x0, x30
 ; CHECK: ldp x29, x30, [sp], #16
 ; CHECK: ret
   %0 = tail call i8* @llvm.returnaddress(i32 2)
Index: llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
+
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; pointer authentication code from the pointer.
+; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
+; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
+; On Armv8.3-A and onwards XPACI is available so use that instead.
+
+define i8* @ra0() nounwind readnone {
+entry:
+; CHECK-LABEL: ra0:
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint#7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: ret
+; CHECKV83:   str x30, [sp, #-16]!
+; CHECKV83-NEXT:  xpaci   x30
+; CHECKV83-NEXT:  mov x0, x30
+; CHECKV83-NEXT:  ldr x30, [sp], #16
+; CHECKV83-NEXT:  ret
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @ra1() nounwind readnone #0 {
+entry:
+; CHECK-LABEL: ra1:
+; CHECK:  hint#25
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint#7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: hint#29
+; CHECK-NEXT: ret
+; CHECKV83:   paciasp
+; CHECKV83-NEXT:  str x30, [sp, #-16]!
+; CHECKV83-NEXT:  xpaci   x30
+; CHECKV83-NEXT:  mov x0, x30
+; CHECKV83-NEXT:  ldr x30, [sp], #16
+; CHECKV83-NEXT:  retaa
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+attributes #0 = { "sign-return-address"="all" }
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6628,17 +6628,34 @@
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
   unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
+  SDValue ReturnAddress;
   if (Depth)

[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-09-24 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

@chill ping.


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[PATCH] D81930: [AArch64] Add -mmark-bti-property flag.

2020-09-16 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG95e43f84b7b9: [AArch64] Add -mmark-bti-property flag. 
(authored by danielkiss).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/arm64-markbti.S
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h

Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
@@ -33,6 +33,9 @@
   /// Emit contents of constant pool for the current section.
   void emitCurrentConstantPool();
 
+  /// Callback used to implement the .note.gnu.property section.
+  void emitNoteSection(unsigned Flags);
+
   /// Callback used to implement the .inst directive.
   virtual void emitInst(uint32_t Inst);
 
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
@@ -11,12 +11,23 @@
 //===--===//
 
 #include "AArch64TargetStreamer.h"
+#include "AArch64MCAsmInfo.h"
+#include "AArch64Subtarget.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/ConstantPools.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
+static cl::opt MarkBTIProperty(
+"aarch64-mark-bti-property", cl::Hidden,
+cl::desc("Add .note.gnu.property with BTI to assembly files"),
+cl::init(false));
+
 //
 // AArch64TargetStreamer Implemenation
 //
@@ -37,8 +48,50 @@
   ConstantPools->emitForCurrentSection(Streamer);
 }
 
-// finish() - write out any non-empty assembler constant pools.
-void AArch64TargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
+// finish() - write out any non-empty assembler constant pools and
+//   write out note.gnu.properties if need.
+void AArch64TargetStreamer::finish() {
+  ConstantPools->emitAll(Streamer);
+
+  if (MarkBTIProperty)
+emitNoteSection(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
+}
+
+void AArch64TargetStreamer::emitNoteSection(unsigned Flags) {
+  if (Flags == 0)
+return;
+
+  MCStreamer  = getStreamer();
+  MCContext  = OutStreamer.getContext();
+  // Emit a .note.gnu.property section with the flags.
+  MCSectionELF *Nt = Context.getELFSection(".note.gnu.property", ELF::SHT_NOTE,
+   ELF::SHF_ALLOC);
+  if (Nt->isRegistered()) {
+SMLoc Loc;
+Context.reportWarning(
+Loc,
+"The .note.gnu.property is not emitted because it is already present.");
+return;
+  }
+  MCSection *Cur = OutStreamer.getCurrentSectionOnly();
+  OutStreamer.SwitchSection(Nt);
+
+  // Emit the note header.
+  OutStreamer.emitValueToAlignment(Align(8).value());
+  OutStreamer.emitIntValue(4, 4); // data size for "GNU\0"
+  OutStreamer.emitIntValue(4 * 4, 4); // Elf_Prop size
+  OutStreamer.emitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4);
+  OutStreamer.emitBytes(StringRef("GNU", 4)); // note name
+
+  // Emit the PAC/BTI properties.
+  OutStreamer.emitIntValue(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND, 4);
+  OutStreamer.emitIntValue(4, 4); // data size
+  OutStreamer.emitIntValue(Flags, 4); // data
+  OutStreamer.emitIntValue(0, 4); // pad
+
+  OutStreamer.endSection(Nt);
+  OutStreamer.SwitchSection(Cur);
+}
 
 void AArch64TargetStreamer::emitInst(uint32_t Inst) {
   char Buffer[4];
Index: llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
===
--- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -223,26 +223,9 @@
 return;
 
   // Emit a .note.gnu.property section with the flags.
-  MCSection *Cur = OutStreamer->getCurrentSectionOnly();
-  MCSection *Nt = MMI->getContext().getELFSection(
-  ".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
-  OutStreamer->SwitchSection(Nt);
-
-  // Emit the note header.
-  emitAlignment(Align(8));
-  OutStreamer->emitInt32(4); // data size for "GNU\0"
-  OutStreamer->emitInt32(4 * 4); // Elf_Prop size
-  OutStreamer->emitInt32(ELF::NT_GNU_PROPERTY_TYPE_0);
-  OutStreamer->emitBytes(StringRef("GNU", 4)); // note name
-
-  // Emit the PAC/BTI properties.
-  OutStreamer->emitInt32(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND);
-  OutStreamer->emitInt32(4); // data

[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-09-16 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 292250.
danielkiss added a comment.

Rebased top of D85649 .


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Files:
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  %r = tail call i32 @g()
-  ret i32 %r
-}
-
-declare dso_local i32 @g()
-
-attributes #0 = { "branch-target-enforcement"="true" }
-
-; Declarations don't prevent setting BTI
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
-
-; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "branch-target-enforcement"="true" }
-
-; No common attribute, no note section
-; ASM: warning: not setting BTI in feature flags
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="none" }
-
-; No common attribute, no note section
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "branch-target-enforcement"="true" "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="all" }
-
-; Only the common atttribute (PAC)
-; ASM: warning: not setting BTI in feature flags
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	2
-
-; OBJ: Properties: aarch64 feature: PAC
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -1,7 +1,5 @@
 ; RUN: llc -mtriple=aarch64-linux %s   -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
 
 define dso_local i32 @f() #0 {
 entry:
@@ -17,9 +15,5 @@
 
 attributes #1 = { "branch-target-enforcement"="true" }
 
-; Only the common atttribute (BTI)
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
-
-; OBJ: Properties: aarch64 feature: BTI
+; Note is not emited if module has no properties
+; ASM-NOT:

[PATCH] D81930: [AArch64] Add -mmark-bti-property flag.

2020-09-15 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss marked 4 inline comments as done.
danielkiss added a comment.

@nickdesaulniers Thanks for the review, comments are addressed.


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[PATCH] D81930: [AArch64] Add -mmark-bti-property flag.

2020-09-15 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 291922.

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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/arm64-markbti.S
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h

Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
@@ -33,6 +33,9 @@
   /// Emit contents of constant pool for the current section.
   void emitCurrentConstantPool();
 
+  /// Callback used to implement the .note.gnu.property section.
+  void emitNoteSection(unsigned Flags);
+
   /// Callback used to implement the .inst directive.
   virtual void emitInst(uint32_t Inst);
 
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
@@ -11,12 +11,23 @@
 //===--===//
 
 #include "AArch64TargetStreamer.h"
+#include "AArch64MCAsmInfo.h"
+#include "AArch64Subtarget.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/ConstantPools.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
+static cl::opt MarkBTIProperty(
+"aarch64-mark-bti-property", cl::Hidden,
+cl::desc("Add .note.gnu.property with BTI to assembly files"),
+cl::init(false));
+
 //
 // AArch64TargetStreamer Implemenation
 //
@@ -37,8 +48,50 @@
   ConstantPools->emitForCurrentSection(Streamer);
 }
 
-// finish() - write out any non-empty assembler constant pools.
-void AArch64TargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
+// finish() - write out any non-empty assembler constant pools and
+//   write out note.gnu.properties if need.
+void AArch64TargetStreamer::finish() {
+  ConstantPools->emitAll(Streamer);
+
+  if (MarkBTIProperty)
+emitNoteSection(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
+}
+
+void AArch64TargetStreamer::emitNoteSection(unsigned Flags) {
+  if (Flags == 0)
+return;
+
+  MCStreamer  = getStreamer();
+  MCContext  = OutStreamer.getContext();
+  // Emit a .note.gnu.property section with the flags.
+  MCSectionELF *Nt = Context.getELFSection(".note.gnu.property", ELF::SHT_NOTE,
+   ELF::SHF_ALLOC);
+  if (Nt->isRegistered()) {
+SMLoc Loc;
+Context.reportWarning(
+Loc,
+"The .note.gnu.property is not emitted because it is already present.");
+return;
+  }
+  MCSection *Cur = OutStreamer.getCurrentSectionOnly();
+  OutStreamer.SwitchSection(Nt);
+
+  // Emit the note header.
+  OutStreamer.emitValueToAlignment(Align(8).value());
+  OutStreamer.emitIntValue(4, 4); // data size for "GNU\0"
+  OutStreamer.emitIntValue(4 * 4, 4); // Elf_Prop size
+  OutStreamer.emitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4);
+  OutStreamer.emitBytes(StringRef("GNU", 4)); // note name
+
+  // Emit the PAC/BTI properties.
+  OutStreamer.emitIntValue(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND, 4);
+  OutStreamer.emitIntValue(4, 4); // data size
+  OutStreamer.emitIntValue(Flags, 4); // data
+  OutStreamer.emitIntValue(0, 4); // pad
+
+  OutStreamer.endSection(Nt);
+  OutStreamer.SwitchSection(Cur);
+}
 
 void AArch64TargetStreamer::emitInst(uint32_t Inst) {
   char Buffer[4];
Index: llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
===
--- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -223,26 +223,9 @@
 return;
 
   // Emit a .note.gnu.property section with the flags.
-  MCSection *Cur = OutStreamer->getCurrentSectionOnly();
-  MCSection *Nt = MMI->getContext().getELFSection(
-  ".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
-  OutStreamer->SwitchSection(Nt);
-
-  // Emit the note header.
-  emitAlignment(Align(8));
-  OutStreamer->emitInt32(4); // data size for "GNU\0"
-  OutStreamer->emitInt32(4 * 4); // Elf_Prop size
-  OutStreamer->emitInt32(ELF::NT_GNU_PROPERTY_TYPE_0);
-  OutStreamer->emitBytes(StringRef("GNU", 4)); // note name
-
-  // Emit the PAC/BTI properties.
-  OutStreamer->emitInt32(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND);
-  OutStreamer->emitInt32(4); // data size
-  OutStreamer->emitInt32(Flags); // data
-  OutStreamer->emitInt32(0); // pad
-
-  OutStreamer->endSection(Nt);
-  OutStreamer->SwitchSection(Cur);
+  if

[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-09-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

@chill Could you check the latest update? I think it should be submitted with 
D84502  together.


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[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-08-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 288775.
danielkiss edited the summary of this revision.
danielkiss added a comment.

Sync with D85649 .


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Files:
  clang/lib/CodeGen/CodeGenModule.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  %r = tail call i32 @g()
-  ret i32 %r
-}
-
-declare dso_local i32 @g()
-
-attributes #0 = { "branch-target-enforcement" }
-
-; Declarations don't prevent setting BTI
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
-
-; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "branch-target-enforcement" }
-
-; No common attribute, no note section
-; ASM: warning: not setting BTI in feature flags
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="none" }
-
-; No common attribute, no note section
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="all" }
-
-; Only the common atttribute (PAC)
-; ASM: warning: not setting BTI in feature flags
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	2
-
-; OBJ: Properties: aarch64 feature: PAC
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -1,25 +1,12 @@
 ; RUN: llc -mtriple=aarch64-linux %s   -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
 
 define dso_local i32 @f() #0 {
 entry:
   ret i32 0
 }
 
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
 attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
 
-attributes #1 = { "branch-target-enforcement" }
-
-; Only the common

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-08-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss abandoned this revision.
danielkiss added a comment.

Abandoning in favour of D85649 .


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[PATCH] D81930: [AArch64] Add -mmark-bti-property flag.

2020-08-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 288765.
danielkiss marked an inline comment as done.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81930/new/

https://reviews.llvm.org/D81930

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/arm64-markbti.S
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h

Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
@@ -36,6 +36,9 @@
   /// Callback used to implement the .inst directive.
   virtual void emitInst(uint32_t Inst);
 
+  /// Callback used to implement the .note.gnu.property section.
+  virtual void emitNoteSection(unsigned Flags);
+
   virtual void EmitARM64WinCFIAllocStack(unsigned Size) {}
   virtual void EmitARM64WinCFISaveFPLR(int Offset) {}
   virtual void EmitARM64WinCFISaveFPLRX(int Offset) {}
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
@@ -11,12 +11,23 @@
 //===--===//
 
 #include "AArch64TargetStreamer.h"
+#include "AArch64MCAsmInfo.h"
+#include "AArch64Subtarget.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/ConstantPools.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
+static cl::opt MarkBTIProperty(
+"aarch64-mark-bti-property", cl::Hidden,
+cl::desc("Add .note.gnu.property with BTI to assembly files"),
+cl::init(false));
+
 //
 // AArch64TargetStreamer Implemenation
 //
@@ -37,8 +48,52 @@
   ConstantPools->emitForCurrentSection(Streamer);
 }
 
-// finish() - write out any non-empty assembler constant pools.
-void AArch64TargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
+// finish() - write out any non-empty assembler constant pools and
+//   write out note.gnu.properties if need.
+void AArch64TargetStreamer::finish() {
+  ConstantPools->emitAll(Streamer);
+
+  if (MarkBTIProperty) {
+emitNoteSection(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
+  }
+}
+
+void AArch64TargetStreamer::emitNoteSection(unsigned Flags) {
+  if (Flags == 0) {
+return;
+  }
+  MCStreamer  = getStreamer();
+  MCContext  = OutStreamer.getContext();
+  // Emit a .note.gnu.property section with the flags.
+  MCSection *Cur = OutStreamer.getCurrentSectionOnly();
+  MCSectionELF *Nt = Context.getELFSection(".note.gnu.property", ELF::SHT_NOTE,
+   ELF::SHF_ALLOC);
+  if (Nt->isRegistered()) {
+SMLoc Loc;
+Context.reportWarning(
+Loc,
+"The .note.gnu.property is not emitted because it is already present.");
+return;
+  }
+
+  OutStreamer.SwitchSection(Nt);
+
+  // Emit the note header.
+  OutStreamer.emitValueToAlignment(Align(8).value());
+  OutStreamer.emitIntValue(4, 4); // data size for "GNU\0"
+  OutStreamer.emitIntValue(4 * 4, 4); // Elf_Prop size
+  OutStreamer.emitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4);
+  OutStreamer.emitBytes(StringRef("GNU", 4)); // note name
+
+  // Emit the PAC/BTI properties.
+  OutStreamer.emitIntValue(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND, 4);
+  OutStreamer.emitIntValue(4, 4); // data size
+  OutStreamer.emitIntValue(Flags, 4); // data
+  OutStreamer.emitIntValue(0, 4); // pad
+
+  OutStreamer.endSection(Nt);
+  OutStreamer.SwitchSection(Cur);
+}
 
 void AArch64TargetStreamer::emitInst(uint32_t Inst) {
   char Buffer[4];
Index: llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
===
--- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -221,26 +221,9 @@
 return;
 
   // Emit a .note.gnu.property section with the flags.
-  MCSection *Cur = OutStreamer->getCurrentSectionOnly();
-  MCSection *Nt = MMI->getContext().getELFSection(
-  ".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
-  OutStreamer->SwitchSection(Nt);
-
-  // Emit the note header.
-  emitAlignment(Align(8));
-  OutStreamer->emitInt32(4); // data size for "GNU\0"
-  OutStreamer->emitInt32(4 * 4); // Elf_Prop size
-  OutStreamer->emitInt32(ELF::NT_GNU_PROPERTY_TYPE_0);
-  OutStreamer->emitBytes(StringRef("GNU", 4)); // note name
-
-  // Emit the PAC/BTI properties.
-  OutStreamer->emitInt32(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND);
-  OutStreamer->emitInt32(4); // data size
-

[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-08-27 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 288275.
danielkiss added a comment.

updating tests too. check-llvm, check-clang passes.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75044/new/

https://reviews.llvm.org/D75044

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
  llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
  llvm/test/CodeGen/AArch64/arm64_32.ll
  llvm/test/CodeGen/AArch64/returnaddr.ll

Index: llvm/test/CodeGen/AArch64/returnaddr.ll
===
--- llvm/test/CodeGen/AArch64/returnaddr.ll
+++ llvm/test/CodeGen/AArch64/returnaddr.ll
@@ -3,6 +3,7 @@
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
 ; CHECK-LABEL: rt0:
+; CHECK: hint #7
 ; CHECK: mov x0, x30
   %0 = tail call i8* @llvm.returnaddress(i32 0)
   ret i8* %0
@@ -13,7 +14,9 @@
 ; CHECK-LABEL: rt2:
 ; CHECK: ldr x[[reg:[0-9]+]], [x29]
 ; CHECK: ldr x[[reg]], [x[[reg]]]
-; CHECK: ldr x0, [x[[reg]], #8]
+; CHECK: ldr x30, [x[[reg]], #8]
+; CHECK: hint #7
+; CHECK: mov x0, x30
   %0 = tail call i8* @llvm.returnaddress(i32 2)
   ret i8* %0
 }
Index: llvm/test/CodeGen/AArch64/arm64_32.ll
===
--- llvm/test/CodeGen/AArch64/arm64_32.ll
+++ llvm/test/CodeGen/AArch64/arm64_32.ll
@@ -253,7 +253,9 @@
 define i8* @test_deep_returnaddr() {
 ; CHECK-LABEL: test_deep_returnaddr:
 ; CHECK: ldr x[[FRAME_REC:[0-9]+]], [x29]
-; CHECK-OPT: ldr x0, [x[[FRAME_REC]], #8]
+; CHECK-OPT: ldr x30, [x[[FRAME_REC]], #8]
+; CHECK-OPT: hint #7
+; CHECK-OPT: mov x0, x30
 ; CHECK-FAST: ldr [[TMP:x[0-9]+]], [x[[FRAME_REC]], #8]
 ; CHECK-FAST: and x0, [[TMP]], #0x
   %val = call i8* @llvm.returnaddress(i32 1)
Index: llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
===
--- llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
+++ llvm/test/CodeGen/AArch64/arm64-returnaddr.ll
@@ -3,6 +3,7 @@
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
 ; CHECK-LABEL: rt0:
+; CHECK: hint #7
 ; CHECK: mov x0, x30
 ; CHECK: ret
   %0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -16,7 +17,9 @@
 ; CHECK: mov x29, sp
 ; CHECK: ldr x[[REG:[0-9]+]], [x29]
 ; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]]
-; CHECK: ldr x0, [x[[REG2]], #8]
+; CHECK: ldr x30, [x[[REG2]], #8]
+; CHECK: hint #7
+; CHECK: mov x0, x30
 ; CHECK: ldp x29, x30, [sp], #16
 ; CHECK: ret
   %0 = tail call i8* @llvm.returnaddress(i32 2)
Index: llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
+
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; pointer authentication code from the pointer.
+; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
+; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
+; On Armv8.3-A and onwards XPACI is available so use that instead.
+
+define i8* @ra0() nounwind readnone {
+entry:
+; CHECK-LABEL: ra0:
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint#7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: ret
+; CHECKV83:   str x30, [sp, #-16]!
+; CHECKV83-NEXT:  xpaci   x30
+; CHECKV83-NEXT:  mov x0, x30
+; CHECKV83-NEXT:  ldr x30, [sp], #16
+; CHECKV83-NEXT:  ret
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @ra1() nounwind readnone #0 {
+entry:
+; CHECK-LABEL: ra1:
+; CHECK:  hint#25
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint#7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: hint#29
+; CHECK-NEXT: ret
+; CHECKV83:   paciasp
+; CHECKV83-NEXT:  str x30, [sp, #-16]!
+; CHECKV83-NEXT:  xpaci   x30
+; CHECKV83-NEXT:  mov x0, x30
+; CHECKV83-NEXT:  ldr x30, [sp], #16
+; CHECKV83-NEXT:  retaa
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+attributes #0 = { "sign-return-address"="all" }
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6469,17 +6469,34 @@
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
   unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
+  SDValue ReturnAddress;
   if (Depth) {
 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
 SDValue Offset =

[PATCH] D81930: [AArch64] Add -mmark-bti-property flag.

2020-08-13 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss marked an inline comment as done.
danielkiss added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64.td:352
 
+def FeatureEmitNoteBTIProperty : SubtargetFeature<"markbtiproperty", 
"MarkBTIProperty",
+"true", "Emit .note.gnu.property for Branch Target Identification" >;

chill wrote:
> No, this is an abuse of subtarget features. Subtarget features represent 
> characteristics of the chip, they shouldn't be used to pass arbitrary bits of 
> information.
> Possible alternatives - `TargetOptions` (cf. 
> `BackendUtil.cpp:initTargetOptions()`) or
> LLVM command-line arguments (cf. `BackendUtil.cpp:setCommandLineOpts()`.
Thanks, now I learned how to pass flags across layers, that was not clear at 
the first time.


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[PATCH] D81930: [AArch64] Add -mmark-bti-property flag.

2020-08-13 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 285492.
danielkiss added a comment.

Fix review comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81930/new/

https://reviews.llvm.org/D81930

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/arm64-markbti.S
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h

Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
@@ -36,6 +36,9 @@
   /// Callback used to implement the .inst directive.
   virtual void emitInst(uint32_t Inst);
 
+  /// Callback used to implement the .note.gnu.property section.
+  virtual void emitNoteSection(unsigned Flags);
+
   virtual void EmitARM64WinCFIAllocStack(unsigned Size) {}
   virtual void EmitARM64WinCFISaveFPLR(int Offset) {}
   virtual void EmitARM64WinCFISaveFPLRX(int Offset) {}
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
@@ -11,8 +11,13 @@
 //===--===//
 
 #include "AArch64TargetStreamer.h"
+#include "AArch64MCAsmInfo.h"
+#include "AArch64Subtarget.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/ConstantPools.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 using namespace llvm;
@@ -37,8 +42,56 @@
   ConstantPools->emitForCurrentSection(Streamer);
 }
 
-// finish() - write out any non-empty assembler constant pools.
-void AArch64TargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
+// finish() - write out any non-empty assembler constant pools and
+//   write out note.gnu.properties if need.
+void AArch64TargetStreamer::finish() {
+  ConstantPools->emitAll(Streamer);
+
+  MCContext  = getStreamer().getContext();
+  const AArch64MCAsmInfoELF *MCAI =
+  static_cast(Context.getAsmInfo());
+
+  if (MCAI->EmitBTIMarking) {
+emitNoteSection(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
+  }
+}
+
+void AArch64TargetStreamer::emitNoteSection(unsigned Flags) {
+  if (Flags == 0) {
+return;
+  }
+  MCStreamer  = getStreamer();
+  MCContext  = OutStreamer.getContext();
+  // Emit a .note.gnu.property section with the flags.
+  MCSection *Cur = OutStreamer.getCurrentSectionOnly();
+  MCSectionELF *Nt = Context.getELFSection(".note.gnu.property", ELF::SHT_NOTE,
+   ELF::SHF_ALLOC);
+  if (Nt->isRegistered()) {
+SMLoc Loc;
+Context.reportWarning(
+Loc,
+"The .note.gnu.property is not emitted because it is already present.");
+return;
+  }
+
+  OutStreamer.SwitchSection(Nt);
+
+  // Emit the note header.
+  OutStreamer.emitValueToAlignment(Align(8).value());
+  OutStreamer.emitIntValue(4, 4); // data size for "GNU\0"
+  OutStreamer.emitIntValue(4 * 4, 4); // Elf_Prop size
+  OutStreamer.emitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4);
+  OutStreamer.emitBytes(StringRef("GNU", 4)); // note name
+
+  // Emit the PAC/BTI properties.
+  OutStreamer.emitIntValue(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND, 4);
+  OutStreamer.emitIntValue(4, 4); // data size
+  OutStreamer.emitIntValue(Flags, 4); // data
+  OutStreamer.emitIntValue(0, 4); // pad
+
+  OutStreamer.endSection(Nt);
+  OutStreamer.SwitchSection(Cur);
+}
 
 void AArch64TargetStreamer::emitInst(uint32_t Inst) {
   char Buffer[4];
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h
@@ -31,6 +31,7 @@
 
 struct AArch64MCAsmInfoELF : public MCAsmInfoELF {
   explicit AArch64MCAsmInfoELF(const Triple );
+  bool EmitBTIMarking;
 };
 
 struct AArch64MCAsmInfoMicrosoftCOFF : public MCAsmInfoMicrosoft {
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
@@ -30,6 +30,11 @@
 cl::values(clEnumValN(Generic, "generic", "Emit generic NEON assembly"),
clEnumValN(Apple, "apple", "Emit Apple-style NEON assembly")));
 
+static cl::opt MarkBTIProperty(
+"aarch64-mark-bti-property", cl::Hidden,

[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-08-13 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 285332.
danielkiss added a comment.

Always emit xpac* instructions as discussed in D84502 
.


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Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll

Index: llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
+
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; pointer authentication code from the pointer.
+; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
+; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
+; On Armv8.3-A and onwards XPACI is available so use that instead.
+
+define i8* @ra0() nounwind readnone {
+entry:
+; CHECK-LABEL: ra0:
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint#7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: ret
+; CHECKV83:   str x30, [sp, #-16]!
+; CHECKV83-NEXT:  xpaci   x30
+; CHECKV83-NEXT:  mov x0, x30
+; CHECKV83-NEXT:  ldr x30, [sp], #16
+; CHECKV83-NEXT:  ret
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @ra1() nounwind readnone #0 {
+entry:
+; CHECK-LABEL: ra1:
+; CHECK:  hint#25
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint#7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: hint#29
+; CHECK-NEXT: ret
+; CHECKV83:   paciasp
+; CHECKV83-NEXT:  str x30, [sp, #-16]!
+; CHECKV83-NEXT:  xpaci   x30
+; CHECKV83-NEXT:  mov x0, x30
+; CHECKV83-NEXT:  ldr x30, [sp], #16
+; CHECKV83-NEXT:  retaa
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+attributes #0 = { "sign-return-address"="all" }
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6388,17 +6388,34 @@
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
   unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
+  SDValue ReturnAddress;
   if (Depth) {
 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
-return DAG.getLoad(VT, DL, DAG.getEntryNode(),
-   DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
-   MachinePointerInfo());
+ReturnAddress = DAG.getLoad(
+VT, DL, DAG.getEntryNode(),
+DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo());
+  } else {
+// Return LR, which contains the return address. Mark it an implicit
+// live-in.
+unsigned Reg = MF.addLiveIn(AArch64::LR, ::GPR64RegClass);
+ReturnAddress = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
+  }
+
+  // The XPACLRI instruction assembles to a hint-space instruction before
+  // Armv8.3-A therefore this instruction can be safely used for any pre
+  // Armv8.3-A architectures. On Armv8.3-A and onwards XPACI is available so use
+  // that instead.
+  SDNode *St;
+  if (Subtarget->hasV8_3aOps()) {
+St = DAG.getMachineNode(AArch64::XPACI, DL, VT, ReturnAddress);
+  } else {
+// XPACLRI operates on LR therefore we must move the operand accordingly.
+SDValue Chain =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::LR, ReturnAddress);
+St = DAG.getMachineNode(AArch64::XPACLRI, DL, VT, Chain);
   }
-
-  // Return LR, which contains the return address. Mark it an implicit live-in.
-  unsigned Reg = MF.addLiveIn(AArch64::LR, ::GPR64RegClass);
-  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
+  return SDValue(St, 0);
 }
 
 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
Index: llvm/include/llvm/CodeGen/ISDOpcodes.h
===
--- llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -86,7 +86,16 @@
   /// the parent's frame or return address, and so on.
   FRAMEADDR,
   RETURNADDR,
+
+  /// ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
+  /// This node takes no operand, returns a target-specific pointer to the
+  /// place in the stack frame where the return address of the current
+  /// function is stored.

[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-08-11 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

>> it is not useful to have a bti annotated function unless everything else is 
>> bti compatible too: it is all or nothing per elf module.
>
> This is false. Some functions in an elf module could be in a guarded region, 
> some in a non-guarded region. Some function may always
> be called in a "BTI-safe" way, which may be unknown to the compiler.

Right now the elf and all of the `text` sections considered BTI enabled or not. 
The dynamic linkers/loaders can't support this use case without additional 
information to be encoded somewhere (and specified). To support such we need to 
consider grouping/align to page boundaries these functions in the linker 
because BTI could be controlled by flags in PTE.
With the current spec this usecase is not supported in this way. The user have 
to link the BTI protected code into another elf.
Side note: The `force-bti` linker option can't work with half BTI enabled 
objects.


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[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-08-05 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

> FWIW GCC has a "sign-return-address" function attribute with a default value 
> of "none". It is considered deprecated, however, in favour of 
> "branch-protection"

This is just the internal representation, the function attribute in C/C++ 
source is the "branch-protection".

Old version of the patch used attribute value to represent the 
"ignore"/disabled state https://reviews.llvm.org/D75181?id=247201 so I have no 
idea what would be the right solution.


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[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-08-05 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 283172.
danielkiss edited the summary of this revision.
danielkiss added a comment.

This version of the patch behaves as `gcc` for case when no function present 
and when function has `-mbranch-protection` attribute without compiler flag.
The logic should be in clang because in llvm we won't have enough information 
to handle these things. (see D75181 )


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Files:
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  %r = tail call i32 @g()
-  ret i32 %r
-}
-
-declare dso_local i32 @g()
-
-attributes #0 = { "branch-target-enforcement" }
-
-; Declarations don't prevent setting BTI
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
-
-; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "branch-target-enforcement" }
-
-; No common attribute, no note section
-; ASM: warning: not setting BTI in feature flags
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf -S - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="none" }
-
-; No common attribute, no note section
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="all" }
-
-; Only the common atttribute (PAC)
-; ASM: warning: not setting BTI in feature flags
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	2
-
-; OBJ: Properties: aarch64 feature: PAC
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -1,25 +1,12 @@
 ; RUN: llc -mtriple=aarch64-linux %s   -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf --notes - | FileCheck %s

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-08-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

Would it be better to add a new value to `"sign-return-address"` as `"none"`? I 
don't see any other alternative option, I'm open to any other idea.


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[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-07-23 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 280048.
danielkiss added a comment.

fix review comments.


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Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll

Index: llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
+
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; pointer authentication code from the pointer.
+; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
+; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
+; On Armv8.3-A and onwards XPACI is available so use that instead.
+
+define i8* @era0() nounwind readnone #0 {
+entry:
+; CHECK-LABEL: era0:
+; CHECK:  hint #25
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint #7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: hint #29
+; CHECK-NEXT: ret
+; CHECKV83:   paciasp
+; CHECKV83-NEXT:  str x30, [sp, #-16]!
+; CHECKV83-NEXT:  xpaci   x30
+; CHECKV83-NEXT:  mov x0, x30
+; CHECKV83-NEXT:  ldr x30, [sp], #16
+; CHECKV83-NEXT:  retaa
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+attributes #0 = { "sign-return-address"="all" }
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6267,17 +6267,37 @@
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
   unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
+  SDValue ReturnAddress;
   if (Depth) {
 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
-return DAG.getLoad(VT, DL, DAG.getEntryNode(),
-   DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
-   MachinePointerInfo());
+ReturnAddress = DAG.getLoad(
+VT, DL, DAG.getEntryNode(),
+DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo());
+  } else {
+// Return LR, which contains the return address. Mark it an implicit
+// live-in.
+unsigned Reg = MF.addLiveIn(AArch64::LR, ::GPR64RegClass);
+ReturnAddress = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
+  }
+
+  if (!MF.getFunction().hasFnAttribute("sign-return-address"))
+return ReturnAddress;
+
+  // The XPACLRI instruction assembles to a hint-space instruction before
+  // Armv8.3-A therefore this instruction can be safely used for any pre
+  // Armv8.3-A architectures. On Armv8.3-A and onwards XPACI is available so use
+  // that instead.
+  if (Subtarget->hasV8_3aOps()) {
+SDNode *St = DAG.getMachineNode(AArch64::XPACI, DL, VT, ReturnAddress);
+return SDValue(St, 0);
+  } else {
+// XPACLRI operates on LR therefore we must move the operand accordingly.
+SDValue Chain =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::LR, ReturnAddress);
+SDNode *St = DAG.getMachineNode(AArch64::XPACLRI, DL, VT, Chain);
+return SDValue(St, 0);
   }
-
-  // Return LR, which contains the return address. Mark it an implicit live-in.
-  unsigned Reg = MF.addLiveIn(AArch64::LR, ::GPR64RegClass);
-  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
 }
 
 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
Index: llvm/include/llvm/CodeGen/ISDOpcodes.h
===
--- llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -86,7 +86,16 @@
   /// the parent's frame or return address, and so on.
   FRAMEADDR,
   RETURNADDR,
+
+  /// ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
+  /// This node takes no operand, returns a target-specific pointer to the
+  /// place in the stack frame where the return address of the current
+  /// function is stored.
   ADDROFRETURNADDR,
+
+  /// SPONENTRY - Represents the llvm.sponentry intrinsic. Takes no argument
+  /// and returns the stack pointer value at the entry of the current
+  /// function calling this intrinsic.
   SPONENTRY,
 
   /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
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[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-07-21 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

> If any function has the attribute "sign-return-address", then the output note
>  section should have PAC bit set. The return address signing is completely 
> local
>  to the function, and functions with or without return address signing can be
>  freely mixed with each other.

That is true PAC and non-PAC functions can be mixed. 
Does one function makes the "all executable sections" pac-ret enabled?
BTW `GNU_PROPERTY_AARCH64_FEATURE_1_PAC` is not really used for anything.

> Likewise, if any function has the attribute "branch-target-enforcement", then
>  the output note section should have the BTI flag set. Even though code 
> compiled
>  with BTI is not necessarily compatible with non-BTI code:
> 
> - the only way to get BTI code is by explicit use of 
> `-mbranch-protection=...` command-line option, or the corresponding 
> attribute, which we should consider a clear indication about the user's 
> intent to use BTI.
> - the only way to get a mix of present/non-present 
> "branch-target-enforcement" attributes is by the explicit use of the 
> `__attribute__((target("branch-protection=..."))`, in which case we should 
> assume the user knows what they are doing.

`__ARM_FEATURE_PAC_DEFAULT` and `__ARM_FEATURE_BTI_DEFAULT` controlled by the 
`-mbranch-protection=...` 
https://developer.arm.com/documentation/101028/0011/Feature-test-macros?lang=en

One of the reasons of the introduction of these macros is the management of the 
function attributes.
For example:

  #ifdef __ARM_FEATURE_PAC_DEFAULT
  #ifdef __ARM_FEATURE_BTI_DEFAULT
  #define NO_PAC_FUNC __attribute__((target("branch-protection=bti")))
  #else
  #define NO_PAC_FUNC __attribute__((target("branch-protection=none")))
  #endif /* __ARM_FEATURE_BTI_DEFAULT */
  ...

In my humble opinion the function attribute is there to alter global setting.
I considered to propagate the function attribute to the module flags but 
that would lead to inconsistent compilation with the macros that I'd avoid.

> What do to if there are no functions in the compile unit?
> 
> Technically, objects produced from such a unit are fully compatible with both 
> PAC and BTI, which
>  means both flags should be set. But looking at the (non-existent) function 
> attributes alone does
>  not allow us to unambiguously derive a user's intent to use PAC/BTI. In this 
> case, I would suggest
>  setting the ELF note flags, according to the LLVM IR module flags.

I think the only clear indication from the user to use PAC/BTI is the explicit 
use of `-mbranch-protection=...` command-line option.
A few function attributes that would turn PAC/BTI on just on those few 
functions makes no sense for me in any real world application. 
Valid to turn off PAC/BTI on selected functions while the whole application 
compiled with them.

We need to turn PAC off on the code path where we change\manage the keys for 
example.
Exaggerated example for BTI: https://godbolt.org/z/Y9bhe9  Current version of 
llvm issues a warning and won't emit the note while I think it should.


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[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-07-20 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

Patch for gcc is merged. 
https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=a70d5d81c41048556fd86eaa1036018a6bfba115


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[PATCH] D75453: [Driver][ARM] parse version of arm/thumb architecture correctly

2020-07-01 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG070acb1d1e51: [Driver][ARM] parse version of arm/thumb 
architecture correctly (authored by danielkiss).

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Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/windows-thumbv7em.cpp


Index: clang/test/Driver/windows-thumbv7em.cpp
===
--- /dev/null
+++ clang/test/Driver/windows-thumbv7em.cpp
@@ -0,0 +1,8 @@
+// RUN: %clang -target thumb-none-windows-eabi-coff -mcpu=cortex-m7 -### -c %s 
2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-V7
+// CHECK-V7-NOT: error: the target architecture 'thumbv7em' is not supported 
by the target 'thumbv7em-none-windows-eabi'
+
+// RUN: %clang -target thumb-none-windows-eabi-coff -mcpu=cortex-m1 -### -c %s 
2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-V6
+// CHECK-V6: error: the target architecture 'thumbv6m' is not supported by the 
target 'thumbv6m-none-windows-eabi'
+
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -4041,9 +4041,10 @@
   if (Triple.isOSWindows() && (Triple.getArch() == llvm::Triple::arm ||
Triple.getArch() == llvm::Triple::thumb)) {
 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
-unsigned Version;
-Triple.getArchName().substr(Offset).getAsInteger(10, Version);
-if (Version < 7)
+unsigned Version = 0;
+bool Failure =
+Triple.getArchName().substr(Offset).consumeInteger(10, Version);
+if (Failure || Version < 7)
   D.Diag(diag::err_target_unsupported_arch) << Triple.getArchName()
 << TripleStr;
   }


Index: clang/test/Driver/windows-thumbv7em.cpp
===
--- /dev/null
+++ clang/test/Driver/windows-thumbv7em.cpp
@@ -0,0 +1,8 @@
+// RUN: %clang -target thumb-none-windows-eabi-coff -mcpu=cortex-m7 -### -c %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-V7
+// CHECK-V7-NOT: error: the target architecture 'thumbv7em' is not supported by the target 'thumbv7em-none-windows-eabi'
+
+// RUN: %clang -target thumb-none-windows-eabi-coff -mcpu=cortex-m1 -### -c %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-V6
+// CHECK-V6: error: the target architecture 'thumbv6m' is not supported by the target 'thumbv6m-none-windows-eabi'
+
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -4041,9 +4041,10 @@
   if (Triple.isOSWindows() && (Triple.getArch() == llvm::Triple::arm ||
Triple.getArch() == llvm::Triple::thumb)) {
 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
-unsigned Version;
-Triple.getArchName().substr(Offset).getAsInteger(10, Version);
-if (Version < 7)
+unsigned Version = 0;
+bool Failure =
+Triple.getArchName().substr(Offset).consumeInteger(10, Version);
+if (Failure || Version < 7)
   D.Diag(diag::err_target_unsupported_arch) << Triple.getArchName()
 << TripleStr;
   }
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[PATCH] D75453: [Driver][ARM] parse version of arm/thumb architecture correctly

2020-07-01 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

@j0le  patch is landed but I just realised the review is still blocked by 
@compnerd. So it won't be closed I think, that is my bad.

https://github.com/llvm/llvm-project/commit/070acb1d1e51ffd289a46b8f93e993635d0053b7


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[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-06-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

In D80791#2120755 , @kees wrote:

> In D80791#2120503 , @nickdesaulniers 
> wrote:
>
> > Might someone wish to disable PAC/BTI on an individual function, while 
> > having it on for the rest?  I guess that would mean you can't call that 
> > function indirectly?
>
>
> It would mean you can't call it _at all_, not just indirectly. :) Which is 
> why I still think the warning is useful. Perhaps don't warn for the functions 
> with the attribute?


BTI landing pad is needed only when the previous instructions was an indirect 
branch/jump  `bl x16`. 
With a direct branch `bl foo` no landing pad is needed at all. Rational is that 
direct branches can't be hijacked, they always land at the same location. 
Landing pads emitted only when indirect branch is possible to a function.[1]

[1] 
https://github.com/llvm/llvm-project/blob/f45b41348ba49c4a76baab1e3e302ef8e2bb992b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp#L94


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[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-06-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

Function level attributes could set different attributes for functions. If 
function attribute is used then I assume the user know what he/she is doing so 
no need to emit a warning.
Maybe some would ensure the function is only directly called and never called 
indirectly by enforcing the branch-proctection=None or Pac-ret.
By default this warning shall not present anyway, especially for LLVM internals.

> Specifically, this appears to be a legitimate bug, found by the warnings: 
> https://bugs.llvm.org/show_bug.cgi?id=46258

Thanks for pointing to this bug, I pick it up, since my two other patches 
address it:
https://reviews.llvm.org/D75181
and for CFI https://reviews.llvm.org/D81251

after those two patches, if we would emit a warning for the different flags we 
could do it in clang due to no reason to postpone the diagnostic to the 
backend. also would be easier suppress the warning if needed.


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[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-06-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

This patch solve this too: https://bugs.llvm.org/show_bug.cgi?id=46480


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[PATCH] D75453: [Driver][ARM] parse version of arm/thumb architecture correctly

2020-06-22 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

j0le, I will commit later this week for you.
compnerd do you have any comment for this version?


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[PATCH] D81930: [AArch64] Add -mmark-bti-property flag.

2020-06-19 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 272024.
danielkiss retitled this revision from "[AArch64] Add -mbti flag." to 
"[AArch64] Add -mmark-bti-property flag.".
danielkiss edited the summary of this revision.
danielkiss added a comment.

Rename the flag to -mmark-bti-property


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/arm64-markbti.S
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h

Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
@@ -20,6 +20,7 @@
 class AArch64TargetStreamer : public MCTargetStreamer {
 public:
   AArch64TargetStreamer(MCStreamer );
+  AArch64TargetStreamer(MCStreamer , const MCSubtargetInfo *STI);
   ~AArch64TargetStreamer() override;
 
   void finish() override;
@@ -36,6 +37,9 @@
   /// Callback used to implement the .inst directive.
   virtual void emitInst(uint32_t Inst);
 
+  /// Callback used to implement the .note.gnu.property section.
+  virtual void emitNoteSection(unsigned Flags);
+
   virtual void EmitARM64WinCFIAllocStack(unsigned Size) {}
   virtual void EmitARM64WinCFISaveFPLR(int Offset) {}
   virtual void EmitARM64WinCFISaveFPLRX(int Offset) {}
@@ -56,6 +60,7 @@
 
 private:
   std::unique_ptr ConstantPools;
+  const MCSubtargetInfo *STI;
 };
 
 class AArch64TargetELFStreamer : public AArch64TargetStreamer {
@@ -65,7 +70,8 @@
   void emitInst(uint32_t Inst) override;
 
 public:
-  AArch64TargetELFStreamer(MCStreamer ) : AArch64TargetStreamer(S) {}
+  AArch64TargetELFStreamer(MCStreamer , const MCSubtargetInfo *STI)
+  : AArch64TargetStreamer(S, STI) {}
 };
 
 class AArch64TargetWinCOFFStreamer : public llvm::AArch64TargetStreamer {
@@ -76,8 +82,8 @@
   // Symbol of the current epilog for which we are processing SEH directives.
   MCSymbol *CurrentEpilog = nullptr;
 public:
-  AArch64TargetWinCOFFStreamer(llvm::MCStreamer )
-: AArch64TargetStreamer(S) {}
+  AArch64TargetWinCOFFStreamer(llvm::MCStreamer , const MCSubtargetInfo *STI)
+  : AArch64TargetStreamer(S, STI) {}
 
   // The unwind codes on ARM64 Windows are documented at
   // https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
@@ -11,8 +11,12 @@
 //===--===//
 
 #include "AArch64TargetStreamer.h"
+#include "AArch64Subtarget.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/ConstantPools.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 using namespace llvm;
@@ -21,7 +25,13 @@
 // AArch64TargetStreamer Implemenation
 //
 AArch64TargetStreamer::AArch64TargetStreamer(MCStreamer )
-: MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()) {}
+: MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()),
+  STI(nullptr) {}
+
+AArch64TargetStreamer::AArch64TargetStreamer(MCStreamer ,
+ const MCSubtargetInfo *STI)
+: MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()),
+  STI(STI) {}
 
 AArch64TargetStreamer::~AArch64TargetStreamer() = default;
 
@@ -37,8 +47,54 @@
   ConstantPools->emitForCurrentSection(Streamer);
 }
 
-// finish() - write out any non-empty assembler constant pools.
-void AArch64TargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
+// finish() - write out any non-empty assembler constant pools and
+//   write out note.gnu.properties if need.
+void AArch64TargetStreamer::finish() {
+  ConstantPools->emitAll(Streamer);
+  if (!STI)
+return;
+
+  if (STI->getFeatureBits()[AArch64::FeatureEmitNoteBTIProperty]) {
+emitNoteSection(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
+  }
+}
+
+void AArch64TargetStreamer::emitNoteSection(unsigned Flags) {
+  if (Flags == 0) {
+return;
+  }
+  MCStreamer  = getStreamer();
+  MCContext  = OutStreamer.getContext();
+  // Emit a .note.gnu.property section with the flags.
+  MCSection *Cur = OutStreamer.getCurrentSectionOnly();
+  MCSectionELF *Nt = Context.getELFSection(".note.gnu.property", ELF::SHT_NOTE,
+

[PATCH] D81930: [AArch64] Add -mbti flag.

2020-06-18 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss planned changes to this revision.
danielkiss added a comment.

I got some comment internally, the -mbti might suggest it enables the bti 
feature so I'm going to rename the flag to -mmark-bti-property.


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[PATCH] D81930: [AArch64] Add -mbti flag.

2020-06-16 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss created this revision.
danielkiss added reviewers: nsz, tamas.petz, pbarrio, ostannard, chill.
Herald added subscribers: llvm-commits, cfe-commits, hiraditya, kristof.beyls.
Herald added projects: clang, LLVM.

Writing the .note.gnu.property manually is error prone and hard to
maintain in the assembly files.
The -mbti is for the assembler to emit the section with the
GNU_PROPERTY_AARCH64_FEATURE_1_BTI. To be used when C/C++ is compiled
with -mbranch-protection=bti.

This patch refactors the .note.gnu.property handling.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/test/Driver/arm64-markbti.S
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h

Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
@@ -20,6 +20,7 @@
 class AArch64TargetStreamer : public MCTargetStreamer {
 public:
   AArch64TargetStreamer(MCStreamer );
+  AArch64TargetStreamer(MCStreamer , const MCSubtargetInfo *STI);
   ~AArch64TargetStreamer() override;
 
   void finish() override;
@@ -36,6 +37,9 @@
   /// Callback used to implement the .inst directive.
   virtual void emitInst(uint32_t Inst);
 
+  /// Callback used to implement the .note.gnu.property section.
+  virtual void emitNoteSection(unsigned Flags);
+
   virtual void EmitARM64WinCFIAllocStack(unsigned Size) {}
   virtual void EmitARM64WinCFISaveFPLR(int Offset) {}
   virtual void EmitARM64WinCFISaveFPLRX(int Offset) {}
@@ -56,6 +60,7 @@
 
 private:
   std::unique_ptr ConstantPools;
+  const MCSubtargetInfo *STI;
 };
 
 class AArch64TargetELFStreamer : public AArch64TargetStreamer {
@@ -65,7 +70,8 @@
   void emitInst(uint32_t Inst) override;
 
 public:
-  AArch64TargetELFStreamer(MCStreamer ) : AArch64TargetStreamer(S) {}
+  AArch64TargetELFStreamer(MCStreamer , const MCSubtargetInfo *STI)
+  : AArch64TargetStreamer(S, STI) {}
 };
 
 class AArch64TargetWinCOFFStreamer : public llvm::AArch64TargetStreamer {
@@ -76,8 +82,8 @@
   // Symbol of the current epilog for which we are processing SEH directives.
   MCSymbol *CurrentEpilog = nullptr;
 public:
-  AArch64TargetWinCOFFStreamer(llvm::MCStreamer )
-: AArch64TargetStreamer(S) {}
+  AArch64TargetWinCOFFStreamer(llvm::MCStreamer , const MCSubtargetInfo *STI)
+  : AArch64TargetStreamer(S, STI) {}
 
   // The unwind codes on ARM64 Windows are documented at
   // https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
===
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp
@@ -11,8 +11,12 @@
 //===--===//
 
 #include "AArch64TargetStreamer.h"
+#include "AArch64Subtarget.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/ConstantPools.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 using namespace llvm;
@@ -21,7 +25,13 @@
 // AArch64TargetStreamer Implemenation
 //
 AArch64TargetStreamer::AArch64TargetStreamer(MCStreamer )
-: MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()) {}
+: MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()),
+  STI(nullptr) {}
+
+AArch64TargetStreamer::AArch64TargetStreamer(MCStreamer ,
+ const MCSubtargetInfo *STI)
+: MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()),
+  STI(STI) {}
 
 AArch64TargetStreamer::~AArch64TargetStreamer() = default;
 
@@ -37,8 +47,54 @@
   ConstantPools->emitForCurrentSection(Streamer);
 }
 
-// finish() - write out any non-empty assembler constant pools.
-void AArch64TargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
+// finish() - write out any non-empty assembler constant pools and
+//   write out note.gnu.properties if need.
+void AArch64TargetStreamer::finish() {
+  ConstantPools->emitAll(Streamer);
+  if (!STI)
+return;
+
+  if (STI->getFeatureBits()[AArch64::FeatureEmitNoteBTI]) {
+emitNoteSection(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
+  }
+}
+
+void AArch64TargetStreamer::emitNoteSection(unsigned Flags) {
+  if (Flags == 0) {
+return;
+  }
+  MCStreamer  = getStreamer();
+  MCContext  = OutStreamer.getContext();
+  // Emit a

[PATCH] D75453: [Driver][ARM] parse version of arm/thumb architecture correctly

2020-06-16 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss accepted this revision.
danielkiss added a comment.

Sorry for the delay, it is okay to say "ping" after a while :) 
LGTM


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[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-06-08 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

patch for gcc: https://gcc.gnu.org/pipermail/gcc-patches/2020-June/547404.html


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[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-06-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

depends on D80791 


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[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-06-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 268383.
danielkiss edited the summary of this revision.
danielkiss added a comment.

Patch is refactored, the new pass smooth out the attribute issues.
This version fixes issues with _clang_call_terminate, sanitisers and the CFI. 
New pass might need a new file, I'm not yet convinced myself.


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Files:
  clang/lib/CodeGen/CGDeclCXX.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aarch64-branch-protection-attr.c
  clang/test/CodeGen/aarch64-sign-return-address.c
  clang/test/CodeGenCXX/aarch64-branch-target_clang_call_terminate.cpp
  clang/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
  llvm/lib/Target/AArch64/AArch64.h
  llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/test/CodeGen/AArch64/O0-pipeline.ll
  llvm/test/CodeGen/AArch64/O3-pipeline.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
@@ -8,10 +8,11 @@
   ret i32 0
 }
 
-!llvm.module.flags = !{!0, !1}
+!llvm.module.flags = !{!0, !1, !2}
 
 !0 = !{i32 4, !"branch-target-enforcement", i32 1}
 !1 = !{i32 4, !"sign-return-address", !"non-leaf"}
+!2 = !{i32 4, !"sign-return-address-key", !"a_key"}
 
 ; Both attribute present
 ; ASM:	.word	3221225472
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
@@ -8,9 +8,10 @@
   ret i32 0
 }
 
-!llvm.module.flags = !{!0}
+!llvm.module.flags = !{!0, !1}
 
 !0 = !{i32 4, !"sign-return-address", !"all"}
+!1 = !{i32 4, !"sign-return-address-key", !"a_key"}
 
 ; PAC attribute present
 ; ASM:	.word	3221225472
Index: llvm/test/CodeGen/AArch64/O3-pipeline.ll
===
--- llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -23,6 +23,8 @@
 ; CHECK-NEXT: Dominator Tree Construction
 ; CHECK-NEXT: FunctionPass Manager
 ; CHECK-NEXT:   Simplify the CFG
+; CHECK-NEXT: AArch64 Branch Protection
+; CHECK-NEXT: FunctionPass Manager
 ; CHECK-NEXT:   Dominator Tree Construction
 ; CHECK-NEXT:   Natural Loop Information
 ; CHECK-NEXT:   Lazy Branch Probability Analysis
Index: llvm/test/CodeGen/AArch64/O0-pipeline.ll
===
--- llvm/test/CodeGen/AArch64/O0-pipeline.ll
+++ llvm/test/CodeGen/AArch64/O0-pipeline.ll
@@ -16,6 +16,8 @@
 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
 ; CHECK-NEXT: FunctionPass Manager
 ; CHECK-NEXT:   Expand Atomic instructions
+; CHECK-NEXT: AArch64 Branch Protection
+; CHECK-NEXT: FunctionPass Manager
 ; CHECK-NEXT:   Module Verifier
 ; CHECK-NEXT:   Lower Garbage Collection Instructions
 ; CHECK-NEXT:   Shadow Stack GC Lowering
Index: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
===
--- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -33,6 +33,7 @@
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/Function.h"
+#include "llvm/IR/Metadata.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCTargetOptions.h"
@@ -454,6 +455,9 @@
   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
 addPass(createCFGSimplificationPass(1, true, true, false, true));
 
+  // Sets up the branch protection attributes for functions that added so far.
+  addPass(createAArch64BranchProtectionPass());
+
   // Run LoopDataPrefetch
   //
   // Run this before LSR to remove the multiplies involved in computing the
Index: llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
===
--- llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
+++ llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
@@ -26,9 +26,57 @@
 using namespace llvm;
 
 #define DEBUG_TYPE "aarch64-branch-targets"
+#define AARCH64_BRANCH_PROTECTION_NAME "AArch64 Branch Protection"
 #define AARCH64_BRANCH_TARGETS_NAME "AArch64 Branch Targets"
 
 namespace {
+
+struct AArch64BranchProtection : public ModulePass {
+  static char ID;
+  AArch64BranchProtection() : ModulePass(ID) {
+initializeAArch64BranchProtectionPass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnModule(Module ) override {
+bool changed = false;
+const

[PATCH] D80791: [AArch64] Generate .note.gnu.property based on module flags.

2020-05-29 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss created this revision.
danielkiss added reviewers: tamas.petz, chill.
Herald added subscribers: llvm-commits, cfe-commits, hiraditya, kristof.beyls.
Herald added projects: clang, LLVM.

Generate .note.gnu.property for PAC and BTI if the compile unit is
compiled with -mbranch-protection. 
It is valid use case to have a non-bti protected function therefore the note 
shouldn't be
removed in that case. In this case only the direct call is valid to the 
function.
This behaviour matches with gcc.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80791

Files:
  clang/lib/CodeGen/CodeGenModule.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
-; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  %r = tail call i32 @g()
-  ret i32 %r
-}
-
-declare dso_local i32 @g()
-
-attributes #0 = { "branch-target-enforcement" }
-
-; Declarations don't prevent setting BTI
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	1
-
-; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf -S | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "branch-target-enforcement" }
-
-; No common attribute, no note section
-; ASM: warning: not setting BTI in feature flags
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf -S | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="none" }
-
-; No common attribute, no note section
-; ASM-NOT: .note.gnu.property
-; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux %s   -o - 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o -  |  \
-; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
-
-define dso_local i32 @f() #0 {
-entry:
-  ret i32 0
-}
-
-define dso_local i32 @g() #1 {
-entry:
-  ret i32 0
-}
-
-attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
-
-attributes #1 = { "sign-return-address"="all" }
-
-; Only the common atttribute (PAC)
-; ASM: warning: not setting BTI in feature flags
-; ASM:	.word	3221225472
-; ASM-NEXT:	.word	4
-; ASM-NEXT:	.word	2
-
-; OBJ: Properties: aarch64 feature: PAC
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -1,25 +1,12 @@
 ; RUN: llc -mtriple=aarch64-linux %s   -o - | \
 ; RUN:   FileCheck %s --check-prefix=ASM
-; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - |  \
-; RUN:   llvm-readelf --notes | FileCheck %s

[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-05-28 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

Related ticket for gcc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891


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[PATCH] D75044: [AArch64] __builtin_return_address for PAuth.

2020-05-27 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 266595.
danielkiss marked an inline comment as done.
danielkiss retitled this revision from "[AArch64] __builtin_extract_return_addr 
 for PAuth." to "[AArch64] __builtin_return_address for PAuth.".
danielkiss edited the summary of this revision.
danielkiss added a comment.

Changing the implementation from __builtin_extract_return_addr to 
__builtin_return_address.
Stripping PAC in __builtin_return_address is a better solution,  because:

- we should not expose PAC bits to the user because it could be passed around 
and that would be an ABI break.
- __builtin_extract_return_addr has a pair, the __builtin_frob_return_addr 
which won't be supported with PAC.

I'm thinking of adding a warning if __builtin_frob_return_addr is used with PAC 
on.
Same change will be proposed from gcc too.


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Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll

Index: llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
+
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; pointer authentication code from the pointer.
+; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
+; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
+; On Armv8.3-A and onwards XPACI is available so use that instead.
+
+define i8* @era0() nounwind readnone #0 {
+entry:
+; CHECK-LABEL: era0:
+; CHECK:  hint #25
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: hint #7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: hint #29
+; CHECK-NEXT: ret
+; CHECKV83:   paciasp
+; CHECKV83-NEXT:  xpaci   x0
+; CHECKV83-NEXT:  retaa
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+attributes #0 = { "sign-return-address"="all" }
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6093,17 +6093,39 @@
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
   unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
+  SDValue ReturnAddress;
   if (Depth) {
 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
-return DAG.getLoad(VT, DL, DAG.getEntryNode(),
-   DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
-   MachinePointerInfo());
+ReturnAddress = DAG.getLoad(
+VT, DL, DAG.getEntryNode(),
+DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo());
+  } else {
+// Return LR, which contains the return address. Mark it an implicit
+// live-in.
+unsigned Reg = MF.addLiveIn(AArch64::LR, ::GPR64RegClass);
+ReturnAddress = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
+  }
+
+  if (!MF.getFunction().hasFnAttribute("sign-return-address"))
+return ReturnAddress;
+
+  // The XPACLRI instruction assembles to a hint-space instruction before
+  // Armv8.3-A therefore this instruction can be safely used for any pre
+  // Armv8.3-A architectures. On Armv8.3-A and onwards XPACI is available so use
+  // that instead.
+  if (Subtarget->hasV8_3aOps()) {
+SDValue Reg =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, ReturnAddress);
+SDNode *St = DAG.getMachineNode(AArch64::XPACI, DL, VT, Reg);
+return SDValue(St, 0);
+  } else {
+// XPACLRI operates on LR therefore we must move the operand accordingly.
+SDValue Reg =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::LR, ReturnAddress);
+SDNode *St = DAG.getMachineNode(AArch64::XPACLRI, DL, VT, Reg);
+return SDValue(St, 0);
   }
-
-  // Return LR, which contains the return address. Mark it an implicit live-in.
-  unsigned Reg = MF.addLiveIn(AArch64::LR, ::GPR64RegClass);
-  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
 }
 
 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
Index: llvm/include/llvm/CodeGen/ISDOpcodes.h
===
--- llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -85,7 +85,16 @@
   /// the parent's frame or return address, and so on.
   FRAMEADDR,
   RETURNADDR,
+
+  ///

[PATCH] D75453: [Driver][ARM] fix undefined behaviour when checking architecture version

2020-04-28 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

Please update the title and the summary because those will be the commit 
message.
IMHO the test a case would be extended with a test where the body of the 
modified if condition is tested.
Otherwise LGTM.


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[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-04-08 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:5149-5152
+  if (BPI.BranchTargetEnforcement)
+Fn->addFnAttr("branch-target-enforcement", "true");
+  else
+Fn->addFnAttr("branch-target-enforcement", "false");

tamas.petz wrote:
> chill wrote:
> > danielkiss wrote:
> > > I'm going to rebase the patch. I add there a new attribute here 
> > > "ignore-branch-target-enforcement"
> > > so then the "branch-target-enforcement"="true"/"false" could be just 
> > > "branch-target-enforcement".
> > > 
> > > 
> > TBH, that's worse, IMHO.
> > 
> > Ideally, I *think* we'd like *every* LLVM IR function that the backend sees,
> > regardless of how, why and by whom it is created, to have (or not have)
> > the three existing PACBTI attributes "sign-return-address", 
> > "sign-return-address-key", and "branch-target-enforcement", so the backend 
> > can generate code accordingly.
> > 
> > The module attributes are LLVM IR metadata,  and  AFAIK LLVM IR metadata is 
> > an optional extra, 
> > it should not affect correctness.
> > Indeed, *module* metadata is a somwhat grey area,  better not use it if 
> > there a way around it.
> > 
> > 
> > 
> Which case are you trying to handle here?
> Is this the case, for example, when -mbranch-protection=standard is set but a 
> function has _attribute _((target("branch-protection=none")))?
Chill: I think I have code that solve that for clang created functions, but 
functions created in llvm I don't have any idea. 

Tamas: yes, that is the case when module is compiled with bti but the function 
is not ( "none" or "pac-ret" and so on. )


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[PATCH] D75044: [AArch64] __builtin_extract_return_addr for PAuth.

2020-04-08 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss marked 4 inline comments as done.
danielkiss added inline comments.



Comment at: llvm/include/llvm/CodeGen/ISDOpcodes.h:74
 /// the parent's frame or return address, and so on.
-FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, SPONENTRY,
+FRAMEADDR, RETURNADDR, ADDROFRETURNADDR, EXTRACTRETURNADDR, SPONENTRY,
 

chill wrote:
> Needs a comment about `EXTRACTRETURNADDR`. And also a slightly different 
> grouping, so the non-commented/undocumented things stand out.
agree, I. added documentation for all now.


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[PATCH] D75044: [AArch64] __builtin_extract_return_addr for PAuth.

2020-04-08 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 256069.
danielkiss added a comment.

Rebased and address review comments.


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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm64-extractreturnaddress.c
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/aarch64-extractreturnaddress.ll

Index: llvm/test/CodeGen/AArch64/aarch64-extractreturnaddress.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-extractreturnaddress.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
+
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; pointer authentication code from the pointer.
+; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
+; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
+; On Armv8.3-A and onwards XPACI is available so use that instead.
+
+define i8* @era0(i8* %x) nounwind readnone #0 {
+entry:
+; CHECK-LABEL: era0:
+; CHECK:  hint #25
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: mov x30, x0
+; CHECK-NEXT: hint #7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: hint #29
+; CHECK-NEXT: ret
+; CHECKV83:   paciasp
+; CHECKV83-NEXT:  xpaci   x0
+; CHECKV83-NEXT:  retaa
+  %0 = tail call i8* @llvm.extractreturnaddress(i8* %x)
+  ret i8* %0
+}
+attributes #0 = { "sign-return-address"="all" }
+
+declare i8* @llvm.extractreturnaddress(i8*) nounwind readnone
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.h
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -768,6 +768,7 @@
   SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG ) const;
   SDValue LowerSPONENTRY(SDValue Op, SelectionDAG ) const;
   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG ) const;
+  SDValue LowerEXTRACTRETURNADDR(SDValue Op, SelectionDAG ) const;
   SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG ) const;
   SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG ) const;
   SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG ) const;
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3323,6 +3323,8 @@
 return LowerSPONENTRY(Op, DAG);
   case ISD::RETURNADDR:
 return LowerRETURNADDR(Op, DAG);
+  case ISD::EXTRACTRETURNADDR:
+return LowerEXTRACTRETURNADDR(Op, DAG);
   case ISD::ADDROFRETURNADDR:
 return LowerADDROFRETURNADDR(Op, DAG);
   case ISD::INSERT_VECTOR_ELT:
@@ -6027,6 +6029,29 @@
   return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
 }
 
+SDValue AArch64TargetLowering::LowerEXTRACTRETURNADDR(SDValue Op,
+  SelectionDAG ) const {
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+
+  // The XPACLRI instruction assembles to a hint-space instruction before
+  // Armv8.3-A therefore this instruction can be safely used for any pre
+  // Armv8.3-A architectures. On Armv8.3-A and onwards XPACI is available so use
+  // that instead.
+  if (Subtarget->hasV8_3aOps()) {
+SDValue Reg =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, Op.getOperand(0));
+SDNode *St = DAG.getMachineNode(AArch64::XPACI, DL, VT, Reg);
+return SDValue(St, 0);
+  } else {
+// XPACLRI operates on LR therefore we must move the operand accordingly.
+SDValue Reg =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::LR, Op.getOperand(0));
+SDNode *St = DAG.getMachineNode(AArch64::XPACLRI, DL, VT, Reg);
+return SDValue(St, 0);
+  }
+}
+
 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5652,6 +5652,11 @@
  TLI.getPointerTy(DAG.getDataLayout()),
  getValue(I.getArgOperand(0;
 return;
+  case

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-04-06 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 255347.
danielkiss added a reviewer: tamas.petz.
danielkiss added a comment.

Fix review comments from Tamas.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75181/new/

https://reviews.llvm.org/D75181

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aarch64-branch-protection-attr.c
  clang/test/CodeGenCXX/aarch64-branch-target_clang_call_terminate.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=aarch64-linux %s   -o - | \
+; RUN:   FileCheck %s --check-prefix=ASM
+; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
+; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
+
+define dso_local i32 @f() #0 {
+entry:
+  ret i32 0
+}
+
+define dso_local i32 @g() {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "branch-target-enforcement" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
+; Only the common atttribute (BTI)
+; ASM:	.word	3221225472
+; ASM-NEXT:	.word	4
+; ASM-NEXT	.word	1
+
+; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
@@ -13,6 +13,10 @@
 
 attributes #0 = { "branch-target-enforcement" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
 ; Declarations don't prevent setting BTI
 ; ASM:	.word	3221225472
 ; ASM-NEXT:	.word	4
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
@@ -13,10 +13,14 @@
   ret i32 0
 }
 
-attributes #0 = { "sign-return-address"="non-leaf" }
+attributes #0 = { "ignore-branch-target-enforcement" "sign-return-address"="non-leaf" }
 
 attributes #1 = { "branch-target-enforcement" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
 ; No common attribute, no note section
 ; ASM: warning: not setting BTI in feature flags
 ; ASM-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
@@ -17,6 +17,11 @@
 
 attributes #1 = { "sign-return-address"="none" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"sign-return-address", !"non-leaf"}
+
+
 ; No common attribute, no note section
 ; ASM-NOT: .note.gnu.property
 ; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
@@ -15,7 +15,13 @@
 
 attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
 
-attributes #1 = { "sign-return-address"="all" }
+attributes #1 = { "ignore-branch-target-enforcement" "sign-return-address"="all" }
+
+!llvm.module.flags = !{!0, !1}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+!1 = !{i32 4, !"sign-return-address", !"all"}
+
 
 ; Only the common atttribute (PAC)
 ; ASM: warning: not setting BTI in feature flags
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -17,6 +17,10 @@
 
 attributes #1 = { "branch-target-enforcement" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
 ; Only the common atttribute (BTI)
 ; ASM:	.word	3221225472
 ; ASM-NEXT:	.word	4
Index:

[PATCH] D75044: [AArch64] __builtin_extract_return_addr for PAuth.

2020-04-03 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 254921.
danielkiss added a comment.

Rebased.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75044/new/

https://reviews.llvm.org/D75044

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm64-extractreturnaddress.c
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/aarch64-extractreturnaddress.ll

Index: llvm/test/CodeGen/AArch64/aarch64-extractreturnaddress.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-extractreturnaddress.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
+
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
+; pointer authentication code from the pointer.
+; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
+; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
+; On Armv8.3-A and onwards XPACI is available so use that instead.
+
+define i8* @era0(i8* %x) nounwind readnone #0 {
+entry:
+; CHECK-LABEL: era0:
+; CHECK:  hint #25
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK-NEXT: mov x30, x0
+; CHECK-NEXT: hint #7
+; CHECK-NEXT: mov x0, x30
+; CHECK-NEXT: ldr x30, [sp], #16
+; CHECK-NEXT: hint #29
+; CHECK-NEXT: ret
+; CHECKV83:   paciasp
+; CHECKV83-NEXT:  xpaci   x0
+; CHECKV83-NEXT:  retaa
+  %0 = tail call i8* @llvm.extractreturnaddress(i8* %x)
+  ret i8* %0
+}
+attributes #0 = { "sign-return-address"="all" }
+
+declare i8* @llvm.extractreturnaddress(i8*) nounwind readnone
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.h
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -768,6 +768,7 @@
   SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG ) const;
   SDValue LowerSPONENTRY(SDValue Op, SelectionDAG ) const;
   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG ) const;
+  SDValue LowerEXTRACTRETURNADDR(SDValue Op, SelectionDAG ) const;
   SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG ) const;
   SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG ) const;
   SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG ) const;
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3323,6 +3323,8 @@
 return LowerSPONENTRY(Op, DAG);
   case ISD::RETURNADDR:
 return LowerRETURNADDR(Op, DAG);
+  case ISD::EXTRACTRETURNADDR:
+return LowerEXTRACTRETURNADDR(Op, DAG);
   case ISD::ADDROFRETURNADDR:
 return LowerADDROFRETURNADDR(Op, DAG);
   case ISD::INSERT_VECTOR_ELT:
@@ -6027,6 +6029,29 @@
   return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
 }
 
+SDValue AArch64TargetLowering::LowerEXTRACTRETURNADDR(SDValue Op,
+  SelectionDAG ) const {
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+
+  // The XPACLRI instruction assembles to a hint-space instruction before
+  // Armv8.3-A therefore this instruction can be safely used for any pre
+  // Armv8.3-A architectures. On Armv8.3-A and onwards XPACI is available so use
+  // that instead.
+  if (Subtarget->hasV8_3aOps()) {
+SDValue Reg =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, Op.getOperand(0));
+SDNode *St = DAG.getMachineNode(AArch64::XPACI, DL, VT, Reg);
+return SDValue(St, 0);
+  } else {
+// XPACLRI operates on LR therefore we must move the operand accordingly.
+SDValue Reg =
+DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::LR, Op.getOperand(0));
+SDNode *St = DAG.getMachineNode(AArch64::XPACLRI, DL, VT, Reg);
+return SDValue(St, 0);
+  }
+}
+
 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5642,6 +5642,11 @@
  TLI.getPointerTy(DAG.getDataLayout()),
  getValue(I.getArgOperand(0;
 return;
+  case Intrinsic::extractreturnaddress:
+setValue(,

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-04-03 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 254761.
danielkiss added a comment.

The patched is rebased and the hopefully the logic is now simpler.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75181/new/

https://reviews.llvm.org/D75181

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aarch64-branch-protection-attr.c
  clang/test/CodeGenCXX/aarch64-branch-target_clang_call_terminate.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll

Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=aarch64-linux %s   -o - | \
+; RUN:   FileCheck %s --check-prefix=ASM
+; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
+; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
+
+define dso_local i32 @f() #0 {
+entry:
+  ret i32 0
+}
+
+define dso_local i32 @g() {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "branch-target-enforcement" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
+; Only the common atttribute (BTI)
+; ASM:	.word	3221225472
+; ASM-NEXT:	.word	4
+; ASM-NEXT	.word	1
+
+; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
@@ -13,6 +13,10 @@
 
 attributes #0 = { "branch-target-enforcement" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
 ; Declarations don't prevent setting BTI
 ; ASM:	.word	3221225472
 ; ASM-NEXT:	.word	4
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
@@ -13,10 +13,14 @@
   ret i32 0
 }
 
-attributes #0 = { "sign-return-address"="non-leaf" }
+attributes #0 = { "ignore-branch-target-enforcement" "sign-return-address"="non-leaf" }
 
 attributes #1 = { "branch-target-enforcement" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
 ; No common attribute, no note section
 ; ASM: warning: not setting BTI in feature flags
 ; ASM-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
@@ -17,6 +17,11 @@
 
 attributes #1 = { "sign-return-address"="none" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"sign-return-address", !"non-leaf"}
+
+
 ; No common attribute, no note section
 ; ASM-NOT: .note.gnu.property
 ; OBJ-NOT: .note.gnu.property
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
@@ -15,7 +15,13 @@
 
 attributes #0 = { "branch-target-enforcement" "sign-return-address"="non-leaf" }
 
-attributes #1 = { "sign-return-address"="all" }
+attributes #1 = { "ignore-branch-target-enforcement" "sign-return-address"="all" }
+
+!llvm.module.flags = !{!0, !1}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+!1 = !{i32 4, !"sign-return-address", !"all"}
+
 
 ; Only the common atttribute (PAC)
 ; ASM: warning: not setting BTI in feature flags
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
@@ -17,6 +17,10 @@
 
 attributes #1 = { "branch-target-enforcement" }
 
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
 ; Only the common atttribute (BTI)
 ; ASM:	.word	3221225472
 ; ASM-NEXT:	.word	4
Index:

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-04-02 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss marked an inline comment as done.
danielkiss added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:5149-5152
+  if (BPI.BranchTargetEnforcement)
+Fn->addFnAttr("branch-target-enforcement", "true");
+  else
+Fn->addFnAttr("branch-target-enforcement", "false");

I'm going to rebase the patch. I add there a new attribute here 
"ignore-branch-target-enforcement"
so then the "branch-target-enforcement"="true"/"false" could be just 
"branch-target-enforcement".




CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75181/new/

https://reviews.llvm.org/D75181



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[PATCH] D77134: [clang][AARCH64] Add __ARM_FEATURE_{PAC, BTI}_DEFAULT defines

2020-04-02 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG37ced5a57106: [clang][AARCH64] Add __ARM_FEATURE_{PAC, 
BTI}_DEFAULT  defines (authored by danielkiss).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77134/new/

https://reviews.llvm.org/D77134

Files:
  clang/include/clang/Basic/LangOptions.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/test/Preprocessor/aarch64-target-features.c

Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -39,6 +39,8 @@
 // CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2
 // CHECK-NOT: __ARM_FEATURE_SVE
 // CHECK-NOT: __ARM_FEATURE_DOTPROD
+// CHECK-NOT: __ARM_FEATURE_PAC_DEFAULT
+// CHECK-NOT: __ARM_FEATURE_BTI_DEFAULT
 
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
@@ -334,3 +336,33 @@
 // == Check Memory Tagging Extensions (MTE).
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a+memtag -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-MEMTAG %s
 // CHECK-MEMTAG: __ARM_FEATURE_MEMORY_TAGGING 1
+
+// == Check Pointer Authentication Extension (PAuth).
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-BKEY %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-ALL %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+leaf+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-BKEY-ALL %s
+// CHECK-PAUTH-OFF-NOT:  __ARM_FEATURE_PAC_DEFAULT
+// CHECK-PAUTH:  #define __ARM_FEATURE_PAC_DEFAULT 1
+// CHECK-PAUTH-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
+// CHECK-PAUTH-ALL:  #define __ARM_FEATURE_PAC_DEFAULT 5
+// CHECK-PAUTH-BKEY-ALL: #define __ARM_FEATURE_PAC_DEFAULT 6
+
+// == Check Branch Target Identification (BTI).
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8.5-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+leaf+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI %s
+// CHECK-BTI-OFF-NOT: __ARM_FEATURE_BTI_DEFAULT
+// CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -283,6

[PATCH] D77131: [clang] Move branch-protection from CodeGenOptions to LangOptions

2020-04-02 Thread Daniel Kiss via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7314aea5a42d: [clang] Move branch-protection from 
CodeGenOptions to  LangOptions (authored by danielkiss).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D77131

Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/CodeGenOptions.h
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Basic/LangOptions.h
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/AST/PrintfFormatString.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGDeclCXX.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Frontend/CompilerInvocation.cpp

Index: clang/lib/Frontend/CompilerInvocation.cpp
===
--- clang/lib/Frontend/CompilerInvocation.cpp
+++ clang/lib/Frontend/CompilerInvocation.cpp
@@ -1387,38 +1387,6 @@
 
   Opts.Addrsig = Args.hasArg(OPT_faddrsig);
 
-  if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
-StringRef SignScope = A->getValue();
-
-if (SignScope.equals_lower("none"))
-  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::None);
-else if (SignScope.equals_lower("all"))
-  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::All);
-else if (SignScope.equals_lower("non-leaf"))
-  Opts.setSignReturnAddress(
-  CodeGenOptions::SignReturnAddressScope::NonLeaf);
-else
-  Diags.Report(diag::err_drv_invalid_value)
-  << A->getAsString(Args) << SignScope;
-
-if (Arg *A = Args.getLastArg(OPT_msign_return_address_key_EQ)) {
-  StringRef SignKey = A->getValue();
-  if (!SignScope.empty() && !SignKey.empty()) {
-if (SignKey.equals_lower("a_key"))
-  Opts.setSignReturnAddressKey(
-  CodeGenOptions::SignReturnAddressKeyValue::AKey);
-else if (SignKey.equals_lower("b_key"))
-  Opts.setSignReturnAddressKey(
-  CodeGenOptions::SignReturnAddressKeyValue::BKey);
-else
-  Diags.Report(diag::err_drv_invalid_value)
-  << A->getAsString(Args) << SignKey;
-  }
-}
-  }
-
-  Opts.BranchTargetEnforcement = Args.hasArg(OPT_mbranch_target_enforce);
-
   Opts.KeepStaticConsts = Args.hasArg(OPT_fkeep_static_consts);
 
   Opts.SpeculativeLoadHardening = Args.hasArg(OPT_mspeculative_load_hardening);
@@ -3348,6 +3316,40 @@
   Opts.BuildingPCHWithObjectFile = Args.hasArg(OPT_building_pch_with_obj);
 
   Opts.MaxTokens = getLastArgIntValue(Args, OPT_fmax_tokens_EQ, 0, Diags);
+
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
+StringRef SignScope = A->getValue();
+
+if (SignScope.equals_lower("none"))
+  Opts.setSignReturnAddressScope(
+  LangOptions::SignReturnAddressScopeKind::None);
+else if (SignScope.equals_lower("all"))
+  Opts.setSignReturnAddressScope(
+  LangOptions::SignReturnAddressScopeKind::All);
+else if (SignScope.equals_lower("non-leaf"))
+  Opts.setSignReturnAddressScope(
+  LangOptions::SignReturnAddressScopeKind::NonLeaf);
+else
+  Diags.Report(diag::err_drv_invalid_value)
+  << A->getAsString(Args) << SignScope;
+
+if (Arg *A = Args.getLastArg(OPT_msign_return_address_key_EQ)) {
+  StringRef SignKey = A->getValue();
+  if (!SignScope.empty() && !SignKey.empty()) {
+if (SignKey.equals_lower("a_key"))
+  Opts.setSignReturnAddressKey(
+  LangOptions::SignReturnAddressKeyKind::AKey);
+else if (SignKey.equals_lower("b_key"))
+  Opts.setSignReturnAddressKey(
+  LangOptions::SignReturnAddressKeyKind::BKey);
+else
+  Diags.Report(diag::err_drv_invalid_value)
+  << A->getAsString(Args) << SignKey;
+  }
+}
+  }
+
+  Opts.BranchTargetEnforcement = Args.hasArg(OPT_mbranch_target_enforce);
 }
 
 static bool isStrictlyPreprocessorAction(frontend::ActionKind Action) {
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -5107,9 +5107,11 @@
 if (!FD)
   return;
 
-CodeGenOptions::SignReturnAddressScope Scope = CGM.getCodeGenOpts().getSignReturnAddress();
-CodeGenOptions::SignReturnAddressKeyValue Key = CGM.getCodeGenOpts().getSignReturnAddressKey();
-bool BranchTargetEnforcement = CGM.getCodeGenOpts().BranchTargetEnforcement;
+LangOptions::SignReturnAddressScopeKind Scope =
+CGM.getLangOpts().getSignReturnAddressScope();
+LangOptions::SignReturnAddressKeyKind Key =
+CGM.getLangOpts().getSignReturnAddressKey();
+bool BranchTargetEnforcement = CGM.getLangOpts().BranchTargetEnforcement;
 if (const auto *TA = FD->getAttr()) {
   ParsedTargetAttr Attr = TA->parse();
   if

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-04-01 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added inline comments.



Comment at: clang/lib/CodeGen/CGCall.cpp:1828
+  if (CodeGenOpts.BranchTargetEnforcement) {
+FuncAttrs.addAttribute("branch-target-enforcement", "true");
+  }

chill wrote:
> danielkiss wrote:
> > chill wrote:
> > > I would really prefer to not set values "true" or "false" for the 
> > > attribute: we don't really have tri-state logic there 
> > > (absent/present-true/present-false), and those values just add some 
> > > not-very useful string processing.
> > > 
> > the attribute will be  "absent" for the runtime emitted function.
> How about setting the attribute for LLVM created functions at the time of 
> creation, just like Clang created functions
> get their attribute at the time of creation?
> 
Attributes are not always set in clang as I see:
CodeGenModule::CreateRuntimeFunction() -> 
CodeGenModule::GetOrCreateLLVMFunction  
CreateRuntimeFunction could be fixed but, the common location for LLVM created 
function is the llvm::Function::Create() where the CodeGenOpts and LangOpts are 
no available.
Adding target specific code there seems not right for me.


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[PATCH] D77131: [clang] Move branch-protection from CodeGenOptions to LangOptions

2020-03-31 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

just a nit, LGTM otherwise.




Comment at: clang/include/clang/Basic/CodeGenOptions.def:402
 #undef VALUE_CODEGENOPT
-

is this change necessary? 


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[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-03-30 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss added a comment.

ping


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[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-03-13 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 250191.
danielkiss marked an inline comment as done.
danielkiss added a comment.

Patch is rebased, test is updated.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75181/new/

https://reviews.llvm.org/D75181

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDeclCXX.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aarch64-branch-protection-attr.c
  clang/test/CodeGen/aarch64-sign-return-address.c
  clang/test/CodeGenCXX/aarch64-branch-target_clang_call_terminate.cpp
  clang/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
  llvm/lib/Target/AArch64/AArch64CallLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
  llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
  llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
  llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
  llvm/test/CodeGen/AArch64/machine-outliner-outline-bti.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
  llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll

Index: llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
===
--- llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
+++ llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
 
-define void @f0() "patchable-function-entry"="0" "branch-target-enforcement" {
+define void @f0() "patchable-function-entry"="0" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f0:
 ; CHECK-NEXT: .Lfunc_begin0:
 ; CHECK:  // %bb.0:
@@ -12,7 +12,7 @@
 
 ;; -fpatchable-function-entry=1 -mbranch-protection=bti
 ;; For M=0, place the label .Lpatch0 after the initial BTI.
-define void @f1() "patchable-function-entry"="1" "branch-target-enforcement" {
+define void @f1() "patchable-function-entry"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f1:
 ; CHECK-NEXT: .Lfunc_begin1:
 ; CHECK-NEXT: .cfi_startproc
@@ -28,7 +28,7 @@
 }
 
 ;; -fpatchable-function-entry=2,1 -mbranch-protection=bti
-define void @f2_1() "patchable-function-entry"="1" "patchable-function-prefix"="1" "branch-target-enforcement" {
+define void @f2_1() "patchable-function-entry"="1" "patchable-function-prefix"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: .type f2_1,@function
 ; CHECK-NEXT: .Ltmp0:
 ; CHECK-NEXT:  nop
@@ -50,7 +50,7 @@
 ;; -fpatchable-function-entry=1 -mbranch-protection=bti
 ;; For M=0, don't create .Lpatch0 if the initial instruction is not BTI,
 ;; even if other basic blocks may have BTI.
-define internal void @f1i(i64 %v) "patchable-function-entry"="1" "branch-target-enforcement" {
+define internal void @f1i(i64 %v) "patchable-function-entry"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f1i:
 ; CHECK-NEXT: .Lfunc_begin3:
 ; CHECK:  // %bb.0:
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=aarch64-linux %s   -o - | \
+; RUN:   FileCheck %s --check-prefix=ASM
+; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
+; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
+
+define dso_local i32 @f() #0 {
+entry:
+  ret i32 0
+}
+
+define dso_local i32 @g() {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "branch-target-enforcement"="true" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
+; Only the common atttribute (BTI)
+; ASM:	.word	3221225472
+; ASM-NEXT:	.word	4
+; ASM-NEXT	.word	1
+
+; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
@@ -11,7 +11,11 @@
 
 declare dso_local i32 @g()
 
-attributes #0 = { "branch-target-enforcement" }
+attributes #0 = { "branch-target-enforcement"="true" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4,

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-03-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 248222.
danielkiss marked an inline comment as done.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75181/new/

https://reviews.llvm.org/D75181

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDeclCXX.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aarch64-branch-protection-attr.c
  clang/test/CodeGen/aarch64-sign-return-address.c
  clang/test/CodeGenCXX/aarch64-branch-target_clang_call_terminate.cpp
  clang/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
  llvm/lib/Target/AArch64/AArch64CallLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
  llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
  llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
  llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
  llvm/test/CodeGen/AArch64/machine-outliner-outline-bti.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
  llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll

Index: llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
===
--- llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
+++ llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
 
-define void @f0() "patchable-function-entry"="0" "branch-target-enforcement" {
+define void @f0() "patchable-function-entry"="0" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f0:
 ; CHECK-NEXT: .Lfunc_begin0:
 ; CHECK:  // %bb.0:
@@ -12,7 +12,7 @@
 
 ;; -fpatchable-function-entry=1 -mbranch-protection=bti
 ;; For M=0, place the label .Lpatch0 after the initial BTI.
-define void @f1() "patchable-function-entry"="1" "branch-target-enforcement" {
+define void @f1() "patchable-function-entry"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f1:
 ; CHECK-NEXT: .Lfunc_begin1:
 ; CHECK-NEXT: .cfi_startproc
@@ -28,7 +28,7 @@
 }
 
 ;; -fpatchable-function-entry=2,1 -mbranch-protection=bti
-define void @f2_1() "patchable-function-entry"="1" "patchable-function-prefix"="1" "branch-target-enforcement" {
+define void @f2_1() "patchable-function-entry"="1" "patchable-function-prefix"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: .type f2_1,@function
 ; CHECK-NEXT: .Ltmp0:
 ; CHECK-NEXT:  nop
@@ -50,7 +50,7 @@
 ;; -fpatchable-function-entry=1 -mbranch-protection=bti
 ;; For M=0, don't create .Lpatch0 if the initial instruction is not BTI,
 ;; even if other basic blocks may have BTI.
-define internal void @f1i(i64 %v) "patchable-function-entry"="1" "branch-target-enforcement" {
+define internal void @f1i(i64 %v) "patchable-function-entry"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f1i:
 ; CHECK-NEXT: .Lfunc_begin3:
 ; CHECK:  // %bb.0:
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=aarch64-linux %s   -o - | \
+; RUN:   FileCheck %s --check-prefix=ASM
+; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
+; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
+
+define dso_local i32 @f() #0 {
+entry:
+  ret i32 0
+}
+
+define dso_local i32 @g() {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "branch-target-enforcement"="true" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
+; Only the common atttribute (BTI)
+; ASM:	.word	3221225472
+; ASM-NEXT:	.word	4
+; ASM-NEXT	.word	1
+
+; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
===
--- llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
@@ -11,7 +11,11 @@
 
 declare dso_local i32 @g()
 
-attributes #0 = { "branch-target-enforcement" }
+attributes #0 = { "branch-target-enforcement"="true" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
 
 ; Declarations don't prevent setting BTI
 ; ASM:

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-03-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss updated this revision to Diff 248201.
danielkiss added a comment.

Thanks for the comments, patch is improved
isStringAttribute() check removed, the attribute is always a string in this 
case or "null" so the check is not needed.
Function level the attribute is now only change when needed, so as the function 
level attribute is expected to be rare I hope the performance won't be impacted 
by the patch.
I kept the "tri-state" logic because of the emitted functions. Introducing a 
"branch-target-enforcement-disabled" attribute seems even more confusing for me.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75181/new/

https://reviews.llvm.org/D75181

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDeclCXX.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/aarch64-branch-protection-attr.c
  clang/test/CodeGen/aarch64-sign-return-address.c
  clang/test/CodeGenCXX/aarch64-branch-target_clang_call_terminate.cpp
  clang/test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
  llvm/lib/Target/AArch64/AArch64CallLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
  llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
  llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll
  llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
  llvm/test/CodeGen/AArch64/machine-outliner-outline-bti.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-0.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-1.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-2.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-3.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-4.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-5.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-6.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-7.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll
  llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
  llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll

Index: llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
===
--- llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
+++ llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
 
-define void @f0() "patchable-function-entry"="0" "branch-target-enforcement" {
+define void @f0() "patchable-function-entry"="0" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f0:
 ; CHECK-NEXT: .Lfunc_begin0:
 ; CHECK:  // %bb.0:
@@ -12,7 +12,7 @@
 
 ;; -fpatchable-function-entry=1 -mbranch-protection=bti
 ;; For M=0, place the label .Lpatch0 after the initial BTI.
-define void @f1() "patchable-function-entry"="1" "branch-target-enforcement" {
+define void @f1() "patchable-function-entry"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f1:
 ; CHECK-NEXT: .Lfunc_begin1:
 ; CHECK-NEXT: .cfi_startproc
@@ -28,7 +28,7 @@
 }
 
 ;; -fpatchable-function-entry=2,1 -mbranch-protection=bti
-define void @f2_1() "patchable-function-entry"="1" "patchable-function-prefix"="1" "branch-target-enforcement" {
+define void @f2_1() "patchable-function-entry"="1" "patchable-function-prefix"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: .type f2_1,@function
 ; CHECK-NEXT: .Ltmp0:
 ; CHECK-NEXT:  nop
@@ -50,7 +50,7 @@
 ;; -fpatchable-function-entry=1 -mbranch-protection=bti
 ;; For M=0, don't create .Lpatch0 if the initial instruction is not BTI,
 ;; even if other basic blocks may have BTI.
-define internal void @f1i(i64 %v) "patchable-function-entry"="1" "branch-target-enforcement" {
+define internal void @f1i(i64 %v) "patchable-function-entry"="1" "branch-target-enforcement"="true" {
 ; CHECK-LABEL: f1i:
 ; CHECK-NEXT: .Lfunc_begin3:
 ; CHECK:  // %bb.0:
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-9.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=aarch64-linux %s   -o - | \
+; RUN:   FileCheck %s --check-prefix=ASM
+; RUN: llc -mtriple=aarch64-linux %s -filetype=obj -o - | \
+; RUN:   llvm-readelf --notes | FileCheck %s --check-prefix=OBJ
+
+define dso_local i32 @f() #0 {
+entry:
+  ret i32 0
+}
+
+define dso_local i32 @g() {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "branch-target-enforcement"="true" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"branch-target-enforcement", i32 1}
+
+; Only the common atttribute (BTI)
+; ASM:	.word	3221225472
+; ASM-NEXT:	.word	4
+; ASM-NEXT	.word	1
+
+; OBJ: Properties: aarch64 feature: BTI
Index: llvm/test/CodeGen/AArch64/note-gnu-property-pac-bti-8.ll

[PATCH] D75181: [AArch64] Handle BTI/PAC in case of generated functions.

2020-03-04 Thread Daniel Kiss via Phabricator via cfe-commits

danielkiss marked 4 inline comments as done.
danielkiss added inline comments.



Comment at: clang/lib/CodeGen/CGCall.cpp:1828
+  if (CodeGenOpts.BranchTargetEnforcement) {
+FuncAttrs.addAttribute("branch-target-enforcement", "true");
+  }

chill wrote:
> I would really prefer to not set values "true" or "false" for the attribute: 
> we don't really have tri-state logic there 
> (absent/present-true/present-false), and those values just add some not-very 
> useful string processing.
> 
the attribute will be  "absent" for the runtime emitted function.



Comment at: clang/lib/CodeGen/CGCall.cpp:1831
+
+  auto RASignKind = CodeGenOpts.getSignReturnAddress();
+  if (RASignKind != CodeGenOptions::SignReturnAddressScope::None) {

chill wrote:
> What do we get from setting the PACBTI state in the  default function 
> attributes? We still have 
> to do a per function processing, we can just as well avoid repeating the 
> logic, and spare us some
> adding and potentially removing attributes churn.
> 
in the new patch the per function processing will change the attribute only if 
really need.



Comment at: llvm/lib/Target/AArch64/AArch64BranchTargets.cpp:62
+
+  // LLVM emmited function won't have the attribute.
+  if (!F.hasFnAttribute("branch-target-enforcement")) {

emmited -> emitted


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75181/new/

https://reviews.llvm.org/D75181



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