[PATCH] D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info

2021-12-19 Thread Haocong Lu via Phabricator via cfe-commits 
Luhaocong added a comment.

ping. Hi everyone, can you please help me review?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115430/new/

https://reviews.llvm.org/D115430

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[PATCH] D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info

2021-12-12 Thread Haocong Lu via Phabricator via cfe-commits 
Luhaocong updated this revision to Diff 393788.
Luhaocong added a comment.

re-upload with full context


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115430/new/

https://reviews.llvm.org/D115430

Files:
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c


Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
+++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
@@ -9,7 +9,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, 
DW_OP_minus))
 
 __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t 
arg_2) {
   __rvv_int16mf2_t ret;
@@ -17,7 +17,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, 
DW_OP_minus))
 
 __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t 
arg_2) {
   __rvv_int32mf2_t ret;
@@ -25,4 +25,4 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, 
DW_OP_minus))
Index: clang/lib/CodeGen/CGDebugInfo.cpp
===
--- clang/lib/CodeGen/CGDebugInfo.cpp
+++ clang/lib/CodeGen/CGDebugInfo.cpp
@@ -768,7 +768,7 @@
   }
 
   // Element count = (VLENB / SEW) x LMUL
-  SmallVector Expr(
+  SmallVector Expr(
   // The DW_OP_bregx operation has two operands: a register which is
   // specified by an unsigned LEB128 number, followed by a signed 
LEB128
   // offset.
@@ -782,6 +782,8 @@
 Expr.push_back(llvm::dwarf::DW_OP_div);
   else
 Expr.push_back(llvm::dwarf::DW_OP_mul);
+  // Element max index = count - 1
+  Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
 
   auto *LowerBound =
   llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(


Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
+++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
@@ -9,7 +9,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2) {
   __rvv_int16mf2_t ret;
@@ -17,7 +17,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2) {
   __rvv_int32mf2_t ret;
@@ -25,4 +25,4 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))
Index: clang/lib/CodeGen/CGDebugInfo.cpp
===
--- clang/lib/CodeGen/CGDebugInfo.cpp
+++ clang/lib/CodeGen/CGDebugInfo.cpp
@@ -768,7 +768,7 @@
   }
 
   // Element count = (VLENB / SEW) x LMUL
-  SmallVector Expr(
+  SmallVector Expr(
   // The DW_OP_bregx operation has two operands: a register which is
   // specified by an unsigned LEB128 number, followed by a signed LEB128
   // offset.
@@ -782,6 +782,8 @@
 Expr.push_back(llvm::dwarf::DW_OP_div);
   else
 Expr.push_back(llvm::dwarf::DW_OP_mul);
+  // Element max index = count - 1
+  Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
 
   auto *LowerBound =
   llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(
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[PATCH] D115430: [RISCV] Fix upper bound of RISC-V V type in debug info

2021-12-09 Thread Haocong Lu via Phabricator via cfe-commits 
Luhaocong created this revision.
Luhaocong added reviewers: craig.topper, rogfer01, frasercrmck, arcbbb, luke957.
Luhaocong added a project: clang.
Herald added subscribers: VincentWu, achieveartificialintelligence, vkmr, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Luhaocong requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.

The UpperBound of RVV type in debug info should be elements count minus one,
as the LowerBound start from zero.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D115430

Files:
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c


Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
+++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
@@ -9,7 +9,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, 
DW_OP_minus))
 
 __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t 
arg_2) {
   __rvv_int16mf2_t ret;
@@ -17,7 +17,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, 
DW_OP_minus))
 
 __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t 
arg_2) {
   __rvv_int32mf2_t ret;
@@ -25,4 +25,4 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, 
DW_OP_minus))
Index: clang/lib/CodeGen/CGDebugInfo.cpp
===
--- clang/lib/CodeGen/CGDebugInfo.cpp
+++ clang/lib/CodeGen/CGDebugInfo.cpp
@@ -768,7 +768,7 @@
   }
 
   // Element count = (VLENB / SEW) x LMUL
-  SmallVector Expr(
+  SmallVector Expr(
   // The DW_OP_bregx operation has two operands: a register which is
   // specified by an unsigned LEB128 number, followed by a signed 
LEB128
   // offset.
@@ -782,6 +782,8 @@
 Expr.push_back(llvm::dwarf::DW_OP_div);
   else
 Expr.push_back(llvm::dwarf::DW_OP_mul);
+  // Element max index = count - 1
+  Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
 
   auto *LowerBound =
   llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(


Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
+++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
@@ -9,7 +9,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2) {
   __rvv_int16mf2_t ret;
@@ -17,7 +17,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2) {
   __rvv_int32mf2_t ret;
@@ -25,4 +25,4 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))
Index: clang/lib/CodeGen/CGDebugInfo.cpp
===
--- clang/lib/CodeGen/CGDebugInfo.cpp
+++ clang/lib/CodeGen/CGDebugInfo.cpp
@@ -768,7 +768,7 @@
   }
 
   // Element count = (VLENB / SEW) x LMUL
-  SmallVector Expr(
+  SmallVector Expr(
   // The DW_OP_bregx operation has two operands: a register which is
   // specified by an unsigned LEB128 number, followed by a signed LEB128
   // offset.
@@ -782,6 +782,8 @@
 Expr.push_back(llvm::dwarf::DW_OP_div);
   else
 Expr.push_back(llvm::dwarf::DW_OP_mul);
+  // Element max index = count - 1
+  Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
 
   auto *LowerBound =
   llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSig