r361261 - [ARM][CMSE] Add commandline option and feature macro
Author: javed.absar
Date: Tue May 21 07:21:26 2019
New Revision: 361261
URL: http://llvm.org/viewvc/llvm-project?rev=361261=rev
Log:
[ARM][CMSE] Add commandline option and feature macro
Defines macro ARM_FEATURE_CMSE to 1 for v8-M targets and introduces
-mcmse option which for v8-M targets sets ARM_FEATURE_CMSE to 3.
A diagnostic is produced when the option is given on architectures
without support for Security Extensions.
Reviewed By: dmgreen, snidertm
Differential Revision: https://reviews.llvm.org/D59879
Modified:
cfe/trunk/include/clang/Basic/Attr.td
cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td
cfe/trunk/include/clang/Basic/LangOptions.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/ARM.cpp
cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp
cfe/trunk/test/Preprocessor/arm-target-features.c
Modified: cfe/trunk/include/clang/Basic/Attr.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/Attr.td?rev=361261=361260=361261=diff
==
--- cfe/trunk/include/clang/Basic/Attr.td (original)
+++ cfe/trunk/include/clang/Basic/Attr.td Tue May 21 07:21:26 2019
@@ -299,6 +299,9 @@ def ObjC : LangOpt<"ObjC">;
def BlocksSupported : LangOpt<"Blocks">;
def ObjCAutoRefCount : LangOpt<"ObjCAutoRefCount">;
+// Language option for CMSE extensions
+def Cmse : LangOpt<"Cmse">;
+
// Defines targets for target-specific attributes. Empty lists are unchecked.
class TargetSpec {
// Specifies Architectures for which the target applies, based off the
Modified: cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td?rev=361261=361260=361261=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td Tue May 21 07:21:26
2019
@@ -252,6 +252,8 @@ def err_target_unsupported_unaligned : E
"the %0 sub-architecture does not support unaligned accesses">;
def err_target_unsupported_execute_only : Error<
"execute only is not supported for the %0 sub-architecture">;
+def err_target_unsupported_mcmse : Error<
+ "-mcmse is not supported for %0">;
def err_opt_not_valid_with_opt : Error<
"option '%0' cannot be specified with '%1'">;
def err_opt_not_valid_without_opt : Error<
Modified: cfe/trunk/include/clang/Basic/LangOptions.def
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/LangOptions.def?rev=361261=361260=361261=diff
==
--- cfe/trunk/include/clang/Basic/LangOptions.def (original)
+++ cfe/trunk/include/clang/Basic/LangOptions.def Tue May 21 07:21:26 2019
@@ -300,6 +300,8 @@ LANGOPT(SanitizeAddressFieldPadding, 2,
"field padding (0: none, 1:least "
"aggressive, 2: more aggressive)")
+LANGOPT(Cmse, 1, 0, "ARM Security extensions support")
+
LANGOPT(XRayInstrument, 1, 0, "controls whether to do XRay instrumentation")
LANGOPT(XRayAlwaysEmitCustomEvents, 1, 0,
"controls whether to always emit intrinsic calls to "
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=361261=361260=361261=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Tue May 21 07:21:26 2019
@@ -2143,6 +2143,9 @@ def mnocrc : Flag<["-"], "mnocrc">, Grou
HelpText<"Disallow use of CRC instructions (ARM only)">;
def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">,
Group,
HelpText<"Disallow converting instructions with negative immediates to their
negation or inversion.">;
+def mcmse : Flag<["-"], "mcmse">, Group,
+ Flags<[DriverOption,CC1Option]>,
+ HelpText<"Allow use of CMSE (Armv8-M Security Extensions)">;
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">,
Group,
HelpText<"Generate code which only uses the general purpose registers
(AArch64 only)">;
Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.cpp?rev=361261=361260=361261=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp Tue May 21 07:21:26 2019
@@ -434,6 +434,11 @@ bool ARMTargetInfo::handleTargetFeatures
DSP = 1;
} else if (Feature == "+fp-only-sp") {
HW_FP_remove |= HW_FP_DP;
+} else if (Feature == "+8msecext") {
+ if (CPUProfile !=
r359348 - [AArch64] Add support for MTE intrinsics
Author: javed.absar
Date: Fri Apr 26 14:08:11 2019
New Revision: 359348
URL: http://llvm.org/viewvc/llvm-project?rev=359348=rev
Log:
[AArch64] Add support for MTE intrinsics
This provides intrinsics support for Memory Tagging Extension (MTE),
which was introduced with the Armv8.5-a architecture.
These intrinsics are available when __ARM_FEATURE_MEMORY_TAGGING is defined.
Each intrinsic is described in detail in the ACLE Q1 2019 documentation:
https://developer.arm.com/docs/101028/latest
Reviewed By: Tim Nortover, David Spickett
Differential Revision: https://reviews.llvm.org/D60485
Added:
cfe/trunk/test/CodeGen/arm64-mte.c
cfe/trunk/test/Sema/builtins-arm64-mte.c
Modified:
cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
cfe/trunk/include/clang/Sema/Sema.h
cfe/trunk/lib/Basic/Targets/AArch64.cpp
cfe/trunk/lib/Basic/Targets/AArch64.h
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/Headers/arm_acle.h
cfe/trunk/lib/Sema/SemaChecking.cpp
cfe/trunk/test/Preprocessor/aarch64-target-features.c
Modified: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAArch64.def?rev=359348=359347=359348=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def Fri Apr 26 14:08:11 2019
@@ -52,6 +52,14 @@ BUILTIN(__builtin_arm_crc32cw, "UiUiUi",
BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc")
BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc")
+// Memory Tagging Extensions (MTE)
+BUILTIN(__builtin_arm_irg, "v*v*Ui", "t")
+BUILTIN(__builtin_arm_addg, "v*v*Ui", "t")
+BUILTIN(__builtin_arm_gmi, "Uiv*Ui", "t")
+BUILTIN(__builtin_arm_ldg, "v*v*", "t")
+BUILTIN(__builtin_arm_stg, "vv*", "t")
+BUILTIN(__builtin_arm_subp, "Uiv*v*", "t")
+
// Memory barrier
BUILTIN(__builtin_arm_dmb, "vUi", "nc")
BUILTIN(__builtin_arm_dsb, "vUi", "nc")
Modified: cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td?rev=359348=359347=359348=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td Fri Apr 26 14:08:11
2019
@@ -9621,6 +9621,18 @@ def err_std_compare_type_not_supported :
"the type is not trivially copyable|"
"the type does not have the expected form}1">;
+// Memory Tagging Extensions (MTE) diagnostics
+def err_memtag_arg_null_or_pointer : Error<
+ "%0 argument of MTE builtin function must be a null or a pointer (%1
invalid)">;
+def err_memtag_any2arg_pointer : Error<
+ "at least one argument of MTE builtin function must be a pointer (%0, %1
invalid)">;
+def err_memtag_arg_must_be_pointer : Error<
+ "%0 argument of MTE builtin function must be a pointer (%1 invalid)">;
+def err_memtag_arg_must_be_integer : Error<
+ "%0 argument of MTE builtin function must be an integer type (%1 invalid)">;
+def err_memtag_arg_must_be_unsigned : Error<
+ "%0 argument of MTE builtin function must be an unsigned integer type (%1
invalid)">;
+
def warn_dereference_of_noderef_type : Warning<
"dereferencing %0; was declared with a 'noderef' type">, InGroup;
def warn_dereference_of_noderef_type_no_decl : Warning<
Modified: cfe/trunk/include/clang/Sema/Sema.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Sema/Sema.h?rev=359348=359347=359348=diff
==
--- cfe/trunk/include/clang/Sema/Sema.h (original)
+++ cfe/trunk/include/clang/Sema/Sema.h Fri Apr 26 14:08:11 2019
@@ -10759,6 +10759,7 @@ private:
bool SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,
int ArgNum, unsigned ExpectedFieldNum,
bool AllowName);
+ bool SemaBuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall);
public:
enum FormatStringType {
FST_Scanf,
Modified: cfe/trunk/lib/Basic/Targets/AArch64.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AArch64.cpp?rev=359348=359347=359348=diff
==
--- cfe/trunk/lib/Basic/Targets/AArch64.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AArch64.cpp Fri Apr 26 14:08:11 2019
@@ -194,6 +194,9 @@ void AArch64TargetInfo::getTargetDefines
if (HasDotProd)
Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1");
+ if (HasMTE)
+Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1");
+
if ((FPU & NeonMode) && HasFP16FML)
Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
@@ -258,6 +261,8 @@ bool AArch64TargetInfo::handleTargetFeat
HasDotProd = 1;
if (Feature
r304889 - [ARM] Fix Neon vector type alignment to 64-bit
Author: javed.absar
Date: Wed Jun 7 05:02:02 2017
New Revision: 304889
URL: http://llvm.org/viewvc/llvm-project?rev=304889=rev
Log:
[ARM] Fix Neon vector type alignment to 64-bit
This is restricted version of patch - https://reviews.llvm.org/D33205
that I reverted as it was leading to ABI breaks on darwin etc.
This patch restricts the fix to AAPCS (Android remains 128-bit).
Reviewed by: Renato Golin, Stephen Hines
Differential Revision: https://reviews.llvm.org/D33786
Added:
cfe/trunk/test/CodeGen/neon-aapcs-align.c
Modified:
cfe/trunk/lib/Basic/Targets.cpp
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304889=304888=304889=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Wed Jun 7 05:02:02 2017
@@ -5385,6 +5385,10 @@ public:
// ARM has atomics up to 8 bytes
setAtomic();
+// Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
+if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android))
+ MaxVectorAlign = 64;
+
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
// that follows it, `bar', `bar' will be aligned as the type of the
Added: cfe/trunk/test/CodeGen/neon-aapcs-align.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/neon-aapcs-align.c?rev=304889=auto
==
--- cfe/trunk/test/CodeGen/neon-aapcs-align.c (added)
+++ cfe/trunk/test/CodeGen/neon-aapcs-align.c Wed Jun 7 05:02:02 2017
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple armv7a-none-eabi -target-feature +neon -emit-llvm
-o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS
+// RUN: %clang_cc1 -triple armv7a-none-gnueabi -target-feature +neon
-emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS
+// RUN: %clang_cc1 -triple armv7a-none-freebsd -target-feature +neon
-emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS
+
+// RUN: %clang_cc1 -triple armv7a-apple-ios -target-feature +neon -emit-llvm
-o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT
+// RUN: %clang_cc1 -triple armv7a-none-android -target-feature +neon
-emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT
+// RUN: %clang_cc1 -triple armv7a-none-androideabi -target-feature +neon
-emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT
+
+#include
+// Neon types have 64-bit alignment
+int32x4_t gl_b;
+void t3(int32x4_t *src) {
+// CHECK: @t3
+ gl_b = *src;
+// AAPCS: store <4 x i32> {{%.*}}, <4 x i32>* @gl_b, align 8
+// DEFAULT: store <4 x i32> {{%.*}}, <4 x i32>* @gl_b, align 16
+}
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r304705 - Add support for #pragma clang section
Author: javed.absar
Date: Mon Jun 5 05:11:57 2017
New Revision: 304705
URL: http://llvm.org/viewvc/llvm-project?rev=304705=rev
Log:
Add support for #pragma clang section
This patch provides a means to specify section-names for global variables,
functions and static variables, using #pragma directives.
This feature is only defined to work sensibly for ELF targets.
One can specify section names as:
#pragma clang section bss="myBSS" data="myData" rodata="myRodata" text="myText"
One can "unspecify" a section name with empty string e.g.
#pragma clang section bss="" data="" text="" rodata=""
Reviewers: Roger Ferrer, Jonathan Roelofs, Reid Kleckner
Differential Revision: https://reviews.llvm.org/D33412
Added:
cfe/trunk/test/CodeGenCXX/clang-sections-tentative.c
cfe/trunk/test/CodeGenCXX/clang-sections.cpp
cfe/trunk/test/Sema/pragma-clang-section.c
Modified:
cfe/trunk/docs/LanguageExtensions.rst
cfe/trunk/include/clang/Basic/Attr.td
cfe/trunk/include/clang/Basic/DiagnosticParseKinds.td
cfe/trunk/include/clang/Parse/Parser.h
cfe/trunk/include/clang/Sema/Sema.h
cfe/trunk/lib/CodeGen/CGDecl.cpp
cfe/trunk/lib/CodeGen/CodeGenModule.cpp
cfe/trunk/lib/Parse/ParsePragma.cpp
cfe/trunk/lib/Sema/SemaAttr.cpp
cfe/trunk/lib/Sema/SemaDecl.cpp
Modified: cfe/trunk/docs/LanguageExtensions.rst
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/docs/LanguageExtensions.rst?rev=304705=304704=304705=diff
==
--- cfe/trunk/docs/LanguageExtensions.rst (original)
+++ cfe/trunk/docs/LanguageExtensions.rst Mon Jun 5 05:11:57 2017
@@ -2521,3 +2521,45 @@ whether or not an attribute is supported
The attributes are applied to all matching declarations individually, even when
the attribute is semantically incorrect. The attributes that aren't applied to
any declaration are not verified semantically.
+
+Specifying section names for global objects (#pragma clang section)
+===
+
+The ``#pragma clang section`` directive provides a means to assign
section-names
+to global variables, functions and static variables.
+
+The section names can be specified as:
+
+.. code-block:: c++
+
+ #pragma clang section bss="myBSS" data="myData" rodata="myRodata"
text="myText"
+
+The section names can be reverted back to default name by supplying an empty
+string to the section kind, for example:
+
+.. code-block:: c++
+
+ #pragma clang section bss="" data="" text="" rodata=""
+
+The ``#pragma clang section`` directive obeys the following rules:
+
+* The pragma applies to all global variable, statics and function declarations
+ from the pragma to the end of the translation unit.
+
+* The pragma clang section is enabled automatically, without need of any flags.
+
+* This feature is only defined to work sensibly for ELF targets.
+
+* If section name is specified through _attribute_((section("myname"))), then
+ the attribute name gains precedence.
+
+* Global variables that are initialized to zero will be placed in the named
+ bss section, if one is present.
+
+* The ``#pragma clang section`` directive does not does try to infer
section-kind
+ from the name. For example, naming a section "``.bss.mySec``" does NOT mean
+ it will be a bss section name.
+
+* The decision about which section-kind applies to each global is taken in the
back-end.
+ Once the section-kind is known, appropriate section name, as specified by
the user using
+ ``#pragma clang section`` directive, is applied to that global.
Modified: cfe/trunk/include/clang/Basic/Attr.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/Attr.td?rev=304705=304704=304705=diff
==
--- cfe/trunk/include/clang/Basic/Attr.td (original)
+++ cfe/trunk/include/clang/Basic/Attr.td Mon Jun 5 05:11:57 2017
@@ -1683,6 +1683,42 @@ def Section : InheritableAttr {
let Documentation = [SectionDocs];
}
+def PragmaClangBSSSection : InheritableAttr {
+ // This attribute has no spellings as it is only ever created implicitly.
+ let Spellings = [];
+ let Args = [StringArgument<"Name">];
+ let Subjects = SubjectList<[GlobalVar], ErrorDiag,
+ "ExpectedFunctionMethodOrGlobalVar">;
+ let Documentation = [Undocumented];
+}
+
+def PragmaClangDataSection : InheritableAttr {
+ // This attribute has no spellings as it is only ever created implicitly.
+ let Spellings = [];
+ let Args = [StringArgument<"Name">];
+ let Subjects = SubjectList<[GlobalVar], ErrorDiag,
+ "ExpectedFunctionMethodOrGlobalVar">;
+ let Documentation = [Undocumented];
+}
+
+def PragmaClangRodataSection : InheritableAttr {
+ // This attribute has no spellings as it is only ever created implicitly.
+ let Spellings = [];
+ let Args = [StringArgument<"Name">];
+ let Subjects =
r304220 - Reverting Neon vector type 64-alignment fix
Author: javed.absar
Date: Tue May 30 12:09:47 2017
New Revision: 304220
URL: http://llvm.org/viewvc/llvm-project?rev=304220=rev
Log:
Reverting Neon vector type 64-alignment fix
The patch caused ABI breaks on darwin/others.
Reverting to come back with a more restrictive patch.
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/CodeGen/arm-abi-vector.c
cfe/trunk/test/CodeGen/arm-neon-misc.c
cfe/trunk/test/CodeGen/arm-swiftcall.c
cfe/trunk/test/CodeGen/armv7k-abi.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304220=304219=304220=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue May 30 12:09:47 2017
@@ -5382,11 +5382,6 @@ public:
// ARM has atomics up to 8 bytes
setAtomic();
-if (Triple.getEnvironment() == llvm::Triple::Android)
- MaxVectorAlign = 128; // don't break existing Android ABI
-else
- MaxVectorAlign = 64; // AAPCS
-
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
// that follows it, `bar', `bar' will be aligned as the type of the
Modified: cfe/trunk/test/CodeGen/arm-abi-vector.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-abi-vector.c?rev=304220=304219=304220=diff
==
--- cfe/trunk/test/CodeGen/arm-abi-vector.c (original)
+++ cfe/trunk/test/CodeGen/arm-abi-vector.c Tue May 30 12:09:47 2017
@@ -133,20 +133,20 @@ double test_5c(__char5 *in) {
double varargs_vec_9c(int fixed, ...) {
// CHECK: varargs_vec_9c
-// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 8
+// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 16
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <9 x i8>*
// CHECK: [[T0:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 8
-// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 8
+// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 16
// APCS-GNU: varargs_vec_9c
-// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 8
+// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 16
// APCS-GNU: [[AP:%.*]] = load i8*,
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <9 x i8>*
// APCS-GNU: [[VEC:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 4
-// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 8
+// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 16
// ANDROID: varargs_vec_9c
// ANDROID: [[VAR:%.*]] = alloca <9 x i8>, align 16
// ANDROID: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
@@ -246,15 +246,15 @@ double test_3s(__short3 *in) {
double varargs_vec_5s(int fixed, ...) {
// CHECK: varargs_vec_5s
-// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 8
+// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 16
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <5 x i16>*
// CHECK: [[VEC:%.*]] = load <5 x i16>, <5 x i16>* [[AP_CAST]], align 8
-// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 8
+// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 16
// APCS-GNU: varargs_vec_5s
-// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 8
+// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 16
// APCS-GNU: [[AP:%.*]] = load i8*,
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <5 x i16>*
Modified: cfe/trunk/test/CodeGen/arm-neon-misc.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-neon-misc.c?rev=304220=304219=304220=diff
==
--- cfe/trunk/test/CodeGen/arm-neon-misc.c (original)
+++ cfe/trunk/test/CodeGen/arm-neon-misc.c Tue May 30 12:09:47 2017
@@ -32,11 +32,3 @@ void t2(uint64_t *src1, uint8_t *src2, u
*dst = q;
// CHECK: store <2 x i64>
}
-
-// Neon types have 64-bit alignment
-int32x4_t gl_b;
-void t3(int32x4_t *src) {
-// CHECK: @t3
- gl_b = *src;
-// CHECK: store <4 x i32> {{%.*}}, <4 x i32>* @gl_b, align 8
-}
Modified: cfe/trunk/test/CodeGen/arm-swiftcall.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-swiftcall.c?rev=304220=304219=304220=diff
==
--- cfe/trunk/test/CodeGen/arm-swiftcall.c (original)
+++
Re: r304201 - [ARM] Fix Neon vector type alignment to 64-bit
Sorry, I didn't see the email from Ahmed. I think best option is to revert
right now and submit for review a restricted version later as suggested.
Will do revert.
Thanks
Javed
From: Javed Absar
Sent: 30 May 2017 17:43:35
To: Vedant Kumar
Cc: cfe-commits; Diana Picus
Subject: Re: r304201 - [ARM] Fix Neon vector type alignment to 64-bit
Hi.
I fixed the tests
- union-align.c and bool_casts.cl
Did you mean this error now:
FAILED: lib/Target/ARM/ARMGenGlobalISel.inc.tmp "
because that doesn't seem related to alignment fix.
Thanks
Javed
From: v...@apple.com <v...@apple.com> on behalf of Vedant Kumar <v...@apple.com>
Sent: 30 May 2017 17:06
To: Javed Absar
Cc: cfe-commits; Diana Picus
Subject: Re: r304201 - [ARM] Fix Neon vector type alignment to 64-bit
Hi,
I think this change is responsible for a tablgen failure in stage2 builds:
http://green.lab.llvm.org/green/job/clang-stage2-configure-Rthinlto_build/2171/
On May 30, 2017, at 4:59 AM, Diana Picus via cfe-commits
<cfe-commits@lists.llvm.org<mailto:cfe-commits@lists.llvm.org>> wrote:
Hi Javed,
I think this broke the bots:
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/7620
Can you have a look, or revert?
+ 1
best,
vedant
Thanks,
Diana
On 30 May 2017 at 12:12, Javed Absar via cfe-commits
<cfe-commits@lists.llvm.org<mailto:cfe-commits@lists.llvm.org>> wrote:
Author: javed.absar
Date: Tue May 30 05:12:15 2017
New Revision: 304201
URL: http://llvm.org/viewvc/llvm-project?rev=304201=rev
Log:
[ARM] Fix Neon vector type alignment to 64-bit
The maximum alignment for ARM NEON data types should be 64-bits as specified
in ARM procedure call standard document Sec. A.2 Notes.
This patch fixes it from its current larger natural default values, except
for Android (so as not to break existing ABI).
Reviewed by: Stephen Hines, Renato Golin.
Differential Revision: https://reviews.llvm.org/D33205
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/CodeGen/arm-abi-vector.c
cfe/trunk/test/CodeGen/arm-neon-misc.c
cfe/trunk/test/CodeGen/arm-swiftcall.c
cfe/trunk/test/CodeGen/armv7k-abi.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304201=304200=304201=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue May 30 05:12:15 2017
@@ -5382,6 +5382,11 @@ public:
// ARM has atomics up to 8 bytes
setAtomic();
+if (Triple.getEnvironment() == llvm::Triple::Android)
+ MaxVectorAlign = 128; // don't break existing Android ABI
+else
+ MaxVectorAlign = 64; // AAPCS
+
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
// that follows it, `bar', `bar' will be aligned as the type of the
Modified: cfe/trunk/test/CodeGen/arm-abi-vector.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-abi-vector.c?rev=304201=304200=304201=diff
==
--- cfe/trunk/test/CodeGen/arm-abi-vector.c (original)
+++ cfe/trunk/test/CodeGen/arm-abi-vector.c Tue May 30 05:12:15 2017
@@ -133,20 +133,20 @@ double test_5c(__char5 *in) {
double varargs_vec_9c(int fixed, ...) {
// CHECK: varargs_vec_9c
-// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 16
+// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 8
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <9 x i8>*
// CHECK: [[T0:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 8
-// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 16
+// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 8
// APCS-GNU: varargs_vec_9c
-// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 16
+// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 8
// APCS-GNU: [[AP:%.*]] = load i8*,
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <9 x i8>*
// APCS-GNU: [[VEC:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 4
-// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 16
+// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 8
// ANDROID: varargs_vec_9c
// ANDROID: [[VAR:%.*]] = alloca <9 x i8>, align 16
// ANDROID: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
@@ -246,15 +246,15 @@ double test_3s(__short3 *in) {
double varargs_vec_5s(int fixed, ...) {
// CHECK: varargs_vec_5s
-// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i
Re: r304201 - [ARM] Fix Neon vector type alignment to 64-bit
Hi.
I fixed the tests
- union-align.c and bool_casts.cl
Did you mean this error now:
FAILED: lib/Target/ARM/ARMGenGlobalISel.inc.tmp "
because that doesn't seem related to alignment fix.
Thanks
Javed
From: v...@apple.com <v...@apple.com> on behalf of Vedant Kumar <v...@apple.com>
Sent: 30 May 2017 17:06
To: Javed Absar
Cc: cfe-commits; Diana Picus
Subject: Re: r304201 - [ARM] Fix Neon vector type alignment to 64-bit
Hi,
I think this change is responsible for a tablgen failure in stage2 builds:
http://green.lab.llvm.org/green/job/clang-stage2-configure-Rthinlto_build/2171/
On May 30, 2017, at 4:59 AM, Diana Picus via cfe-commits
<cfe-commits@lists.llvm.org<mailto:cfe-commits@lists.llvm.org>> wrote:
Hi Javed,
I think this broke the bots:
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/7620
Can you have a look, or revert?
+ 1
best,
vedant
Thanks,
Diana
On 30 May 2017 at 12:12, Javed Absar via cfe-commits
<cfe-commits@lists.llvm.org<mailto:cfe-commits@lists.llvm.org>> wrote:
Author: javed.absar
Date: Tue May 30 05:12:15 2017
New Revision: 304201
URL: http://llvm.org/viewvc/llvm-project?rev=304201=rev
Log:
[ARM] Fix Neon vector type alignment to 64-bit
The maximum alignment for ARM NEON data types should be 64-bits as specified
in ARM procedure call standard document Sec. A.2 Notes.
This patch fixes it from its current larger natural default values, except
for Android (so as not to break existing ABI).
Reviewed by: Stephen Hines, Renato Golin.
Differential Revision: https://reviews.llvm.org/D33205
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/CodeGen/arm-abi-vector.c
cfe/trunk/test/CodeGen/arm-neon-misc.c
cfe/trunk/test/CodeGen/arm-swiftcall.c
cfe/trunk/test/CodeGen/armv7k-abi.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304201=304200=304201=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue May 30 05:12:15 2017
@@ -5382,6 +5382,11 @@ public:
// ARM has atomics up to 8 bytes
setAtomic();
+if (Triple.getEnvironment() == llvm::Triple::Android)
+ MaxVectorAlign = 128; // don't break existing Android ABI
+else
+ MaxVectorAlign = 64; // AAPCS
+
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
// that follows it, `bar', `bar' will be aligned as the type of the
Modified: cfe/trunk/test/CodeGen/arm-abi-vector.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-abi-vector.c?rev=304201=304200=304201=diff
==
--- cfe/trunk/test/CodeGen/arm-abi-vector.c (original)
+++ cfe/trunk/test/CodeGen/arm-abi-vector.c Tue May 30 05:12:15 2017
@@ -133,20 +133,20 @@ double test_5c(__char5 *in) {
double varargs_vec_9c(int fixed, ...) {
// CHECK: varargs_vec_9c
-// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 16
+// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 8
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <9 x i8>*
// CHECK: [[T0:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 8
-// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 16
+// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 8
// APCS-GNU: varargs_vec_9c
-// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 16
+// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 8
// APCS-GNU: [[AP:%.*]] = load i8*,
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <9 x i8>*
// APCS-GNU: [[VEC:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 4
-// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 16
+// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 8
// ANDROID: varargs_vec_9c
// ANDROID: [[VAR:%.*]] = alloca <9 x i8>, align 16
// ANDROID: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
@@ -246,15 +246,15 @@ double test_3s(__short3 *in) {
double varargs_vec_5s(int fixed, ...) {
// CHECK: varargs_vec_5s
-// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 16
+// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 8
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <5 x i16>*
// CHECK: [[VEC:%.*]] = load <5 x i1
r304210 - Fix issue with test that caused bildbot failure
Author: javed.absar Date: Tue May 30 08:34:26 2017 New Revision: 304210 URL: http://llvm.org/viewvc/llvm-project?rev=304210=rev Log: Fix issue with test that caused bildbot failure These tests did not specify the target. The failure was triggered by change - https://reviews.llvm.org/D33205 http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-full/builds/7314 which sets vector alignment to 8-byte for arm-targets (except for Android). So, fixing the test to make it target specific. Modified: cfe/trunk/test/CodeGen/union-align.c cfe/trunk/test/CodeGenOpenCL/bool_cast.cl Modified: cfe/trunk/test/CodeGen/union-align.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/union-align.c?rev=304210=304209=304210=diff == --- cfe/trunk/test/CodeGen/union-align.c (original) +++ cfe/trunk/test/CodeGen/union-align.c Tue May 30 08:34:26 2017 @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -emit-llvm %s -o - | grep load | grep "4 x float" | not grep "align 4" -// RUN: %clang_cc1 -emit-llvm %s -o - | grep load | grep "4 x float" | grep "align 16" +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | grep load | grep "4 x float" | not grep "align 4" +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | grep load | grep "4 x float" | grep "align 16" // PR3432 // rdar://6536377 Modified: cfe/trunk/test/CodeGenOpenCL/bool_cast.cl URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/bool_cast.cl?rev=304210=304209=304210=diff == --- cfe/trunk/test/CodeGenOpenCL/bool_cast.cl (original) +++ cfe/trunk/test/CodeGenOpenCL/bool_cast.cl Tue May 30 08:34:26 2017 @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - -O0 | FileCheck %s +// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -o - -O0 | FileCheck %s typedef unsigned char uchar4 __attribute((ext_vector_type(4))); typedef unsigned int int4 __attribute((ext_vector_type(4))); ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r304201 - [ARM] Fix Neon vector type alignment to 64-bit
Author: javed.absar
Date: Tue May 30 05:12:15 2017
New Revision: 304201
URL: http://llvm.org/viewvc/llvm-project?rev=304201=rev
Log:
[ARM] Fix Neon vector type alignment to 64-bit
The maximum alignment for ARM NEON data types should be 64-bits as specified
in ARM procedure call standard document Sec. A.2 Notes.
This patch fixes it from its current larger natural default values, except
for Android (so as not to break existing ABI).
Reviewed by: Stephen Hines, Renato Golin.
Differential Revision: https://reviews.llvm.org/D33205
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/CodeGen/arm-abi-vector.c
cfe/trunk/test/CodeGen/arm-neon-misc.c
cfe/trunk/test/CodeGen/arm-swiftcall.c
cfe/trunk/test/CodeGen/armv7k-abi.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304201=304200=304201=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue May 30 05:12:15 2017
@@ -5382,6 +5382,11 @@ public:
// ARM has atomics up to 8 bytes
setAtomic();
+if (Triple.getEnvironment() == llvm::Triple::Android)
+ MaxVectorAlign = 128; // don't break existing Android ABI
+else
+ MaxVectorAlign = 64; // AAPCS
+
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
// that follows it, `bar', `bar' will be aligned as the type of the
Modified: cfe/trunk/test/CodeGen/arm-abi-vector.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-abi-vector.c?rev=304201=304200=304201=diff
==
--- cfe/trunk/test/CodeGen/arm-abi-vector.c (original)
+++ cfe/trunk/test/CodeGen/arm-abi-vector.c Tue May 30 05:12:15 2017
@@ -133,20 +133,20 @@ double test_5c(__char5 *in) {
double varargs_vec_9c(int fixed, ...) {
// CHECK: varargs_vec_9c
-// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 16
+// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 8
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <9 x i8>*
// CHECK: [[T0:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 8
-// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 16
+// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 8
// APCS-GNU: varargs_vec_9c
-// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 16
+// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 8
// APCS-GNU: [[AP:%.*]] = load i8*,
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <9 x i8>*
// APCS-GNU: [[VEC:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 4
-// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 16
+// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 8
// ANDROID: varargs_vec_9c
// ANDROID: [[VAR:%.*]] = alloca <9 x i8>, align 16
// ANDROID: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
@@ -246,15 +246,15 @@ double test_3s(__short3 *in) {
double varargs_vec_5s(int fixed, ...) {
// CHECK: varargs_vec_5s
-// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 16
+// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 8
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <5 x i16>*
// CHECK: [[VEC:%.*]] = load <5 x i16>, <5 x i16>* [[AP_CAST]], align 8
-// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 16
+// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 8
// APCS-GNU: varargs_vec_5s
-// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 16
+// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 8
// APCS-GNU: [[AP:%.*]] = load i8*,
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <5 x i16>*
Modified: cfe/trunk/test/CodeGen/arm-neon-misc.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-neon-misc.c?rev=304201=304200=304201=diff
==
--- cfe/trunk/test/CodeGen/arm-neon-misc.c (original)
+++ cfe/trunk/test/CodeGen/arm-neon-misc.c Tue May 30 05:12:15 2017
@@ -32,3 +32,11 @@ void t2(uint64_t *src1, uint8_t *src2, u
*dst = q;
// CHECK: store <2 x i64>
}
+
+// Neon types have 64-bit alignment
+int32x4_t gl_b;
+void t3(int32x4_t *src) {
+// CHECK: @t3
+ gl_b = *src;
+// CHECK: store <4 x i32> {{%.*}}, <4 x i32>* @gl_b, align 8
+}
Modified: cfe/trunk/test/CodeGen/arm-swiftcall.c
URL:
[PATCH] D25474: [ARM] Fix - missing target-cpu in test
This revision was automatically updated to reflect the committed changes.
Closed by commit rL284009: [ARM] Fix - missing target-cpu in test (authored by
javed.absar).
Changed prior to commit:
https://reviews.llvm.org/D25474?vs=74247=74365#toc
Repository:
rL LLVM
https://reviews.llvm.org/D25474
Files:
cfe/trunk/test/Driver/arm-cortex-cpus.c
Index: cfe/trunk/test/Driver/arm-cortex-cpus.c
===
--- cfe/trunk/test/Driver/arm-cortex-cpus.c
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c
@@ -165,7 +165,7 @@
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1
| \
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
-// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}}
"-target-cpu" "cortex-r52"
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-GENERIC %s
Index: cfe/trunk/test/Driver/arm-cortex-cpus.c
===
--- cfe/trunk/test/Driver/arm-cortex-cpus.c
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c
@@ -165,7 +165,7 @@
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1 | \
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
-// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu" "cortex-r52"
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r284009 - [ARM] Fix - missing target-cpu in test
Author: javed.absar
Date: Wed Oct 12 07:13:55 2016
New Revision: 284009
URL: http://llvm.org/viewvc/llvm-project?rev=284009=rev
Log:
[ARM] Fix - missing target-cpu in test
Fixes an incomplete test, wherein the target-cpu name (cortex-r52) was missing.
Differential Revision: http://reviews.llvm.org/D25474
Modified:
cfe/trunk/test/Driver/arm-cortex-cpus.c
Modified: cfe/trunk/test/Driver/arm-cortex-cpus.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-cortex-cpus.c?rev=284009=284008=284009=diff
==
--- cfe/trunk/test/Driver/arm-cortex-cpus.c (original)
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c Wed Oct 12 07:13:55 2016
@@ -165,7 +165,7 @@
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1
| \
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
-// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}}
"-target-cpu" "cortex-r52"
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-GENERIC %s
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D25474: [ARM] Fix - missing target-cpu in test
javed.absar created this revision.
javed.absar added reviewers: jmolloy, rengolin.
javed.absar added a subscriber: cfe-commits.
Herald added a subscriber: aemerson.
This patch fixes an incomplete test, wherein the target-cpu name (cortex-r52)
was missing.
https://reviews.llvm.org/D25474
Files:
test/Driver/arm-cortex-cpus.c
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -165,7 +165,7 @@
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1
| \
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
-// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}}
"-target-cpu" "cortex-r52"
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-GENERIC %s
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -165,7 +165,7 @@
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1 | \
// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
-// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu" "cortex-r52"
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A-GENERIC %s
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r283543 - [ARM]: Add Cortex-R52 target
Author: javed.absar
Date: Fri Oct 7 07:08:41 2016
New Revision: 283543
URL: http://llvm.org/viewvc/llvm-project?rev=283543=rev
Log:
[ARM]: Add Cortex-R52 target
This patch adds Cortex-R52, the new ARM real-time processor.
Cortex-R52 implements the ARMv8-R architecture.
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/arm-target-features.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=283543=283542=283543=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Fri Oct 7 07:08:41 2016
@@ -4929,6 +4929,8 @@ class ARMTargetInfo : public TargetInfo
return "8M_BASE";
case llvm::ARM::AK_ARMV8MMainline:
return "8M_MAIN";
+case llvm::ARM::AK_ARMV8R:
+ return "8R";
}
}
Modified: cfe/trunk/test/Driver/arm-cortex-cpus.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-cortex-cpus.c?rev=283543=283542=283543=diff
==
--- cfe/trunk/test/Driver/arm-cortex-cpus.c (original)
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c Fri Oct 7 07:08:41 2016
@@ -146,6 +146,27 @@
// RUN: %clang -target arm -mlittle-endian -march=armv8-a -mlittle-endian -###
-c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
// CHECK-V8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "cortex-a53"
+// RUN: %clang -target armv8r-linux-gnueabi -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// RUN: %clang -target arm -march=armv8r -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// RUN: %clang -target arm -march=armv8-r -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// CHECK-V8R: "-cc1"{{.*}} "-triple" "armv8r-{{.*}} "-target-cpu" "cortex-r52"
+
+// RUN: %clang -target armv8r-linux-gnueabi -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// RUN: %clang -target arm -march=armv8r -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// RUN: %clang -target arm -march=armv8-r -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// CHECK-V8R-BIG: "-cc1"{{.*}} "-triple" "armebv8r-{{.*}} "-target-cpu"
"cortex-r52"
+
+// RUN: %clang -target armv8r-linux-gnueabi -mthumb -### -c %s 2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB %s
+// RUN: %clang -target arm -march=armv8r -mthumb -### -c %s 2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB %s
+// CHECK-V8R-THUMB: "-cc1"{{.*}} "-triple" "thumbv8r-{{.*}} "-target-cpu"
"cortex-r52"
+// RUN: %clang -target armv8r-linux-gnueabi -mthumb -mbig-endian -### -c %s
2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
+// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1
| \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target armv8a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
@@ -502,6 +523,9 @@
// RUN: %clang -target arm -mcpu=exynos-m2 -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// CHECK-BE-CPUV8A: "-cc1"{{.*}} "-triple" "armebv8-{{.*}}
+// RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-r52 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8R %s
+// CHECK-CPUV8R: "-cc1"{{.*}} "-triple" "armv8r-{{.*}}
+
// RUN: %clang -target arm -mcpu=cortex-a32 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a35 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a53 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
Modified: cfe/trunk/test/Preprocessor/arm-target-features.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/arm-target-features.c?rev=283543=283542=283543=diff
==
--- cfe/trunk/test/Preprocessor/arm-target-features.c (original)
+++ cfe/trunk/test/Preprocessor/arm-target-features.c Fri Oct 7 07:08:41 2016
@@ -9,6 +9,15 @@
// CHECK-V8A: #define __ARM_FP16_ARGS 1
// CHECK-V8A: #define __ARM_FP16_FORMAT_IEEE 1
+// RUN: %clang -target armv8r-none-linux-gnu -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V8R %s
+// CHECK-V8R: #define __ARMEL__ 1
+// CHECK-V8R: #define __ARM_ARCH 8
+// CHECK-V8R: #define __ARM_ARCH_8R__ 1
+// CHECK-V8R: #define __ARM_FEATURE_CRC32 1
+// CHECK-V8R: #define
[PATCH] D25210: [ARM] Add Cortex-R52 target to CLANG
javed.absar updated this revision to Diff 73896.
javed.absar added a comment.
This patch changes the default cpu for armv8-r from 'generic' to cortex-r52.
This is also to reflect the equivalent changes made in llvm, based on review
comments.
https://reviews.llvm.org/D25210
Files:
lib/Basic/Targets.cpp
test/Driver/arm-cortex-cpus.c
test/Preprocessor/arm-target-features.c
Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -9,6 +9,15 @@
// CHECK-V8A: #define __ARM_FP16_ARGS 1
// CHECK-V8A: #define __ARM_FP16_FORMAT_IEEE 1
+// RUN: %clang -target armv8r-none-linux-gnu -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V8R %s
+// CHECK-V8R: #define __ARMEL__ 1
+// CHECK-V8R: #define __ARM_ARCH 8
+// CHECK-V8R: #define __ARM_ARCH_8R__ 1
+// CHECK-V8R: #define __ARM_FEATURE_CRC32 1
+// CHECK-V8R: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
+// CHECK-V8R: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
+// CHECK-V8R: #define __ARM_FP 0xE
+
// RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V7 %s
// CHECK-V7: #define __ARMEL__ 1
// CHECK-V7: #define __ARM_ARCH 7
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -146,6 +146,27 @@
// RUN: %clang -target arm -mlittle-endian -march=armv8-a -mlittle-endian -###
-c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
// CHECK-V8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "cortex-a53"
+// RUN: %clang -target armv8r-linux-gnueabi -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// RUN: %clang -target arm -march=armv8r -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// RUN: %clang -target arm -march=armv8-r -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// CHECK-V8R: "-cc1"{{.*}} "-triple" "armv8r-{{.*}} "-target-cpu" "cortex-r52"
+
+// RUN: %clang -target armv8r-linux-gnueabi -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// RUN: %clang -target arm -march=armv8r -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// RUN: %clang -target arm -march=armv8-r -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// CHECK-V8R-BIG: "-cc1"{{.*}} "-triple" "armebv8r-{{.*}} "-target-cpu"
"cortex-r52"
+
+// RUN: %clang -target armv8r-linux-gnueabi -mthumb -### -c %s 2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB %s
+// RUN: %clang -target arm -march=armv8r -mthumb -### -c %s 2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB %s
+// CHECK-V8R-THUMB: "-cc1"{{.*}} "-triple" "thumbv8r-{{.*}} "-target-cpu"
"cortex-r52"
+// RUN: %clang -target armv8r-linux-gnueabi -mthumb -mbig-endian -### -c %s
2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
+// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1
| \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target armv8a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
@@ -502,6 +523,9 @@
// RUN: %clang -target arm -mcpu=exynos-m2 -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// CHECK-BE-CPUV8A: "-cc1"{{.*}} "-triple" "armebv8-{{.*}}
+// RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-r52 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8R %s
+// CHECK-CPUV8R: "-cc1"{{.*}} "-triple" "armv8r-{{.*}}
+
// RUN: %clang -target arm -mcpu=cortex-a32 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a35 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a53 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -4929,6 +4929,8 @@
return "8M_BASE";
case llvm::ARM::AK_ARMV8MMainline:
return "8M_MAIN";
+case llvm::ARM::AK_ARMV8R:
+ return "8R";
}
}
Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -9,6 +9,15 @@
// CHECK-V8A: #define __ARM_FP16_ARGS 1
// CHECK-V8A: #define __ARM_FP16_FORMAT_IEEE 1
+// RUN: %clang -target
[PATCH] D25210: [ARM] Add Cortex-R52 target to CLANG
javed.absar created this revision.
javed.absar added reviewers: rengolin, jmolloy, t.p.northover.
javed.absar added a subscriber: cfe-commits.
Herald added subscribers: samparker, aemerson.
The following patch adds Cortex-R52, the new ARM real-time processor, to CLANG.
Cortex-R52 implements the ARMv8-R architecture. I am submitting another
corresponding patch for LLVM related changes.
https://reviews.llvm.org/D25210
Files:
lib/Basic/Targets.cpp
test/Driver/arm-cortex-cpus.c
test/Preprocessor/arm-target-features.c
Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -9,6 +9,15 @@
// CHECK-V8A: #define __ARM_FP16_ARGS 1
// CHECK-V8A: #define __ARM_FP16_FORMAT_IEEE 1
+// RUN: %clang -target armv8r-none-linux-gnu -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V8R %s
+// CHECK-V8R: #define __ARMEL__ 1
+// CHECK-V8R: #define __ARM_ARCH 8
+// CHECK-V8R: #define __ARM_ARCH_8R__ 1
+// CHECK-V8R: #define __ARM_FEATURE_CRC32 1
+// CHECK-V8R: #define __ARM_FEATURE_DIRECTED_ROUNDING 1
+// CHECK-V8R: #define __ARM_FEATURE_NUMERIC_MAXMIN 1
+// CHECK-V8R: #define __ARM_FP 0xE
+
// RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V7 %s
// CHECK-V7: #define __ARMEL__ 1
// CHECK-V7: #define __ARM_ARCH 7
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -146,6 +146,27 @@
// RUN: %clang -target arm -mlittle-endian -march=armv8-a -mlittle-endian -###
-c %s 2>&1 | FileCheck -check-prefix=CHECK-V8A %s
// CHECK-V8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}" "-target-cpu" "cortex-a53"
+// RUN: %clang -target armv8r-linux-gnueabi -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// RUN: %clang -target arm -march=armv8r -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// RUN: %clang -target arm -march=armv8-r -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8R %s
+// CHECK-V8R: "-cc1"{{.*}} "-triple" "armv8r-{{.*}} "-target-cpu" "generic"
+
+// RUN: %clang -target armv8r-linux-gnueabi -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// RUN: %clang -target arm -march=armv8r -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// RUN: %clang -target arm -march=armv8-r -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8R-BIG %s
+// CHECK-V8R-BIG: "-cc1"{{.*}} "-triple" "armebv8r-{{.*}} "-target-cpu"
"generic"
+
+// RUN: %clang -target armv8r-linux-gnueabi -mthumb -### -c %s 2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB %s
+// RUN: %clang -target arm -march=armv8r -mthumb -### -c %s 2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB %s
+// CHECK-V8R-THUMB: "-cc1"{{.*}} "-triple" "thumbv8r-{{.*}} "-target-cpu"
"generic"
+// RUN: %clang -target armv8r-linux-gnueabi -mthumb -mbig-endian -### -c %s
2>&1 | \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
+// RUN: %clang -target arm -march=armv8r -mthumb -mbig-endian -### -c %s 2>&1
| \
+// RUN: FileCheck -check-prefix=CHECK-V8R-THUMB-BIG %s
+// CHECK-V8R-THUMB-BIG: "-cc1"{{.*}} "-triple" "thumbebv8r-{{.*}} "-target-cpu
+
// RUN: %clang -mcpu=generic -target armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target arm -march=armv8 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-GENERIC %s
// RUN: %clang -mcpu=generic -target armv8a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V8A-GENERIC %s
@@ -502,6 +523,9 @@
// RUN: %clang -target arm -mcpu=exynos-m2 -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
// CHECK-BE-CPUV8A: "-cc1"{{.*}} "-triple" "armebv8-{{.*}}
+// RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-r52 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8R %s
+// CHECK-CPUV8R: "-cc1"{{.*}} "-triple" "armv8r-{{.*}}
+
// RUN: %clang -target arm -mcpu=cortex-a32 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a35 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
// RUN: %clang -target arm -mcpu=cortex-a53 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -4865,6 +4865,8 @@
return "8M_BASE";
case llvm::ARM::AK_ARMV8MMainline:
return "8M_MAIN";
+case llvm::ARM::AK_ARMV8R:
+ return "8R";
}
}
Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++
