[PATCH] D49143: Fix a typo/regression in r335495.
bsdjhb updated this revision to Diff 154840.
bsdjhb added a comment.
Add tests.
Repository:
rC Clang
https://reviews.llvm.org/D49143
Files:
lib/Driver/ToolChains/FreeBSD.cpp
test/Driver/fsanitize.c
Index: test/Driver/fsanitize.c
===
--- test/Driver/fsanitize.c
+++ test/Driver/fsanitize.c
@@ -316,6 +316,12 @@
// RUN: %clang -target mips-unknown-linux -fsanitize=leak %s -### 2>&1 |
FileCheck %s --check-prefix=CHECK-SANL-MIPS
// CHECK-SANL-MIPS: unsupported option '-fsanitize=leak' for target
'mips-unknown-linux'
+// RUN: %clang -target mips-unknown-freebsd -fsanitize=leak %s -### 2>&1 |
FileCheck %s --check-prefix=CHECK-SANL-MIPS-FREEBSD
+// CHECK-SANL-MIPS-FREEBSD: unsupported option '-fsanitize=leak' for target
'mips-unknown-freebsd'
+
+// RUN: %clang -target mips64-unknown-freebsd -fsanitize=leak %s -### 2>&1 |
FileCheck %s --check-prefix=CHECK-SANL-MIPS64-FREEBSD
+// CHECK-SANL-MIPS64-FREEBSD: "-fsanitize=leak"
+
// RUN: %clang -target powerpc64-unknown-linux -fsanitize=leak %s -### 2>&1 |
FileCheck %s --check-prefix=CHECK-SANL-PPC64
// RUN: %clang -target powerpc64le-unknown-linux -fsanitize=leak %s -### 2>&1
| FileCheck %s --check-prefix=CHECK-SANL-PPC64
// CHECK-SANL-PPC64: "-fsanitize=leak"
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -408,7 +408,7 @@
SanitizerMask FreeBSD::getSupportedSanitizers() const {
const bool IsX86 = getTriple().getArch() == llvm::Triple::x86;
const bool IsX86_64 = getTriple().getArch() == llvm::Triple::x86_64;
- const bool IsMIPS64 = getTriple().isMIPS32();
+ const bool IsMIPS64 = getTriple().isMIPS64();
SanitizerMask Res = ToolChain::getSupportedSanitizers();
Res |= SanitizerKind::Address;
Res |= SanitizerKind::Vptr;
Index: test/Driver/fsanitize.c
===
--- test/Driver/fsanitize.c
+++ test/Driver/fsanitize.c
@@ -316,6 +316,12 @@
// RUN: %clang -target mips-unknown-linux -fsanitize=leak %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-SANL-MIPS
// CHECK-SANL-MIPS: unsupported option '-fsanitize=leak' for target 'mips-unknown-linux'
+// RUN: %clang -target mips-unknown-freebsd -fsanitize=leak %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-SANL-MIPS-FREEBSD
+// CHECK-SANL-MIPS-FREEBSD: unsupported option '-fsanitize=leak' for target 'mips-unknown-freebsd'
+
+// RUN: %clang -target mips64-unknown-freebsd -fsanitize=leak %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-SANL-MIPS64-FREEBSD
+// CHECK-SANL-MIPS64-FREEBSD: "-fsanitize=leak"
+
// RUN: %clang -target powerpc64-unknown-linux -fsanitize=leak %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-SANL-PPC64
// RUN: %clang -target powerpc64le-unknown-linux -fsanitize=leak %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-SANL-PPC64
// CHECK-SANL-PPC64: "-fsanitize=leak"
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -408,7 +408,7 @@
SanitizerMask FreeBSD::getSupportedSanitizers() const {
const bool IsX86 = getTriple().getArch() == llvm::Triple::x86;
const bool IsX86_64 = getTriple().getArch() == llvm::Triple::x86_64;
- const bool IsMIPS64 = getTriple().isMIPS32();
+ const bool IsMIPS64 = getTriple().isMIPS64();
SanitizerMask Res = ToolChain::getSupportedSanitizers();
Res |= SanitizerKind::Address;
Res |= SanitizerKind::Vptr;
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[PATCH] D49143: Fix a typo/regression in r335495.
bsdjhb added a comment. AFAICT, I don't see a way to ask clang "which sanitizers are supported by this target". Hmm, the CHECK-SANL-MIPS test in tests/Driver/fsanitize.c seems like the closest match. Repository: rC Clang https://reviews.llvm.org/D49143 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D49143: Fix a typo/regression in r335495.
bsdjhb created this revision.
bsdjhb added a reviewer: arichardson.
Herald added subscribers: atanasyan, krytarowski, sdardis, emaste.
Use getTriple.isMIPS64() to detect 64-bit MIPS ABIs in
FreeBSD::getSupportedSanitizers() instead of getTriple.isMIPS32().
Repository:
rC Clang
https://reviews.llvm.org/D49143
Files:
lib/Driver/ToolChains/FreeBSD.cpp
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -408,7 +408,7 @@
SanitizerMask FreeBSD::getSupportedSanitizers() const {
const bool IsX86 = getTriple().getArch() == llvm::Triple::x86;
const bool IsX86_64 = getTriple().getArch() == llvm::Triple::x86_64;
- const bool IsMIPS64 = getTriple().isMIPS32();
+ const bool IsMIPS64 = getTriple().isMIPS64();
SanitizerMask Res = ToolChain::getSupportedSanitizers();
Res |= SanitizerKind::Address;
Res |= SanitizerKind::Vptr;
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -408,7 +408,7 @@
SanitizerMask FreeBSD::getSupportedSanitizers() const {
const bool IsX86 = getTriple().getArch() == llvm::Triple::x86;
const bool IsX86_64 = getTriple().getArch() == llvm::Triple::x86_64;
- const bool IsMIPS64 = getTriple().isMIPS32();
+ const bool IsMIPS64 = getTriple().isMIPS64();
SanitizerMask Res = ToolChain::getSupportedSanitizers();
Res |= SanitizerKind::Address;
Res |= SanitizerKind::Vptr;
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[PATCH] D47814: Teach libc++ to use native NetBSD's max_align_t
bsdjhb added a comment. FWIW, for FreeBSD I defined __CLANG_MAX_ALIGN_T and _GCC_MAX_ALIGN_T in FreeBSD's when defining the typedef to handle this. Repository: rL LLVM https://reviews.llvm.org/D47814 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D24867: Request init/fini array on FreeBSD 12 and later
bsdjhb added a comment. Ping. I'd like this to go in and get merged into FreeBSD's clang so we can test this for a few months before 12.0 branches. https://reviews.llvm.org/D24867 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D48507: [mips] Explicitly specify the linker emulation for MIPS on FreeBSD.
bsdjhb updated this revision to Diff 152955.
bsdjhb added a comment.
- Add N32EL.
Repository:
rC Clang
https://reviews.llvm.org/D48507
Files:
lib/Driver/ToolChains/FreeBSD.cpp
test/Driver/freebsd.c
Index: test/Driver/freebsd.c
===
--- test/Driver/freebsd.c
+++ test/Driver/freebsd.c
@@ -42,6 +42,27 @@
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -print-search-dirs 2>&1
\
// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
//
+// Check that MIPS passes the correct linker emulation.
+//
+// RUN: %clang -target mips-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS-LD %s
+// CHECK-MIPS-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmip_fbsd"
+// RUN: %clang -target mipsel-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSEL-LD %s
+// CHECK-MIPSEL-LD: ld{{.*}}" {{.*}} "-m" "elf32ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64-LD %s
+// CHECK-MIPS64-LD: ld{{.*}}" {{.*}} "-m" "elf64btsmip_fbsd"
+// RUN: %clang -target mips64el-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64EL-LD %s
+// CHECK-MIPS64EL-LD: ld{{.*}}" {{.*}} "-m" "elf64ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd -mabi=n32 %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSN32-LD %s
+// CHECK-MIPSN32-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmipn32_fbsd"
+// RUN: %clang -target mips64el-freebsd -mabi=n32 %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSN32EL-LD %s
+// CHECK-MIPSN32EL-LD: ld{{.*}}" {{.*}} "-m" "elf32ltsmipn32_fbsd"
+//
// Check that the new linker flags are passed to FreeBSD
// RUN: %clang -no-canonical-prefixes -target x86_64-pc-freebsd8 -m32 %s \
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -### 2>&1 \
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -166,16 +166,39 @@
CmdArgs.push_back("--enable-new-dtags");
}
- // When building 32-bit code on FreeBSD/amd64, we have to explicitly
- // instruct ld in the base system to link 32-bit code.
- if (Arch == llvm::Triple::x86) {
+ // Explicitly set the linker emulation for platforms that might not
+ // be the default emulation for the linker.
+ switch (Arch) {
+ case llvm::Triple::x86:
CmdArgs.push_back("-m");
CmdArgs.push_back("elf_i386_fbsd");
- }
-
- if (Arch == llvm::Triple::ppc) {
+break;
+ case llvm::Triple::ppc:
CmdArgs.push_back("-m");
CmdArgs.push_back("elf32ppc_fbsd");
+break;
+ case llvm::Triple::mips:
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf32btsmip_fbsd");
+break;
+ case llvm::Triple::mipsel:
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf32ltsmip_fbsd");
+break;
+ case llvm::Triple::mips64:
+CmdArgs.push_back("-m");
+if (tools::mips::hasMipsAbiArg(Args, "n32"))
+ CmdArgs.push_back("elf32btsmipn32_fbsd");
+else
+ CmdArgs.push_back("elf64btsmip_fbsd");
+break;
+ case llvm::Triple::mips64el:
+CmdArgs.push_back("-m");
+if (tools::mips::hasMipsAbiArg(Args, "n32"))
+ CmdArgs.push_back("elf32ltsmipn32_fbsd");
+else
+ CmdArgs.push_back("elf64ltsmip_fbsd");
+break;
}
if (Arg *A = Args.getLastArg(options::OPT_G)) {
Index: test/Driver/freebsd.c
===
--- test/Driver/freebsd.c
+++ test/Driver/freebsd.c
@@ -42,6 +42,27 @@
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -print-search-dirs 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
//
+// Check that MIPS passes the correct linker emulation.
+//
+// RUN: %clang -target mips-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS-LD %s
+// CHECK-MIPS-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmip_fbsd"
+// RUN: %clang -target mipsel-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSEL-LD %s
+// CHECK-MIPSEL-LD: ld{{.*}}" {{.*}} "-m" "elf32ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64-LD %s
+// CHECK-MIPS64-LD: ld{{.*}}" {{.*}} "-m" "elf64btsmip_fbsd"
+// RUN: %clang -target mips64el-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64EL-LD %s
+// CHECK-MIPS64EL-LD: ld{{.*}}" {{.*}} "-m" "elf64ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd -mabi=n32 %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSN32-LD %s
+// CHECK-MIPSN32-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmipn32_fbsd"
+// RUN: %clang -target mips64el-freebsd -mabi=n32 %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSN32EL-LD %s
+// CHECK-MIPSN32EL-LD: ld{{.*}}" {{.*}} "-m" "elf32ltsmipn32_fbsd"
+//
// Check that the new linker flags are passed to FreeBSD
// RUN: %clang
[PATCH] D48507: [mips] Explicitly specify the linker emulation for MIPS on FreeBSD.
bsdjhb added inline comments.
Comment at: lib/Driver/ToolChains/FreeBSD.cpp:197
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf64ltsmip_fbsd");
+break;
atanasyan wrote:
> Does it make a sense to handle N32 ABI case here?
For whatever reason, FreeBSD only supports N32 on big-endian. However,
binutils does ship elf32ltsmipsn32_fbsd linker scripts after all, so I could
handle little-endian N32 here.
Repository:
rC Clang
https://reviews.llvm.org/D48507
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[PATCH] D48507: [mips] Explicitly specify the linker emulation for MIPS on FreeBSD.
bsdjhb created this revision.
bsdjhb added a reviewer: dim.
Herald added subscribers: atanasyan, krytarowski, arichardson, sdardis.
FreeBSD's mips64 builds O32 binaries for /usr/lib32 by default and
thus needs to be able to link O32 binaries which requires an explicit
linker emulation. Go ahead and list all the linker emulation variants
for MIPS so that any supported MIPS ABI binary can be linked by any
linker support MIPS.
Repository:
rC Clang
https://reviews.llvm.org/D48507
Files:
lib/Driver/ToolChains/FreeBSD.cpp
test/Driver/freebsd.c
Index: test/Driver/freebsd.c
===
--- test/Driver/freebsd.c
+++ test/Driver/freebsd.c
@@ -42,6 +42,24 @@
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -print-search-dirs 2>&1
\
// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
//
+// Check that MIPS passes the correct linker emulation.
+//
+// RUN: %clang -target mips-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS-LD %s
+// CHECK-MIPS-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmip_fbsd"
+// RUN: %clang -target mipsel-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSEL-LD %s
+// CHECK-MIPSEL-LD: ld{{.*}}" {{.*}} "-m" "elf32ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64-LD %s
+// CHECK-MIPS64-LD: ld{{.*}}" {{.*}} "-m" "elf64btsmip_fbsd"
+// RUN: %clang -target mips64el-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64EL-LD %s
+// CHECK-MIPS64EL-LD: ld{{.*}}" {{.*}} "-m" "elf64ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd -mabi=n32 %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSN32-LD %s
+// CHECK-MIPSN32-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmipn32_fbsd"
+//
// Check that the new linker flags are passed to FreeBSD
// RUN: %clang -no-canonical-prefixes -target x86_64-pc-freebsd8 -m32 %s \
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -### 2>&1 \
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -166,16 +166,36 @@
CmdArgs.push_back("--enable-new-dtags");
}
- // When building 32-bit code on FreeBSD/amd64, we have to explicitly
- // instruct ld in the base system to link 32-bit code.
- if (Arch == llvm::Triple::x86) {
+ // Explicitly set the linker emulation for platforms that might not
+ // be the default emulation for the linker.
+ switch (Arch) {
+ case llvm::Triple::x86:
CmdArgs.push_back("-m");
CmdArgs.push_back("elf_i386_fbsd");
- }
-
- if (Arch == llvm::Triple::ppc) {
+break;
+ case llvm::Triple::ppc:
CmdArgs.push_back("-m");
CmdArgs.push_back("elf32ppc_fbsd");
+break;
+ case llvm::Triple::mips:
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf32btsmip_fbsd");
+break;
+ case llvm::Triple::mipsel:
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf32ltsmip_fbsd");
+break;
+ case llvm::Triple::mips64:
+CmdArgs.push_back("-m");
+if (tools::mips::hasMipsAbiArg(Args, "n32"))
+ CmdArgs.push_back("elf32btsmipn32_fbsd");
+else
+ CmdArgs.push_back("elf64btsmip_fbsd");
+break;
+ case llvm::Triple::mips64el:
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf64ltsmip_fbsd");
+break;
}
if (Arg *A = Args.getLastArg(options::OPT_G)) {
Index: test/Driver/freebsd.c
===
--- test/Driver/freebsd.c
+++ test/Driver/freebsd.c
@@ -42,6 +42,24 @@
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -print-search-dirs 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
//
+// Check that MIPS passes the correct linker emulation.
+//
+// RUN: %clang -target mips-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS-LD %s
+// CHECK-MIPS-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmip_fbsd"
+// RUN: %clang -target mipsel-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSEL-LD %s
+// CHECK-MIPSEL-LD: ld{{.*}}" {{.*}} "-m" "elf32ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64-LD %s
+// CHECK-MIPS64-LD: ld{{.*}}" {{.*}} "-m" "elf64btsmip_fbsd"
+// RUN: %clang -target mips64el-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPS64EL-LD %s
+// CHECK-MIPS64EL-LD: ld{{.*}}" {{.*}} "-m" "elf64ltsmip_fbsd"
+// RUN: %clang -target mips64-freebsd -mabi=n32 %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MIPSN32-LD %s
+// CHECK-MIPSN32-LD: ld{{.*}}" {{.*}} "-m" "elf32btsmipn32_fbsd"
+//
// Check that the new linker flags are passed to FreeBSD
// RUN: %clang -no-canonical-prefixes -target x86_64-pc-freebsd8 -m32 %s \
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -### 2>&1 \
Index:
[PATCH] D48499: [mips] Use more conservative default CPUs for MIPS on FreeBSD.
bsdjhb created this revision.
bsdjhb added a reviewer: dim.
Herald added subscribers: atanasyan, krytarowski, arichardson.
FreeBSD defaults to mips3 for all MIPS ABIs with GCC as that is the
minimum MIPS architecture FreeBSD supports. Use mips3 for MIPS64 and
mips2 for MIPS32 to match.
Repository:
rC Clang
https://reviews.llvm.org/D48499
Files:
lib/Driver/ToolChains/Arch/Mips.cpp
test/Driver/freebsd-mips-as.c
test/Driver/freebsd.c
Index: test/Driver/freebsd.c
===
--- test/Driver/freebsd.c
+++ test/Driver/freebsd.c
@@ -148,3 +148,17 @@
// RUN: %clang -target mips-unknown-freebsd %s -### -G0 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-MIPS-G %s
// CHECK-MIPS-G: ld{{.*}}" "-G0"
+
+// Check CPU type for MIPS
+// RUN: %clang -target mips-unknown-freebsd -### -c %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-MIPS-CPU %s
+// RUN: %clang -target mipsel-unknown-freebsd -### -c %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-MIPS-CPU %s
+// CHECK-MIPS-CPU: "-target-cpu" "mips2"
+
+// Check CPU type for MIPS64
+// RUN: %clang -target mips64-unknown-freebsd -### -c %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-MIPS64-CPU %s
+// RUN: %clang -target mips64el-unknown-freebsd -### -c %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-MIPS64-CPU %s
+// CHECK-MIPS64-CPU: "-target-cpu" "mips3"
Index: test/Driver/freebsd-mips-as.c
===
--- test/Driver/freebsd-mips-as.c
+++ test/Driver/freebsd-mips-as.c
@@ -3,62 +3,62 @@
// RUN: %clang -target mips-unknown-freebsd -### \
// RUN: -no-integrated-as -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS32-EB-AS %s
-// MIPS32-EB-AS: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EB"
+// MIPS32-EB-AS: as{{(.exe)?}}" "-march" "mips2" "-mabi" "32" "-EB"
// MIPS32-EB-AS-NOT: "-KPIC"
//
// RUN: %clang -target mips-unknown-freebsd -### \
// RUN: -no-integrated-as -fPIC -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS32-EB-PIC %s
-// MIPS32-EB-PIC: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EB"
+// MIPS32-EB-PIC: as{{(.exe)?}}" "-march" "mips2" "-mabi" "32" "-EB"
// MIPS32-EB-PIC: "-KPIC"
//
// RUN: %clang -target mips-unknown-freebsd -### \
// RUN: -no-integrated-as -fpic -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS32-EB-PIC-SMALL %s
-// MIPS32-EB-PIC-SMALL: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EB"
+// MIPS32-EB-PIC-SMALL: as{{(.exe)?}}" "-march" "mips2" "-mabi" "32" "-EB"
// MIPS32-EB-PIC-SMALL: "-KPIC"
//
// RUN: %clang -target mips-unknown-freebsd -### \
// RUN: -no-integrated-as -fPIE -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS32-EB-PIE %s
-// MIPS32-EB-PIE: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EB"
+// MIPS32-EB-PIE: as{{(.exe)?}}" "-march" "mips2" "-mabi" "32" "-EB"
// MIPS32-EB-PIE: "-KPIC"
//
// RUN: %clang -target mips-unknown-freebsd -### \
// RUN: -no-integrated-as -fpie -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS32-EB-PIE-SMALL %s
-// MIPS32-EB-PIE-SMALL: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EB"
+// MIPS32-EB-PIE-SMALL: as{{(.exe)?}}" "-march" "mips2" "-mabi" "32" "-EB"
// MIPS32-EB-PIE-SMALL: "-KPIC"
//
// RUN: %clang -target mipsel-unknown-freebsd -### \
// RUN: -no-integrated-as -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS32-DEF-EL-AS %s
-// MIPS32-DEF-EL-AS: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EL"
+// MIPS32-DEF-EL-AS: as{{(.exe)?}}" "-march" "mips2" "-mabi" "32" "-EL"
//
// RUN: %clang -target mips64-unknown-freebsd -### \
// RUN: -no-integrated-as -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS64-EB-AS %s
-// MIPS64-EB-AS: as{{(.exe)?}}" "-march" "mips64r2" "-mabi" "64" "-EB"
+// MIPS64-EB-AS: as{{(.exe)?}}" "-march" "mips3" "-mabi" "64" "-EB"
//
// RUN: %clang -target mips64el-unknown-freebsd -### \
// RUN: -no-integrated-as -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS64-DEF-EL-AS %s
-// MIPS64-DEF-EL-AS: as{{(.exe)?}}" "-march" "mips64r2" "-mabi" "64" "-EL"
+// MIPS64-DEF-EL-AS: as{{(.exe)?}}" "-march" "mips3" "-mabi" "64" "-EL"
//
// RUN: %clang -target mips64-unknown-freebsd -mabi=n32 -### \
// RUN: -no-integrated-as -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS-N32 %s
-// MIPS-N32: as{{(.exe)?}}" "-march" "mips64r2" "-mabi" "n32" "-EB"
+// MIPS-N32: as{{(.exe)?}}" "-march" "mips3" "-mabi" "n32" "-EB"
//
// RUN: %clang -target mipsel-unknown-freebsd -mabi=32 -### \
// RUN: -no-integrated-as -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS32-EL-AS %s
-// MIPS32-EL-AS: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EL"
+// MIPS32-EL-AS: as{{(.exe)?}}" "-march" "mips2" "-mabi" "32" "-EL"
//
// RUN: %clang -target mips64el-unknown-freebsd -mabi=64 -### \
// RUN: -no-integrated-as -c %s 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS64-EL-AS %s
-// MIPS64-EL-AS: as{{(.exe)?}}" "-march" "mips64r2"
[PATCH] D44604: Make stdarg.h compatible with FreeBSD
bsdjhb added a comment. FWIW, I ended up fixing FreeBSD to only use in freestanding environments and always use in userland which makes this patch no longer necessary. (Only one place needed to be fixed.) Repository: rC Clang https://reviews.llvm.org/D44604 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb added a comment. Ping @sdardis @compnerd Repository: rUNW libunwind https://reviews.llvm.org/D41968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb added a comment. @sdardis ping. I think the approach I've used for O32 is probably the right one in that it matches what DWARF expects (DWARF doesn't treat the 32-bit floating point registers as pairs but as individual registers). I think the question is if I O32 with 32-bit FP registers should use an array of float[]s instead of an array of double[]s though (which adds an extra #ifdef for context size) vs keeping the current layout. Repository: rUNW libunwind https://reviews.llvm.org/D41968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb marked 2 inline comments as done. bsdjhb added a comment. This version follows the suggestion I made earlier of treating 32-bit floating point registers as a "plain" register for O32 rather than a floating-point register. It seems to work for me though for O32 I've only tested with 32-bit floating point registers. If we stick with this approach for 32-bit floating point it might be simpler and/or more readable to make _floats[] an array of uint32_t for that case and just use different context sizes for the O32 with 32-bit fp vs O32 with 64-bit fp. This version works in my testing on FreeBSD for O32 with 32-bit FPR, N32, and N64. Repository: rUNW libunwind https://reviews.llvm.org/D41968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb updated this revision to Diff 137085. bsdjhb added a comment. - Add a comment about using a single FP layout for O32. - Treat 32-bit floating point registers on O32 as plain registers. Repository: rUNW libunwind https://reviews.llvm.org/D41968 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -61,10 +61,9 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k -#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \ -defined(__mips_soft_float) +#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 # define REGISTER_KIND Registers_mips_o32 -#elif defined(__mips64) && defined(__mips_soft_float) +#elif defined(__mips64) # define REGISTER_KIND Registers_mips_newabi #elif defined(__mips__) # warning The MIPS architecture is not supported with this ABI and environment! Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,8 +116,7 @@ xorl %eax, %eax# return UNW_ESUCCESS ret -#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \ -defined(__mips_soft_float) +#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 # # extern int unw_getcontext(unw_context_t* thread_state) @@ -168,12 +167,65 @@ sw$8, (4 * 33)($4) mflo $8 sw$8, (4 * 34)($4) +#ifdef __mips_hard_float +#if __mips_fpr == 32 + sdc1 $f0, (4 * 36 + 8 * 0)($4) + sdc1 $f2, (4 * 36 + 8 * 2)($4) + sdc1 $f4, (4 * 36 + 8 * 4)($4) + sdc1 $f6, (4 * 36 + 8 * 6)($4) + sdc1 $f8, (4 * 36 + 8 * 8)($4) + sdc1 $f10, (4 * 36 + 8 * 10)($4) + sdc1 $f12, (4 * 36 + 8 * 12)($4) + sdc1 $f14, (4 * 36 + 8 * 14)($4) + sdc1 $f16, (4 * 36 + 8 * 16)($4) + sdc1 $f18, (4 * 36 + 8 * 18)($4) + sdc1 $f20, (4 * 36 + 8 * 20)($4) + sdc1 $f22, (4 * 36 + 8 * 22)($4) + sdc1 $f24, (4 * 36 + 8 * 24)($4) + sdc1 $f26, (4 * 36 + 8 * 26)($4) + sdc1 $f28, (4 * 36 + 8 * 28)($4) + sdc1 $f30, (4 * 36 + 8 * 30)($4) +#else + sdc1 $f0, (4 * 36 + 8 * 0)($4) + sdc1 $f1, (4 * 36 + 8 * 1)($4) + sdc1 $f2, (4 * 36 + 8 * 2)($4) + sdc1 $f3, (4 * 36 + 8 * 3)($4) + sdc1 $f4, (4 * 36 + 8 * 4)($4) + sdc1 $f5, (4 * 36 + 8 * 5)($4) + sdc1 $f6, (4 * 36 + 8 * 6)($4) + sdc1 $f7, (4 * 36 + 8 * 7)($4) + sdc1 $f8, (4 * 36 + 8 * 8)($4) + sdc1 $f9, (4 * 36 + 8 * 9)($4) + sdc1 $f10, (4 * 36 + 8 * 10)($4) + sdc1 $f11, (4 * 36 + 8 * 11)($4) + sdc1 $f12, (4 * 36 + 8 * 12)($4) + sdc1 $f13, (4 * 36 + 8 * 13)($4) + sdc1 $f14, (4 * 36 + 8 * 14)($4) + sdc1 $f15, (4 * 36 + 8 * 15)($4) + sdc1 $f16, (4 * 36 + 8 * 16)($4) + sdc1 $f17, (4 * 36 + 8 * 17)($4) + sdc1 $f18, (4 * 36 + 8 * 18)($4) + sdc1 $f19, (4 * 36 + 8 * 19)($4) + sdc1 $f20, (4 * 36 + 8 * 20)($4) + sdc1 $f21, (4 * 36 + 8 * 21)($4) + sdc1 $f22, (4 * 36 + 8 * 22)($4) + sdc1 $f23, (4 * 36 + 8 * 23)($4) + sdc1 $f24, (4 * 36 + 8 * 24)($4) + sdc1 $f25, (4 * 36 + 8 * 25)($4) + sdc1 $f26, (4 * 36 + 8 * 26)($4) + sdc1 $f27, (4 * 36 + 8 * 27)($4) + sdc1 $f28, (4 * 36 + 8 * 28)($4) + sdc1 $f29, (4 * 36 + 8 * 29)($4) + sdc1 $f30, (4 * 36 + 8 * 30)($4) + sdc1 $f31, (4 * 36 + 8 * 31)($4) +#endif +#endif jr $31 # return UNW_ESUCCESS or$2, $0, $0 .set pop -#elif defined(__mips64) && defined(__mips_soft_float) +#elif defined(__mips64) # # extern int unw_getcontext(unw_context_t* thread_state) @@ -224,6 +276,40 @@ sd$8, (8 * 33)($4) mflo $8 sd$8, (8 * 34)($4) +#ifdef __mips_hard_float + sdc1 $f0, (8 * 35)($4) + sdc1 $f1, (8 * 36)($4) + sdc1 $f2, (8 * 37)($4) + sdc1 $f3, (8 * 38)($4) + sdc1 $f4, (8 * 39)($4) + sdc1 $f5, (8 * 40)($4) + sdc1 $f6, (8 * 41)($4) + sdc1 $f7, (8 * 42)($4) + sdc1 $f8, (8 * 43)($4) + sdc1 $f9, (8 * 44)($4) + sdc1 $f10, (8 * 45)($4) + sdc1 $f11, (8 * 46)($4) + sdc1 $f12, (8 * 47)($4) + sdc1 $f13, (8 * 48)($4) + sdc1 $f14, (8 * 49)($4) + sdc1 $f15, (8 * 50)($4) + sdc1 $f16, (8 * 51)($4) + sdc1 $f17, (8 * 52)($4) + sdc1 $f18, (8 * 53)($4) + sdc1 $f19, (8 * 54)($4) + sdc1 $f20, (8 * 55)($4) + sdc1 $f21, (8 * 56)($4) + sdc1 $f22, (8 * 57)($4) + sdc1 $f23, (8 * 58)($4) + sdc1 $f24, (8 * 59)($4) + sdc1 $f25, (8 * 60)($4) + sdc1 $f26, (8 * 61)($4) + sdc1 $f27, (8 * 62)($4) + sdc1 $f28, (8 * 63)($4) + sdc1 $f29, (8 * 64)($4) + sdc1 $f30, (8 * 65)($4) + sdc1 $f31, (8 * 66)($4) +#endif jr $31 # return UNW_ESUCCESS or$2, $0, $0 Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -799,8 +799,7 @@ l.jr r9
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb updated this revision to Diff 136164. bsdjhb added a comment. Herald added a subscriber: christof. - Rebase after N32 commit. - Use ldc1/sdc1 rather than l.d and s.d. Repository: rUNW libunwind https://reviews.llvm.org/D41968 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -61,10 +61,9 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k -#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \ -defined(__mips_soft_float) +#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 # define REGISTER_KIND Registers_mips_o32 -#elif defined(__mips64) && defined(__mips_soft_float) +#elif defined(__mips64) # define REGISTER_KIND Registers_mips_newabi #elif defined(__mips__) # warning The MIPS architecture is not supported with this ABI and environment! Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,8 +116,7 @@ xorl %eax, %eax# return UNW_ESUCCESS ret -#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \ -defined(__mips_soft_float) +#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 # # extern int unw_getcontext(unw_context_t* thread_state) @@ -168,12 +167,65 @@ sw$8, (4 * 33)($4) mflo $8 sw$8, (4 * 34)($4) +#ifdef __mips_hard_float +#if __mips_fpr == 32 + sdc1 $f0, (4 * 36 + 8 * 0)($4) + sdc1 $f2, (4 * 36 + 8 * 2)($4) + sdc1 $f4, (4 * 36 + 8 * 4)($4) + sdc1 $f6, (4 * 36 + 8 * 6)($4) + sdc1 $f8, (4 * 36 + 8 * 8)($4) + sdc1 $f10, (4 * 36 + 8 * 10)($4) + sdc1 $f12, (4 * 36 + 8 * 12)($4) + sdc1 $f14, (4 * 36 + 8 * 14)($4) + sdc1 $f16, (4 * 36 + 8 * 16)($4) + sdc1 $f18, (4 * 36 + 8 * 18)($4) + sdc1 $f20, (4 * 36 + 8 * 20)($4) + sdc1 $f22, (4 * 36 + 8 * 22)($4) + sdc1 $f24, (4 * 36 + 8 * 24)($4) + sdc1 $f26, (4 * 36 + 8 * 26)($4) + sdc1 $f28, (4 * 36 + 8 * 28)($4) + sdc1 $f30, (4 * 36 + 8 * 30)($4) +#else + sdc1 $f0, (4 * 36 + 8 * 0)($4) + sdc1 $f1, (4 * 36 + 8 * 1)($4) + sdc1 $f2, (4 * 36 + 8 * 2)($4) + sdc1 $f3, (4 * 36 + 8 * 3)($4) + sdc1 $f4, (4 * 36 + 8 * 4)($4) + sdc1 $f5, (4 * 36 + 8 * 5)($4) + sdc1 $f6, (4 * 36 + 8 * 6)($4) + sdc1 $f7, (4 * 36 + 8 * 7)($4) + sdc1 $f8, (4 * 36 + 8 * 8)($4) + sdc1 $f9, (4 * 36 + 8 * 9)($4) + sdc1 $f10, (4 * 36 + 8 * 10)($4) + sdc1 $f11, (4 * 36 + 8 * 11)($4) + sdc1 $f12, (4 * 36 + 8 * 12)($4) + sdc1 $f13, (4 * 36 + 8 * 13)($4) + sdc1 $f14, (4 * 36 + 8 * 14)($4) + sdc1 $f15, (4 * 36 + 8 * 15)($4) + sdc1 $f16, (4 * 36 + 8 * 16)($4) + sdc1 $f17, (4 * 36 + 8 * 17)($4) + sdc1 $f18, (4 * 36 + 8 * 18)($4) + sdc1 $f19, (4 * 36 + 8 * 19)($4) + sdc1 $f20, (4 * 36 + 8 * 20)($4) + sdc1 $f21, (4 * 36 + 8 * 21)($4) + sdc1 $f22, (4 * 36 + 8 * 22)($4) + sdc1 $f23, (4 * 36 + 8 * 23)($4) + sdc1 $f24, (4 * 36 + 8 * 24)($4) + sdc1 $f25, (4 * 36 + 8 * 25)($4) + sdc1 $f26, (4 * 36 + 8 * 26)($4) + sdc1 $f27, (4 * 36 + 8 * 27)($4) + sdc1 $f28, (4 * 36 + 8 * 28)($4) + sdc1 $f29, (4 * 36 + 8 * 29)($4) + sdc1 $f30, (4 * 36 + 8 * 30)($4) + sdc1 $f31, (4 * 36 + 8 * 31)($4) +#endif +#endif jr $31 # return UNW_ESUCCESS or$2, $0, $0 .set pop -#elif defined(__mips64) && defined(__mips_soft_float) +#elif defined(__mips64) # # extern int unw_getcontext(unw_context_t* thread_state) @@ -224,6 +276,40 @@ sd$8, (8 * 33)($4) mflo $8 sd$8, (8 * 34)($4) +#ifdef __mips_hard_float + sdc1 $f0, (8 * 35)($4) + sdc1 $f1, (8 * 36)($4) + sdc1 $f2, (8 * 37)($4) + sdc1 $f3, (8 * 38)($4) + sdc1 $f4, (8 * 39)($4) + sdc1 $f5, (8 * 40)($4) + sdc1 $f6, (8 * 41)($4) + sdc1 $f7, (8 * 42)($4) + sdc1 $f8, (8 * 43)($4) + sdc1 $f9, (8 * 44)($4) + sdc1 $f10, (8 * 45)($4) + sdc1 $f11, (8 * 46)($4) + sdc1 $f12, (8 * 47)($4) + sdc1 $f13, (8 * 48)($4) + sdc1 $f14, (8 * 49)($4) + sdc1 $f15, (8 * 50)($4) + sdc1 $f16, (8 * 51)($4) + sdc1 $f17, (8 * 52)($4) + sdc1 $f18, (8 * 53)($4) + sdc1 $f19, (8 * 54)($4) + sdc1 $f20, (8 * 55)($4) + sdc1 $f21, (8 * 56)($4) + sdc1 $f22, (8 * 57)($4) + sdc1 $f23, (8 * 58)($4) + sdc1 $f24, (8 * 59)($4) + sdc1 $f25, (8 * 60)($4) + sdc1 $f26, (8 * 61)($4) + sdc1 $f27, (8 * 62)($4) + sdc1 $f28, (8 * 63)($4) + sdc1 $f29, (8 * 64)($4) + sdc1 $f30, (8 * 65)($4) + sdc1 $f31, (8 * 66)($4) +#endif jr $31 # return UNW_ESUCCESS or$2, $0, $0 Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -799,8 +799,7 @@ l.jr r9 l.nop
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb added a comment. Hmmm, so I was somewhat mistaken as DwarfInstructions.hpp::stepWithDwarf() does use the Register class's setFloatRegister(), however, it assumes that the floating point register is always a double (DwarfInstructions.hpp::getSavedFloatRegister() uses AddressSpace::getDouble() to read a double from memory). So I think that means that the NEWABI cases work as-is. O32 with 64-bit FP registers should also work as-is. However, O32 with 32-bit FP registers will not quite work. The DWARF info for O32 with 32-bit registers does save/restore individual 32-bit registers: 06dc 0034 06e0 FDE cie= pc=d384..d46c DW_CFA_advance_loc4: 16 to d394 DW_CFA_def_cfa_offset: 56 DW_CFA_advance_loc4: 20 to d3a8 DW_CFA_offset: r31 at cfa-12 DW_CFA_offset: r17 at cfa-16 DW_CFA_offset: r16 at cfa-20 DW_CFA_offset: r52 at cfa-4 DW_CFA_offset: r53 at cfa-8 ... If the compiler happens to always save and restore them in pairs then the current approach will work. If we don't want to assume that they are saved and restored in pairs, then we could instead perhaps claim that 32-bit FP registers aren't really floating point but are just plain 32-bit registers. This would make unwinding work (I believe), but would mean that one would need to use unw_get_reg() instead of unw_get_fpreg() to fetch individual 32-bit FP registers. https://reviews.llvm.org/D41968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb added a comment. After thinking about this some more, I need to rework this a bit. The choice of how to expose the floating point registers via getFloatingPointRegister / setFloatingPointRegister only affects consumers of the libunwind unw_get_fpreg/unw_set_fpreg. I think a bigger factor is that we need to honor unwind rules in frames that describe the saved location of FP registers on the stack (which this patchset doesn't do). I think that's fairly trivial for the case where an FP register is the same size as a GP register, and it probably argues for storing 32-bit FP registers as individual 'float' if that is how the unwind information is encoded. I haven't yet looked to see what the implications would be for O32 MIPS with 64-bit FP registers. It may be that I punt on that configuration for now. https://reviews.llvm.org/D41968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43585: [libunwind] Permit additional compiler flags to be passed to tests.
bsdjhb updated this revision to Diff 136098. bsdjhb added a comment. - Match names used in libcxx and add LINKER_FLAGS. Repository: rUNW libunwind https://reviews.llvm.org/D43585 Files: CMakeLists.txt test/lit.site.cfg.in Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -12,6 +12,8 @@ config.use_sanitizer= "@LLVM_USE_SANITIZER@" config.enable_32bit = "@LIBUNWIND_BUILD_32_BITS@" config.target_info = "@LIBUNWIND_TARGET_INFO@" +config.test_linker_flags= "@LIBUNWIND_TEST_LINKER_FLAGS@" +config.test_compiler_flags = "@LIBUNWIND_TEST_COMPILER_FLAGS@" config.executor = "@LIBUNWIND_EXECUTOR@" config.libunwind_shared = "@LIBUNWIND_ENABLE_SHARED@" config.enable_shared= "@LIBCXX_ENABLE_SHARED@" Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,10 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_LINKER_FLAGS "" CACHE STRING +"Additional linker flags for test programs.") +set(LIBUNWIND_TEST_COMPILER_FLAGS "" CACHE STRING +"Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -12,6 +12,8 @@ config.use_sanitizer= "@LLVM_USE_SANITIZER@" config.enable_32bit = "@LIBUNWIND_BUILD_32_BITS@" config.target_info = "@LIBUNWIND_TARGET_INFO@" +config.test_linker_flags= "@LIBUNWIND_TEST_LINKER_FLAGS@" +config.test_compiler_flags = "@LIBUNWIND_TEST_COMPILER_FLAGS@" config.executor = "@LIBUNWIND_EXECUTOR@" config.libunwind_shared = "@LIBUNWIND_ENABLE_SHARED@" config.enable_shared= "@LIBCXX_ENABLE_SHARED@" Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,10 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_LINKER_FLAGS "" CACHE STRING +"Additional linker flags for test programs.") +set(LIBUNWIND_TEST_COMPILER_FLAGS "" CACHE STRING +"Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43585: [libunwind] Permit additional compiler flags to be passed to tests.
bsdjhb updated this revision to Diff 135714. bsdjhb added a comment. - Use STRING instead of PATH. - Update for committed libcxx change. Repository: rUNW libunwind https://reviews.llvm.org/D43585 Files: CMakeLists.txt test/lit.site.cfg.in Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -22,6 +22,7 @@ config.sysroot = "@LIBUNWIND_SYSROOT@" config.gcc_toolchain= "@LIBUNWIND_GCC_TOOLCHAIN@" config.cxx_ext_threads = "@LIBUNWIND_BUILD_EXTERNAL_THREAD_LIBRARY@" +config.test_compiler_flags = "@LIBUNWIND_TEST_CFLAGS@" # Let the main config do the real work. lit_config.load_config(config, "@LIBUNWIND_SOURCE_DIR@/test/lit.cfg") Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,7 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_CFLAGS "" CACHE STRING "Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -22,6 +22,7 @@ config.sysroot = "@LIBUNWIND_SYSROOT@" config.gcc_toolchain= "@LIBUNWIND_GCC_TOOLCHAIN@" config.cxx_ext_threads = "@LIBUNWIND_BUILD_EXTERNAL_THREAD_LIBRARY@" +config.test_compiler_flags = "@LIBUNWIND_TEST_CFLAGS@" # Let the main config do the real work. lit_config.load_config(config, "@LIBUNWIND_SOURCE_DIR@/test/lit.cfg") Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,7 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_CFLAGS "" CACHE STRING "Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43585: [libunwind] Permit additional compiler flags to be passed to tests.
bsdjhb marked 2 inline comments as done. bsdjhb added a comment. My only question is if this should be named LIBUNWIND_TEST_COMPILER_FLAGS to match the name used in libc++? Repository: rUNW libunwind https://reviews.llvm.org/D43585 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43584: [test] Permit additional CFLAGS for tests to be set via config.test_cflags.
bsdjhb abandoned this revision. bsdjhb added a comment. Obsoleted by https://reviews.llvm.org/rCXX325914. Repository: rCXX libc++ https://reviews.llvm.org/D43584 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43584: [test] Permit additional CFLAGS for tests to be set via config.test_cflags.
bsdjhb created this revision.
bsdjhb added a reviewer: sdardis.
Herald added subscribers: cfe-commits, christof.
Currently this is only planned to be used by libunwind's tests.
Repository:
rCXX libc++
https://reviews.llvm.org/D43584
Files:
utils/libcxx/test/config.py
Index: utils/libcxx/test/config.py
===
--- utils/libcxx/test/config.py
+++ utils/libcxx/test/config.py
@@ -583,6 +583,9 @@
# FIXME(EricWF): variant_size.pass.cpp requires a slightly larger
# template depth with older Clang versions.
self.cxx.addFlagIfSupported('-ftemplate-depth=270')
+cflags = self.get_lit_conf('test_cflags')
+if cflags:
+self.cxx.flags += [cflags]
def configure_compile_flags_header_includes(self):
support_path = os.path.join(self.libcxx_src_root, 'test', 'support')
Index: utils/libcxx/test/config.py
===
--- utils/libcxx/test/config.py
+++ utils/libcxx/test/config.py
@@ -583,6 +583,9 @@
# FIXME(EricWF): variant_size.pass.cpp requires a slightly larger
# template depth with older Clang versions.
self.cxx.addFlagIfSupported('-ftemplate-depth=270')
+cflags = self.get_lit_conf('test_cflags')
+if cflags:
+self.cxx.flags += [cflags]
def configure_compile_flags_header_includes(self):
support_path = os.path.join(self.libcxx_src_root, 'test', 'support')
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[PATCH] D43585: [libunwind] Permit additional compiler flags to be passed to tests.
bsdjhb added a comment. @sdardis requested this functionality in the review of https://reviews.llvm.org/D39074. Simon, can you confirm that this works for you in your testing? Repository: rUNW libunwind https://reviews.llvm.org/D43585 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43585: [libunwind] Permit additional compiler flags to be passed to tests.
bsdjhb updated this revision to Diff 135285. bsdjhb added a comment. - Unexpand tabs. Repository: rUNW libunwind https://reviews.llvm.org/D43585 Files: CMakeLists.txt test/lit.site.cfg.in Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -22,6 +22,7 @@ config.sysroot = "@LIBUNWIND_SYSROOT@" config.gcc_toolchain= "@LIBUNWIND_GCC_TOOLCHAIN@" config.cxx_ext_threads = "@LIBUNWIND_BUILD_EXTERNAL_THREAD_LIBRARY@" +config.test_cflags = "@LIBUNWIND_TEST_CFLAGS@" # Let the main config do the real work. lit_config.load_config(config, "@LIBUNWIND_SOURCE_DIR@/test/lit.cfg") Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,7 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_CFLAGS "" CACHE PATH "Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -22,6 +22,7 @@ config.sysroot = "@LIBUNWIND_SYSROOT@" config.gcc_toolchain= "@LIBUNWIND_GCC_TOOLCHAIN@" config.cxx_ext_threads = "@LIBUNWIND_BUILD_EXTERNAL_THREAD_LIBRARY@" +config.test_cflags = "@LIBUNWIND_TEST_CFLAGS@" # Let the main config do the real work. lit_config.load_config(config, "@LIBUNWIND_SOURCE_DIR@/test/lit.cfg") Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,7 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_CFLAGS "" CACHE PATH "Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D43585: [libunwind] Permit additional compiler flags to be passed to tests.
bsdjhb created this revision. bsdjhb added a reviewer: sdardis. Herald added subscribers: christof, mgorny. This is done via a new LIBUNWIND_TEST_CFLAGS variable. Repository: rUNW libunwind https://reviews.llvm.org/D43585 Files: CMakeLists.txt test/lit.site.cfg.in Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -22,6 +22,7 @@ config.sysroot = "@LIBUNWIND_SYSROOT@" config.gcc_toolchain= "@LIBUNWIND_GCC_TOOLCHAIN@" config.cxx_ext_threads = "@LIBUNWIND_BUILD_EXTERNAL_THREAD_LIBRARY@" +config.test_cflags = "@LIBUNWIND_TEST_CFLAGS@" # Let the main config do the real work. lit_config.load_config(config, "@LIBUNWIND_SOURCE_DIR@/test/lit.cfg") Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,7 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_CFLAGS "" CACHE PATH "Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") Index: test/lit.site.cfg.in === --- test/lit.site.cfg.in +++ test/lit.site.cfg.in @@ -22,6 +22,7 @@ config.sysroot = "@LIBUNWIND_SYSROOT@" config.gcc_toolchain= "@LIBUNWIND_GCC_TOOLCHAIN@" config.cxx_ext_threads = "@LIBUNWIND_BUILD_EXTERNAL_THREAD_LIBRARY@" +config.test_cflags = "@LIBUNWIND_TEST_CFLAGS@" # Let the main config do the real work. lit_config.load_config(config, "@LIBUNWIND_SOURCE_DIR@/test/lit.cfg") Index: CMakeLists.txt === --- CMakeLists.txt +++ CMakeLists.txt @@ -139,6 +139,7 @@ set(LIBUNWIND_TARGET_TRIPLE "" CACHE STRING "Target triple for cross compiling.") set(LIBUNWIND_GCC_TOOLCHAIN "" CACHE PATH "GCC toolchain for cross compiling.") set(LIBUNWIND_SYSROOT "" CACHE PATH "Sysroot for cross compiling.") +set(LIBUNWIND_TEST_CFLAGS "" CACHE PATH "Additional compiler flags for test programs.") if (NOT LIBUNWIND_ENABLE_SHARED AND NOT LIBUNWIND_ENABLE_STATIC) message(FATAL_ERROR "libunwind must be built as either a shared or static library.") ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb added a comment. Hmmm, I'm a bit lost on the CFLAGS bit. I couldn't find a reference to LIBOMP_TEST_CFLAGS anywhere in the openmp tree. There is a LIBOMP_CFLAGS that doesn't appear to be test specific. To try to find a way to modify the CFLAGS for tests I looked at how LIBUNWIND_BUILD_32_BITS works. It sets a value (config.enable_32bit) in test/lit.site.cfg.in. This is then used by the utils/libcxx/test/config.py script in the libcxx repository in the configure_default_compile_flags() function to add -m32 to CFLAGS. There isn't an existing config.* knob that can add arbitrary things to CFLAGS though, so I think adding a LIBUNWIND_TEST_CFLAGS would mean changing the config.py to learn about a new 'config.cflags' or the like and then mapping LIBUNWIND_TEST_CFLAGS to that via lit.site.cfg.in? Repository: rUNW libunwind https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb updated this revision to Diff 133660.
bsdjhb added a comment.
- Rebase.
- Rework ABI macro checks.
Repository:
rUNW libunwind
https://reviews.llvm.org/D39074
Files:
include/__libunwind_config.h
src/AddressSpace.hpp
src/DwarfInstructions.hpp
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -61,9 +61,10 @@
# define REGISTER_KIND Registers_arm
#elif defined(__or1k__)
# define REGISTER_KIND Registers_or1k
-#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \
+defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips64) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -116,7 +116,8 @@
xorl %eax, %eax# return UNW_ESUCCESS
ret
-#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \
+defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
@@ -172,7 +173,7 @@
or$2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips64) && defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -799,7 +799,8 @@
l.jr r9
l.nop
-#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
+#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \
+defined(__mips_soft_float)
//
// void libunwind::Registers_mips_o32::jumpto()
@@ -855,7 +856,7 @@
lw$4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips64) && defined(__mips_soft_float)
//
// void libunwind::Registers_mips_newabi::jumpto()
Index: src/DwarfInstructions.hpp
===
--- src/DwarfInstructions.hpp
+++ src/DwarfInstructions.hpp
@@ -82,10 +82,10 @@
const RegisterLocation ) {
switch (savedReg.location) {
case CFI_Parser::kRegisterInCFA:
-return addressSpace.getP(cfa + (pint_t)savedReg.value);
+return addressSpace.getRegister(cfa + (pint_t)savedReg.value);
case CFI_Parser::kRegisterAtExpression:
-return addressSpace.getP(
+return addressSpace.getRegister(
evaluateExpression((pint_t)savedReg.value, addressSpace,
registers, cfa));
Index: src/AddressSpace.hpp
===
--- src/AddressSpace.hpp
+++ src/AddressSpace.hpp
@@ -207,6 +207,7 @@
return val;
}
uintptr_t getP(pint_t addr);
+ uint64_tgetRegister(pint_t addr);
static uint64_t getULEB128(pint_t , pint_t end);
static int64_t getSLEB128(pint_t , pint_t end);
@@ -228,6 +229,14 @@
#endif
}
+inline uint64_t LocalAddressSpace::getRegister(pint_t addr) {
+#if __SIZEOF_POINTER__ == 8 || defined(__mips64)
+ return get64(addr);
+#else
+ return get32(addr);
+#endif
+}
+
/// Read a ULEB128 into a 64-bit word.
inline uint64_t LocalAddressSpace::getULEB128(pint_t , pint_t end) {
const uint8_t *p = (uint8_t *)addr;
@@ -600,6 +609,7 @@
uint32_t get32(pint_t addr);
uint64_t get64(pint_t addr);
pint_tgetP(pint_t addr);
+ uint64_t getRegister(pint_t addr);
uint64_t getULEB128(pint_t , pint_t end);
int64_t getSLEB128(pint_t , pint_t end);
pint_tgetEncodedP(pint_t , pint_t end, uint8_t encoding,
@@ -636,7 +646,12 @@
}
template
-uint64_t RemoteAddressSpace::getULEB128(pint_t , pint_t end) {
+typename P::uint_t OtherAddressSpace::getRegister(pint_t addr) {
+ return P::getRegister(*(uint64_t *)localCopy(addr));
+}
+
+template
+uint64_t OtherAddressSpace::getULEB128(pint_t , pint_t end) {
uintptr_t size = (end - addr);
LocalAddressSpace::pint_t laddr = (LocalAddressSpace::pint_t) localCopy(addr);
LocalAddressSpace::pint_t sladdr = laddr;
Index: include/__libunwind_config.h
===
--- include/__libunwind_config.h
+++ include/__libunwind_config.h
@@ -71,11 +71,15 @@
# define _LIBUNWIND_CURSOR_SIZE 24
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb marked 7 inline comments as done. bsdjhb added a comment. Nice sleuthing! Repository: rUNW libunwind https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D42972: Look for 32-bit libraries in /usr/lib32 for MIPS O32 on FreeBSD.
bsdjhb updated this revision to Diff 10.
bsdjhb added a comment.
- Add a test case.
Repository:
rC Clang
https://reviews.llvm.org/D42972
Files:
lib/Driver/ToolChains/FreeBSD.cpp
test/Driver/freebsd.c
Index: test/Driver/freebsd.c
===
--- test/Driver/freebsd.c
+++ test/Driver/freebsd.c
@@ -36,6 +36,12 @@
// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
// CHECK-LIB32PATHS: libraries: ={{.*:?}}/usr/lib32
//
+// Check that O32 MIPS uses /usr/lib32 on a 64-bit tree.
+//
+// RUN: %clang -target mips-freebsd12 %s \
+// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -print-search-dirs 2>&1
\
+// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
+//
// Check that the new linker flags are passed to FreeBSD
// RUN: %clang -no-canonical-prefixes -target x86_64-pc-freebsd8 -m32 %s \
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -### 2>&1 \
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -317,6 +317,8 @@
// When targeting 32-bit platforms, look for '/usr/lib32/crt1.o' and fall
// back to '/usr/lib' if it doesn't exist.
if ((Triple.getArch() == llvm::Triple::x86 ||
+ Triple.getArch() == llvm::Triple::mips ||
+ Triple.getArch() == llvm::Triple::mipsel ||
Triple.getArch() == llvm::Triple::ppc) &&
D.getVFS().exists(getDriver().SysRoot + "/usr/lib32/crt1.o"))
getFilePaths().push_back(getDriver().SysRoot + "/usr/lib32");
Index: test/Driver/freebsd.c
===
--- test/Driver/freebsd.c
+++ test/Driver/freebsd.c
@@ -36,6 +36,12 @@
// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
// CHECK-LIB32PATHS: libraries: ={{.*:?}}/usr/lib32
//
+// Check that O32 MIPS uses /usr/lib32 on a 64-bit tree.
+//
+// RUN: %clang -target mips-freebsd12 %s \
+// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -print-search-dirs 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-LIB32PATHS %s
+//
// Check that the new linker flags are passed to FreeBSD
// RUN: %clang -no-canonical-prefixes -target x86_64-pc-freebsd8 -m32 %s \
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -### 2>&1 \
Index: lib/Driver/ToolChains/FreeBSD.cpp
===
--- lib/Driver/ToolChains/FreeBSD.cpp
+++ lib/Driver/ToolChains/FreeBSD.cpp
@@ -317,6 +317,8 @@
// When targeting 32-bit platforms, look for '/usr/lib32/crt1.o' and fall
// back to '/usr/lib' if it doesn't exist.
if ((Triple.getArch() == llvm::Triple::x86 ||
+ Triple.getArch() == llvm::Triple::mips ||
+ Triple.getArch() == llvm::Triple::mipsel ||
Triple.getArch() == llvm::Triple::ppc) &&
D.getVFS().exists(getDriver().SysRoot + "/usr/lib32/crt1.o"))
getFilePaths().push_back(getDriver().SysRoot + "/usr/lib32");
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[PATCH] D42972: Look for 32-bit libraries in /usr/lib32 for MIPS O32 on FreeBSD.
bsdjhb created this revision. Herald added subscribers: krytarowski, arichardson, sdardis, emaste. FreeBSD N64 MIPS systems can include 32-bit libraries for O32 in /usr/lib32 similar to the 32-bit compatibility libraries provided for FreeBSD/amd64 and FreeBSD/powerpc64. Repository: rC Clang https://reviews.llvm.org/D42972 Files: lib/Driver/ToolChains/FreeBSD.cpp Index: lib/Driver/ToolChains/FreeBSD.cpp === --- lib/Driver/ToolChains/FreeBSD.cpp +++ lib/Driver/ToolChains/FreeBSD.cpp @@ -317,6 +317,8 @@ // When targeting 32-bit platforms, look for '/usr/lib32/crt1.o' and fall // back to '/usr/lib' if it doesn't exist. if ((Triple.getArch() == llvm::Triple::x86 || + Triple.getArch() == llvm::Triple::mips || + Triple.getArch() == llvm::Triple::mipsel || Triple.getArch() == llvm::Triple::ppc) && D.getVFS().exists(getDriver().SysRoot + "/usr/lib32/crt1.o")) getFilePaths().push_back(getDriver().SysRoot + "/usr/lib32"); Index: lib/Driver/ToolChains/FreeBSD.cpp === --- lib/Driver/ToolChains/FreeBSD.cpp +++ lib/Driver/ToolChains/FreeBSD.cpp @@ -317,6 +317,8 @@ // When targeting 32-bit platforms, look for '/usr/lib32/crt1.o' and fall // back to '/usr/lib' if it doesn't exist. if ((Triple.getArch() == llvm::Triple::x86 || + Triple.getArch() == llvm::Triple::mips || + Triple.getArch() == llvm::Triple::mipsel || Triple.getArch() == llvm::Triple::ppc) && D.getVFS().exists(getDriver().SysRoot + "/usr/lib32/crt1.o")) getFilePaths().push_back(getDriver().SysRoot + "/usr/lib32"); ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb added a comment. @sdardis Can you confirm if the existing N64 bits work fine for you or if the tests crash similarly? https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D42310: Formalize FreeBSD support of compiler rt
bsdjhb added a comment. My only question is if we want an OS version check as the FreeBSD driver does now for libc++ vs libstdc++? FreeBSD started using libcompiler_rt for libgcc.a in 9.0. Repository: rC Clang https://reviews.llvm.org/D42310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb added a comment. After fighting with cmake for a bit, I just broke down and cross-compiled the tests by hand and then ran them under a qemu system (rather than using qemu user mode). All of the tests ran fine for me without crashing using GCC 6.3.0 for FreeBSD 12 with N32. Given the save/restore code is identical for N32 and N64 I would have expected N64 to fail previously if it was restoring the wrong register? https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb added a comment.
In https://reviews.llvm.org/D39074#974913, @sdardis wrote:
> This was libunwind's test suite:
>
> Compiled test failed unexpectedly!
>
> Testing Time: 0.53s
>
> Failing Tests (1):
> libunwind :: libunwind_02.pass.cpp
>
> Expected Passes: 3
> Unexpected Failures: 1
>
>
>
> The hacky patch I used to test n32:
>
> --- a/test/libunwind/test/config.py
> +++ b/test/libunwind/test/config.py
> @@ -48,6 +48,8 @@ class Configuration(LibcxxConfiguration):
># Stack unwinding tests need unwinding tables and these are not
># generated by default on all Targets.
>self.cxx.compile_flags += ['-funwind-tables']
> +self.cxx.compile_flags += ['-mabi=n33']
> +self.cxx.link_flags += ['-mabi=n32']
>if not self.get_lit_bool('enable_threads', True):
>self.cxx.compile_flags += ['-D_LIBUNWIND_HAS_NO_THREADS']
>self.config.available_features.add('libunwind-no-threads')
>
>
Just to be sure, is that '-mabi=n33' in the compile flags a copy and paste typo
in the diff or do you have it locally in the real change as well?
https://reviews.llvm.org/D39074
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[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb added a comment. To be clear, are you getting the failure running libunwind's test suite or your own test? I've managed to get libunwind to cross-compile for me using GCC 6.3.0 on FreeBSD for O32, N32, and N64, but only to build the library, not the tests. I've been running a simple C++ test program (which is using a patched libunwind along with libc++ as it's C++ runtime) for testing. The program uses _Unwind_Backtrace() as well as throws a couple of C++ exceptions with catch handlers that print out the values thrown. If you are able to cross-build the libunwind tests and then run them under qemu I'd appreciate a pointer to get that working as I'd be happier running libunwind's tests than my own. https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb added inline comments. Comment at: src/Registers.hpp:2659 + uint32_t _padding; + double _floats[32]; +#endif I chose to always use double here to avoid having different context sizes for the 32-bit vs 64-bit FPR cases. https://reviews.llvm.org/D41968 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D41968: [libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.
bsdjhb created this revision. bsdjhb added a reviewer: sdardis. Herald added a subscriber: arichardson. For newabi this is fairly simple as we just save/restore the 32 floating-point registers as doubles. For O32 MIPS provides a variety of floating-point ABIs. For O32 MIPS with 64-bit floating-point registers, save/restore the 32 floating-point registers as doubles. For O32 MIPS with 32-bit floating-point registers, save/restore the 16 even registers as doubles. This probably isn't correct but does match the existing libunwind ABI that expects to save/restore floating point registers as doubles. For O32 with 32-bit FPRs the sticky point is trying to distinguish if a user of unw_get_fpreg() or unw_set_fpreg() is trying to operate on a float or a double. It's not clear to me what the right thing here is. If the goal is just to save/restore individual registers then perhaps the FPRs should always be stored as floats that get converted to doubles when returned from unw_get_fpreg() and vice versa? https://reviews.llvm.org/D41968 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -61,10 +61,9 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k -#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +#elif defined(__mips__) && defined(_ABIO32) # define REGISTER_KIND Registers_mips_o32 -#elif defined(__mips__) && (defined(_ABIN32) || defined(_ABI64)) &&\ -defined(__mips_soft_float) +#elif defined(__mips__) && (defined(_ABIN32) || defined(_ABI64)) # define REGISTER_KIND Registers_mips_newabi #elif defined(__mips__) # warning The MIPS architecture is not supported with this ABI and environment! Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,7 +116,7 @@ xorl %eax, %eax# return UNW_ESUCCESS ret -#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +#elif defined(__mips__) && defined(_ABIO32) # # extern int unw_getcontext(unw_context_t* thread_state) @@ -167,13 +167,65 @@ sw$8, (4 * 33)($4) mflo $8 sw$8, (4 * 34)($4) +#ifdef __mips_hard_float +#if __mips_fpr == 32 + s.d $f0, (4 * 36 + 8 * 0)($4) + s.d $f2, (4 * 36 + 8 * 2)($4) + s.d $f4, (4 * 36 + 8 * 4)($4) + s.d $f6, (4 * 36 + 8 * 6)($4) + s.d $f8, (4 * 36 + 8 * 8)($4) + s.d $f10, (4 * 36 + 8 * 10)($4) + s.d $f12, (4 * 36 + 8 * 12)($4) + s.d $f14, (4 * 36 + 8 * 14)($4) + s.d $f16, (4 * 36 + 8 * 16)($4) + s.d $f18, (4 * 36 + 8 * 18)($4) + s.d $f20, (4 * 36 + 8 * 20)($4) + s.d $f22, (4 * 36 + 8 * 22)($4) + s.d $f24, (4 * 36 + 8 * 24)($4) + s.d $f26, (4 * 36 + 8 * 26)($4) + s.d $f28, (4 * 36 + 8 * 28)($4) + s.d $f30, (4 * 36 + 8 * 30)($4) +#else + s.d $f0, (4 * 36 + 8 * 0)($4) + s.d $f1, (4 * 36 + 8 * 1)($4) + s.d $f2, (4 * 36 + 8 * 2)($4) + s.d $f3, (4 * 36 + 8 * 3)($4) + s.d $f4, (4 * 36 + 8 * 4)($4) + s.d $f5, (4 * 36 + 8 * 5)($4) + s.d $f6, (4 * 36 + 8 * 6)($4) + s.d $f7, (4 * 36 + 8 * 7)($4) + s.d $f8, (4 * 36 + 8 * 8)($4) + s.d $f9, (4 * 36 + 8 * 9)($4) + s.d $f10, (4 * 36 + 8 * 10)($4) + s.d $f11, (4 * 36 + 8 * 11)($4) + s.d $f12, (4 * 36 + 8 * 12)($4) + s.d $f13, (4 * 36 + 8 * 13)($4) + s.d $f14, (4 * 36 + 8 * 14)($4) + s.d $f15, (4 * 36 + 8 * 15)($4) + s.d $f16, (4 * 36 + 8 * 16)($4) + s.d $f17, (4 * 36 + 8 * 17)($4) + s.d $f18, (4 * 36 + 8 * 18)($4) + s.d $f19, (4 * 36 + 8 * 19)($4) + s.d $f20, (4 * 36 + 8 * 20)($4) + s.d $f21, (4 * 36 + 8 * 21)($4) + s.d $f22, (4 * 36 + 8 * 22)($4) + s.d $f23, (4 * 36 + 8 * 23)($4) + s.d $f24, (4 * 36 + 8 * 24)($4) + s.d $f25, (4 * 36 + 8 * 25)($4) + s.d $f26, (4 * 36 + 8 * 26)($4) + s.d $f27, (4 * 36 + 8 * 27)($4) + s.d $f28, (4 * 36 + 8 * 28)($4) + s.d $f29, (4 * 36 + 8 * 29)($4) + s.d $f30, (4 * 36 + 8 * 30)($4) + s.d $f31, (4 * 36 + 8 * 31)($4) +#endif +#endif jr $31 # return UNW_ESUCCESS or$2, $0, $0 .set pop -#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\ -defined(__mips_soft_float) +#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) # # extern int unw_getcontext(unw_context_t* thread_state) @@ -224,6 +276,40 @@ sd$8, (8 * 33)($4) mflo $8 sd$8, (8 * 34)($4) +#ifdef __mips_hard_float + s.d $f0, (8 * 35)($4) + s.d $f1, (8 * 36)($4) + s.d $f2, (8 * 37)($4) + s.d $f3, (8 * 38)($4) + s.d $f4, (8 * 39)($4) + s.d $f5, (8 * 40)($4) + s.d $f6, (8 * 41)($4) + s.d $f7, (8 * 42)($4) + s.d $f8, (8 * 43)($4) + s.d $f9, (8 * 44)($4) + s.d $f10, (8
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb updated this revision to Diff 129103.
bsdjhb added a comment.
- Rebase after N64 -> newabi commit.
https://reviews.llvm.org/D39074
Files:
include/__libunwind_config.h
src/AddressSpace.hpp
src/DwarfInstructions.hpp
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -63,7 +63,8 @@
# define REGISTER_KIND Registers_or1k
#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABIN32) || defined(_ABI64)) &&\
+defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -172,7 +172,8 @@
or$2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -685,7 +685,8 @@
lw$4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
//
// void libunwind::Registers_mips_newabi::jumpto()
Index: src/DwarfInstructions.hpp
===
--- src/DwarfInstructions.hpp
+++ src/DwarfInstructions.hpp
@@ -82,10 +82,10 @@
const RegisterLocation ) {
switch (savedReg.location) {
case CFI_Parser::kRegisterInCFA:
-return addressSpace.getP(cfa + (pint_t)savedReg.value);
+return addressSpace.getRegister(cfa + (pint_t)savedReg.value);
case CFI_Parser::kRegisterAtExpression:
-return addressSpace.getP(
+return addressSpace.getRegister(
evaluateExpression((pint_t)savedReg.value, addressSpace,
registers, cfa));
Index: src/AddressSpace.hpp
===
--- src/AddressSpace.hpp
+++ src/AddressSpace.hpp
@@ -207,6 +207,7 @@
return val;
}
uintptr_t getP(pint_t addr);
+ uint64_tgetRegister(pint_t addr);
static uint64_t getULEB128(pint_t , pint_t end);
static int64_t getSLEB128(pint_t , pint_t end);
@@ -228,6 +229,14 @@
#endif
}
+inline uint64_t LocalAddressSpace::getRegister(pint_t addr) {
+#if __SIZEOF_POINTER__ == 8 || (defined(__mips__) && defined(_ABIN32))
+ return get64(addr);
+#else
+ return get32(addr);
+#endif
+}
+
/// Read a ULEB128 into a 64-bit word.
inline uint64_t LocalAddressSpace::getULEB128(pint_t , pint_t end) {
const uint8_t *p = (uint8_t *)addr;
@@ -600,6 +609,7 @@
uint32_t get32(pint_t addr);
uint64_t get64(pint_t addr);
pint_tgetP(pint_t addr);
+ uint64_t getRegister(pint_t addr);
uint64_t getULEB128(pint_t , pint_t end);
int64_t getSLEB128(pint_t , pint_t end);
pint_tgetEncodedP(pint_t , pint_t end, uint8_t encoding,
@@ -636,7 +646,12 @@
}
template
-uint64_t RemoteAddressSpace::getULEB128(pint_t , pint_t end) {
+typename P::uint_t OtherAddressSpace::getRegister(pint_t addr) {
+ return P::getRegister(*(uint64_t *)localCopy(addr));
+}
+
+template
+uint64_t OtherAddressSpace::getULEB128(pint_t , pint_t end) {
uintptr_t size = (end - addr);
LocalAddressSpace::pint_t laddr = (LocalAddressSpace::pint_t) localCopy(addr);
LocalAddressSpace::pint_t sladdr = laddr;
Index: include/__libunwind_config.h
===
--- include/__libunwind_config.h
+++ include/__libunwind_config.h
@@ -75,6 +75,10 @@
#define _LIBUNWIND_TARGET_MIPS_O32 1
#define _LIBUNWIND_CONTEXT_SIZE 18
#define _LIBUNWIND_CURSOR_SIZE 24
+# elif defined(_ABIN32) && defined(__mips_soft_float)
+#define _LIBUNWIND_TARGET_MIPS_NEWABI 1
+#define _LIBUNWIND_CONTEXT_SIZE 35
+#define _LIBUNWIND_CURSOR_SIZE 42
# elif defined(_ABI64) && defined(__mips_soft_float)
#define _LIBUNWIND_TARGET_MIPS_NEWABI 1
#define _LIBUNWIND_CONTEXT_SIZE 35
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[PATCH] D41842: [libunwind][MIPS]: Rename Registers_mips_n64 to Registers_mips_newabi.
bsdjhb created this revision.
bsdjhb added reviewers: compnerd, sdardis.
Herald added a subscriber: arichardson.
This is in preparation for adding support for N32 unwinding which reuses
the newabi register class.
https://reviews.llvm.org/D41842
Files:
include/__libunwind_config.h
src/Registers.hpp
src/UnwindCursor.hpp
src/UnwindRegistersRestore.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -62,7 +62,7 @@
#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
-# define REGISTER_KIND Registers_mips_n64
+# define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
#else
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -593,12 +593,12 @@
#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
//
-// void libunwind::Registers_mips_n64::jumpto()
+// void libunwind::Registers_mips_newabi::jumpto()
//
// On entry:
// thread state pointer is in a0 ($4)
//
-DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv)
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
.set push
.set noat
.set noreorder
Index: src/UnwindCursor.hpp
===
--- src/UnwindCursor.hpp
+++ src/UnwindCursor.hpp
@@ -514,8 +514,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- int stepWithCompactEncoding(Registers_mips_n64 &) {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ int stepWithCompactEncoding(Registers_mips_newabi &) {
return UNW_EINVAL;
}
#endif
@@ -570,8 +570,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- bool compactSaysUseDwarf(Registers_mips_n64 &, uint32_t *) const {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ bool compactSaysUseDwarf(Registers_mips_newabi &, uint32_t *) const {
return true;
}
#endif
@@ -625,8 +625,8 @@
}
#endif
-#if defined (_LIBUNWIND_TARGET_MIPS_N64)
- compact_unwind_encoding_t dwarfEncoding(Registers_mips_n64 &) const {
+#if defined (_LIBUNWIND_TARGET_MIPS_NEWABI)
+ compact_unwind_encoding_t dwarfEncoding(Registers_mips_newabi &) const {
return 0;
}
#endif
Index: src/Registers.hpp
===
--- src/Registers.hpp
+++ src/Registers.hpp
@@ -2248,13 +2248,13 @@
}
#endif // _LIBUNWIND_TARGET_MIPS_O32
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
-/// Registers_mips_n64 holds the register state of a thread in a 64-bit MIPS
-/// process.
-class _LIBUNWIND_HIDDEN Registers_mips_n64 {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+/// Registers_mips_newabi holds the register state of a thread in a
+/// MIPS process using NEWABI (the N32 or N64 ABIs).
+class _LIBUNWIND_HIDDEN Registers_mips_newabi {
public:
- Registers_mips_n64();
- Registers_mips_n64(const void *registers);
+ Registers_mips_newabi();
+ Registers_mips_newabi(const void *registers);
boolvalidRegister(int num) const;
uint64_tgetRegister(int num) const;
@@ -2275,28 +2275,28 @@
void setIP(uint64_t value) { _registers.__pc = value; }
private:
- struct mips_n64_thread_state_t {
+ struct mips_newabi_thread_state_t {
uint64_t __r[32];
uint64_t __pc;
uint64_t __hi;
uint64_t __lo;
};
- mips_n64_thread_state_t _registers;
+ mips_newabi_thread_state_t _registers;
};
-inline Registers_mips_n64::Registers_mips_n64(const void *registers) {
- static_assert((check_fit::does_fit),
-"mips_n64 registers do not fit into unw_context_t");
+inline Registers_mips_newabi::Registers_mips_newabi(const void *registers) {
+ static_assert((check_fit::does_fit),
+"mips_newabi registers do not fit into unw_context_t");
memcpy(&_registers, static_cast(registers),
sizeof(_registers));
}
-inline Registers_mips_n64::Registers_mips_n64() {
+inline Registers_mips_newabi::Registers_mips_newabi() {
memset(&_registers, 0, sizeof(_registers));
}
-inline bool Registers_mips_n64::validRegister(int regNum) const {
+inline bool Registers_mips_newabi::validRegister(int regNum) const {
if (regNum == UNW_REG_IP)
return true;
if (regNum == UNW_REG_SP)
@@ -2313,7 +2313,7 @@
return false;
}
-inline uint64_t Registers_mips_n64::getRegister(int regNum) const {
+inline uint64_t Registers_mips_newabi::getRegister(int regNum) const {
if (regNum >= UNW_MIPS_R0 && regNum <= UNW_MIPS_R31)
return _registers.__r[regNum - UNW_MIPS_R0];
@@ -2327,10 +2327,10 @@
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb added a comment. Ok, I'm definitely fine with splitting the rename out into a separate patch. Will wait for @sdardis to be sure. https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb added a comment. ping @sdardis, @compnerd https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb updated this revision to Diff 126841.
bsdjhb marked an inline comment as done.
bsdjhb added a comment.
- Use __SIZEOF_POINTER__ instead of __LP64__.
- Adjust comment for newabi register class.
https://reviews.llvm.org/D39074
Files:
include/__libunwind_config.h
src/AddressSpace.hpp
src/DwarfInstructions.hpp
src/Registers.hpp
src/UnwindCursor.hpp
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -61,8 +61,9 @@
# define REGISTER_KIND Registers_or1k
#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
-# define REGISTER_KIND Registers_mips_n64
+#elif defined(__mips__) && (defined(_ABIN32) || defined(_ABI64)) &&\
+defined(__mips_soft_float)
+# define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
#else
Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -172,7 +172,8 @@
or$2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -590,15 +590,16 @@
lw$4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
//
-// void libunwind::Registers_mips_n64::jumpto()
+// void libunwind::Registers_mips_newabi::jumpto()
//
// On entry:
// thread state pointer is in a0 ($4)
//
-DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv)
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
.set push
.set noat
.set noreorder
Index: src/UnwindCursor.hpp
===
--- src/UnwindCursor.hpp
+++ src/UnwindCursor.hpp
@@ -514,8 +514,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- int stepWithCompactEncoding(Registers_mips_n64 &) {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ int stepWithCompactEncoding(Registers_mips_newabi &) {
return UNW_EINVAL;
}
#endif
@@ -570,8 +570,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- bool compactSaysUseDwarf(Registers_mips_n64 &, uint32_t *) const {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ bool compactSaysUseDwarf(Registers_mips_newabi &, uint32_t *) const {
return true;
}
#endif
@@ -625,8 +625,8 @@
}
#endif
-#if defined (_LIBUNWIND_TARGET_MIPS_N64)
- compact_unwind_encoding_t dwarfEncoding(Registers_mips_n64 &) const {
+#if defined (_LIBUNWIND_TARGET_MIPS_NEWABI)
+ compact_unwind_encoding_t dwarfEncoding(Registers_mips_newabi &) const {
return 0;
}
#endif
Index: src/Registers.hpp
===
--- src/Registers.hpp
+++ src/Registers.hpp
@@ -2248,13 +2248,13 @@
}
#endif // _LIBUNWIND_TARGET_MIPS_O32
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
-/// Registers_mips_n64 holds the register state of a thread in a 64-bit MIPS
-/// process.
-class _LIBUNWIND_HIDDEN Registers_mips_n64 {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+/// Registers_mips_newabi holds the register state of a thread in a
+/// MIPS process using NEWABI (the N32 or N64 ABIs).
+class _LIBUNWIND_HIDDEN Registers_mips_newabi {
public:
- Registers_mips_n64();
- Registers_mips_n64(const void *registers);
+ Registers_mips_newabi();
+ Registers_mips_newabi(const void *registers);
boolvalidRegister(int num) const;
uint64_tgetRegister(int num) const;
@@ -2275,28 +2275,28 @@
void setIP(uint64_t value) { _registers.__pc = value; }
private:
- struct mips_n64_thread_state_t {
+ struct mips_newabi_thread_state_t {
uint64_t __r[32];
uint64_t __pc;
uint64_t __hi;
uint64_t __lo;
};
- mips_n64_thread_state_t _registers;
+ mips_newabi_thread_state_t _registers;
};
-inline Registers_mips_n64::Registers_mips_n64(const void *registers) {
- static_assert((check_fit::does_fit),
-"mips_n64 registers do not fit into unw_context_t");
+inline Registers_mips_newabi::Registers_mips_newabi(const void *registers) {
+ static_assert((check_fit::does_fit),
+
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb marked 2 inline comments as done.
bsdjhb added inline comments.
Comment at: src/AddressSpace.hpp:201
+inline uint64_t LocalAddressSpace::getRegister(pint_t addr) {
+#if defined(__LP64__) || (defined(__mips__) && defined(_ABIN32))
+ return get64(addr);
compnerd wrote:
> Can you use `__SIZEOF_POINTER__` rather than `__LP64__` please? The former
> accounts for LLP64 environments as well.
I wonder if we should adjust the #if condition used to control the types of
pint_t and sint_t earlier in this file to also use __SIZEOF_POINTER__ (as a
separate change)?
https://reviews.llvm.org/D39074
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[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb updated this revision to Diff 126620.
bsdjhb added a comment.
- Rebase after O32/N64 commit.
https://reviews.llvm.org/D39074
Files:
include/__libunwind_config.h
src/AddressSpace.hpp
src/DwarfInstructions.hpp
src/Registers.hpp
src/UnwindCursor.hpp
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -61,8 +61,9 @@
# define REGISTER_KIND Registers_or1k
#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
-# define REGISTER_KIND Registers_mips_n64
+#elif defined(__mips__) && (defined(_ABIN32) || defined(_ABI64)) &&\
+defined(__mips_soft_float)
+# define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
#else
Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -172,7 +172,8 @@
or$2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -590,15 +590,16 @@
lw$4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
//
-// void libunwind::Registers_mips_n64::jumpto()
+// void libunwind::Registers_mips_newabi::jumpto()
//
// On entry:
// thread state pointer is in a0 ($4)
//
-DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv)
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
.set push
.set noat
.set noreorder
Index: src/UnwindCursor.hpp
===
--- src/UnwindCursor.hpp
+++ src/UnwindCursor.hpp
@@ -514,8 +514,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- int stepWithCompactEncoding(Registers_mips_n64 &) {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ int stepWithCompactEncoding(Registers_mips_newabi &) {
return UNW_EINVAL;
}
#endif
@@ -570,8 +570,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- bool compactSaysUseDwarf(Registers_mips_n64 &, uint32_t *) const {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ bool compactSaysUseDwarf(Registers_mips_newabi &, uint32_t *) const {
return true;
}
#endif
@@ -625,8 +625,8 @@
}
#endif
-#if defined (_LIBUNWIND_TARGET_MIPS_N64)
- compact_unwind_encoding_t dwarfEncoding(Registers_mips_n64 &) const {
+#if defined (_LIBUNWIND_TARGET_MIPS_NEWABI)
+ compact_unwind_encoding_t dwarfEncoding(Registers_mips_newabi &) const {
return 0;
}
#endif
Index: src/Registers.hpp
===
--- src/Registers.hpp
+++ src/Registers.hpp
@@ -2248,13 +2248,13 @@
}
#endif // _LIBUNWIND_TARGET_MIPS_O32
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
-/// Registers_mips_n64 holds the register state of a thread in a 64-bit MIPS
-/// process.
-class _LIBUNWIND_HIDDEN Registers_mips_n64 {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+/// Registers_mips_newabi holds the register state of a thread in a NEWABI
+/// MIPS process including both the N32 and N64 ABIs.
+class _LIBUNWIND_HIDDEN Registers_mips_newabi {
public:
- Registers_mips_n64();
- Registers_mips_n64(const void *registers);
+ Registers_mips_newabi();
+ Registers_mips_newabi(const void *registers);
boolvalidRegister(int num) const;
uint64_tgetRegister(int num) const;
@@ -2275,28 +2275,28 @@
void setIP(uint64_t value) { _registers.__pc = value; }
private:
- struct mips_n64_thread_state_t {
+ struct mips_newabi_thread_state_t {
uint64_t __r[32];
uint64_t __pc;
uint64_t __hi;
uint64_t __lo;
};
- mips_n64_thread_state_t _registers;
+ mips_newabi_thread_state_t _registers;
};
-inline Registers_mips_n64::Registers_mips_n64(const void *registers) {
- static_assert((check_fit::does_fit),
-"mips_n64 registers do not fit into unw_context_t");
+inline Registers_mips_newabi::Registers_mips_newabi(const void *registers) {
+ static_assert((check_fit::does_fit),
+"mips_newabi registers do not fit into unw_context_t");
memcpy(&_registers,
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. Ping @compnerd, @sdardis https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. Ping https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 121396. bsdjhb added a comment. - Rebase. - Update O32 cursor size after unw_word_t change. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -59,8 +59,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -67,7 +67,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,6 +116,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -524,6 +524,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +//
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. In https://reviews.llvm.org/D38110#910526, @mstorsjo wrote: > Just a heads up WRT this patch; we're discussing changing the size of > `unw_word_t` to match `uintptr_t` in https://reviews.llvm.org/D39365. Does > that break anything for your case? It shouldn't affect what's stored in the > Register class, only pointers in the unw_proc_info_t struct. Not sure which > patch will get completed/merged first though. Yes, I saw that. It will probably cause some breakage for the cursor size depending on which path (uint64_t always vs uintptr_t). I'm not quite sure which of those approaches is more correct to be honest. I also have an N32 patch in review but will wait until this one is finally committed before updating that further. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 120798. bsdjhb marked an inline comment as done. bsdjhb added a comment. - Rebase on more MAX_REGISTER changes. - Use macro for lastDwarfRegisterNumber. - Move MIPS ABI constants under a single #ifdef __mips__. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -59,8 +59,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -67,7 +67,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,6 +116,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -524,6 +524,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb updated this revision to Diff 120624.
bsdjhb added a comment.
- Rebase after MAX_REGISTER change.
https://reviews.llvm.org/D39074
Files:
include/__libunwind_config.h
src/AddressSpace.hpp
src/DwarfInstructions.hpp
src/Registers.hpp
src/UnwindCursor.hpp
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -61,8 +61,9 @@
# define REGISTER_KIND Registers_or1k
#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
-# define REGISTER_KIND Registers_mips_n64
+#elif defined(__mips__) && (defined(_ABIN32) || defined(_ABI64)) &&\
+defined(__mips_soft_float)
+# define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
#else
Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -172,7 +172,8 @@
or$2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -580,15 +580,16 @@
lw$4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
//
-// void libunwind::Registers_mips_n64::jumpto()
+// void libunwind::Registers_mips_newabi::jumpto()
//
// On entry:
// thread state pointer is in a0 ($4)
//
-DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv)
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
.set push
.set noat
.set noreorder
Index: src/UnwindCursor.hpp
===
--- src/UnwindCursor.hpp
+++ src/UnwindCursor.hpp
@@ -514,8 +514,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- int stepWithCompactEncoding(Registers_mips_n64 &) {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ int stepWithCompactEncoding(Registers_mips_newabi &) {
return UNW_EINVAL;
}
#endif
@@ -570,8 +570,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- bool compactSaysUseDwarf(Registers_mips_n64 &, uint32_t *) const {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ bool compactSaysUseDwarf(Registers_mips_newabi &, uint32_t *) const {
return true;
}
#endif
@@ -619,8 +619,8 @@
}
#endif
-#if defined (_LIBUNWIND_TARGET_MIPS_N64)
- compact_unwind_encoding_t dwarfEncoding(Registers_mips_n64 &) const {
+#if defined (_LIBUNWIND_TARGET_MIPS_NEWABI)
+ compact_unwind_encoding_t dwarfEncoding(Registers_mips_newabi &) const {
return 0;
}
#endif
Index: src/Registers.hpp
===
--- src/Registers.hpp
+++ src/Registers.hpp
@@ -2247,13 +2247,13 @@
}
#endif // _LIBUNWIND_TARGET_MIPS_O32
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
-/// Registers_mips_n64 holds the register state of a thread in a 64-bit MIPS
-/// process.
-class _LIBUNWIND_HIDDEN Registers_mips_n64 {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+/// Registers_mips_newabi holds the register state of a thread in a NEWABI
+/// MIPS process including both the N32 and N64 ABIs.
+class _LIBUNWIND_HIDDEN Registers_mips_newabi {
public:
- Registers_mips_n64();
- Registers_mips_n64(const void *registers);
+ Registers_mips_newabi();
+ Registers_mips_newabi(const void *registers);
boolvalidRegister(int num) const;
uint64_tgetRegister(int num) const;
@@ -2274,28 +2274,28 @@
void setIP(uint64_t value) { _registers.__pc = value; }
private:
- struct mips_n64_thread_state_t {
+ struct mips_newabi_thread_state_t {
uint64_t __r[32];
uint64_t __pc;
uint64_t __hi;
uint64_t __lo;
};
- mips_n64_thread_state_t _registers;
+ mips_newabi_thread_state_t _registers;
};
-inline Registers_mips_n64::Registers_mips_n64(const void *registers) {
- static_assert((check_fit::does_fit),
-"mips_n64 registers do not fit into unw_context_t");
+inline Registers_mips_newabi::Registers_mips_newabi(const void *registers) {
+ static_assert((check_fit::does_fit),
+"mips_newabi registers do not fit into unw_context_t");
memcpy(&_registers,
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 120623. bsdjhb added a comment. - Rebase for recent change to MAX_REGISTER meaning. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -59,8 +59,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -67,7 +67,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,6 +116,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -524,6 +524,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb marked 2 inline comments as done. bsdjhb added inline comments. Comment at: include/__libunwind_config.h:62 +# define _LIBUNWIND_CONTEXT_SIZE 35 +# define _LIBUNWIND_CURSOR_SIZE 46 +# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 66 sdardis wrote: > Shouldn't this 46 be 47? No, the other parts of a cursor besides the register context use ILP32 layout for N32 instead of LP64. In particular, I think N32 has less padding after the two 'bool' members at the end of UnwindCursor<>. https://reviews.llvm.org/D39074 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb updated this revision to Diff 120578.
bsdjhb marked 3 inline comments as done.
bsdjhb added a comment.
- Use correct #ifdef for N32.
- Rename N64 to newabi.
https://reviews.llvm.org/D39074
Files:
include/__libunwind_config.h
src/AddressSpace.hpp
src/DwarfInstructions.hpp
src/Registers.hpp
src/UnwindCursor.hpp
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -60,8 +60,9 @@
# define REGISTER_KIND Registers_or1k
#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
-# define REGISTER_KIND Registers_mips_n64
+#elif defined(__mips__) && (defined(_ABIN32) || defined(_ABI64)) &&\
+defined(__mips_soft_float)
+# define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment!
#else
Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -143,7 +143,8 @@
or$2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -545,15 +545,16 @@
lw$4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) &&\
+defined(__mips_soft_float)
//
-// void libunwind::Registers_mips_n64::jumpto()
+// void libunwind::Registers_mips_newabi::jumpto()
//
// On entry:
// thread state pointer is in a0 ($4)
//
-DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv)
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
.set push
.set noat
.set noreorder
Index: src/UnwindCursor.hpp
===
--- src/UnwindCursor.hpp
+++ src/UnwindCursor.hpp
@@ -520,8 +520,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- int stepWithCompactEncoding(Registers_mips_n64 &) {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ int stepWithCompactEncoding(Registers_mips_newabi &) {
return UNW_EINVAL;
}
#endif
@@ -576,8 +576,8 @@
}
#endif
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
- bool compactSaysUseDwarf(Registers_mips_n64 &, uint32_t *) const {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+ bool compactSaysUseDwarf(Registers_mips_newabi &, uint32_t *) const {
return true;
}
#endif
@@ -625,8 +625,8 @@
}
#endif
-#if defined (_LIBUNWIND_TARGET_MIPS_N64)
- compact_unwind_encoding_t dwarfEncoding(Registers_mips_n64 &) const {
+#if defined (_LIBUNWIND_TARGET_MIPS_NEWABI)
+ compact_unwind_encoding_t dwarfEncoding(Registers_mips_newabi &) const {
return 0;
}
#endif
Index: src/Registers.hpp
===
--- src/Registers.hpp
+++ src/Registers.hpp
@@ -2187,13 +2187,13 @@
}
#endif // _LIBUNWIND_TARGET_MIPS_O32
-#if defined(_LIBUNWIND_TARGET_MIPS_N64)
-/// Registers_mips_n64 holds the register state of a thread in a 64-bit MIPS
-/// process.
-class _LIBUNWIND_HIDDEN Registers_mips_n64 {
+#if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
+/// Registers_mips_newabi holds the register state of a thread in a NEWABI
+/// MIPS process including both the N32 and N64 ABIs.
+class _LIBUNWIND_HIDDEN Registers_mips_newabi {
public:
- Registers_mips_n64();
- Registers_mips_n64(const void *registers);
+ Registers_mips_newabi();
+ Registers_mips_newabi(const void *registers);
boolvalidRegister(int num) const;
uint64_tgetRegister(int num) const;
@@ -2214,28 +2214,28 @@
void setIP(uint64_t value) { _registers.__pc = value; }
private:
- struct mips_n64_thread_state_t {
+ struct mips_newabi_thread_state_t {
uint64_t __r[32];
uint64_t __pc;
uint64_t __hi;
uint64_t __lo;
};
- mips_n64_thread_state_t _registers;
+ mips_newabi_thread_state_t _registers;
};
-inline Registers_mips_n64::Registers_mips_n64(const void *registers) {
- static_assert((check_fit::does_fit),
-"mips_n64 registers do not fit into unw_context_t");
+inline Registers_mips_newabi::Registers_mips_newabi(const void *registers) {
+ static_assert((check_fit::does_fit),
+"mips_newabi
[PATCH] D39281: [libunwind] Express Registers_*::lastDwarfReg using _LIBUNWIND_HIGHEST_DWARF_REGISTER
bsdjhb added a comment. I think one source of truth is better than two. I do find the constant's value a bit off in general though. That is, the name 'HIGHEST' implies to me that it is the highest value used, not N + 1 as we currently define it. https://reviews.llvm.org/D39281 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb marked an inline comment as done. bsdjhb added a comment. Ping? https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D39074: [libunwind][MIPS]: Add support for unwinding in N32 processes.
bsdjhb created this revision.
Herald added subscribers: JDevlieghere, arichardson, aprantl.
N32 uses the same register context as N64. However, N32 requires one
change to properly fetch addresses from registers stored in memory.
Since N32 is an ILP32 platform, getP() only fetches the first 32-bits
of a stored register. For a big-endian platform this fetches the
upper 32-bits which will be zero. To fix this, add a new
getRegister() method to AddressSpace which is responsible for
extracting the address stored in a register in memory. This matches
getP() for all current ABIs except for N32 where it reads the 64-bit
register and returns the low 32-bits as an address. The
DwarfInstructions::getSavedRegister() method uses
AddressSpace::getRegister() instead of AddressSpace::getP().
Possibly, DwarfInstructions::getSavedRegister()'s return type should
be changed from pint_t to uint64_t.
https://reviews.llvm.org/D39074
Files:
include/__libunwind_config.h
src/AddressSpace.hpp
src/DwarfInstructions.hpp
src/UnwindRegistersRestore.S
src/UnwindRegistersSave.S
src/libunwind.cpp
Index: src/libunwind.cpp
===
--- src/libunwind.cpp
+++ src/libunwind.cpp
@@ -60,6 +60,8 @@
# define REGISTER_KIND Registers_or1k
#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32
+#elif defined(__mips__) && defined(_ABIN32) && defined(__mips_soft_float)
+# define REGISTER_KIND Registers_mips_n64
#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_n64
#elif defined(__mips__)
Index: src/UnwindRegistersSave.S
===
--- src/UnwindRegistersSave.S
+++ src/UnwindRegistersSave.S
@@ -143,7 +143,7 @@
or$2, $0, $0
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) && defined(__mips_soft_float)
#
# extern int unw_getcontext(unw_context_t* thread_state)
Index: src/UnwindRegistersRestore.S
===
--- src/UnwindRegistersRestore.S
+++ src/UnwindRegistersRestore.S
@@ -545,7 +545,7 @@
lw$4, (4 * 4)($4)
.set pop
-#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+#elif defined(__mips__) && (defined(_ABI64) || defined(_ABIN32)) && defined(__mips_soft_float)
//
// void libunwind::Registers_mips_n64::jumpto()
Index: src/DwarfInstructions.hpp
===
--- src/DwarfInstructions.hpp
+++ src/DwarfInstructions.hpp
@@ -82,10 +82,10 @@
const RegisterLocation ) {
switch (savedReg.location) {
case CFI_Parser::kRegisterInCFA:
-return addressSpace.getP(cfa + (pint_t)savedReg.value);
+return addressSpace.getRegister(cfa + (pint_t)savedReg.value);
case CFI_Parser::kRegisterAtExpression:
-return addressSpace.getP(
+return addressSpace.getRegister(
evaluateExpression((pint_t)savedReg.value, addressSpace,
registers, cfa));
Index: src/AddressSpace.hpp
===
--- src/AddressSpace.hpp
+++ src/AddressSpace.hpp
@@ -175,6 +175,7 @@
return val;
}
uintptr_t getP(pint_t addr);
+ uint64_tgetRegister(pint_t addr);
static uint64_t getULEB128(pint_t , pint_t end);
static int64_t getSLEB128(pint_t , pint_t end);
@@ -196,6 +197,14 @@
#endif
}
+inline uint64_t LocalAddressSpace::getRegister(pint_t addr) {
+#if defined(__LP64__) || defined(__mips_n32)
+ return get64(addr);
+#else
+ return get32(addr);
+#endif
+}
+
/// Read a ULEB128 into a 64-bit word.
inline uint64_t LocalAddressSpace::getULEB128(pint_t , pint_t end) {
const uint8_t *p = (uint8_t *)addr;
@@ -511,6 +520,7 @@
uint32_t get32(pint_t addr);
uint64_t get64(pint_t addr);
pint_tgetP(pint_t addr);
+ uint64_t getRegister(pint_t addr);
uint64_t getULEB128(pint_t , pint_t end);
int64_t getSLEB128(pint_t , pint_t end);
pint_tgetEncodedP(pint_t , pint_t end, uint8_t encoding,
@@ -547,7 +557,12 @@
}
template
-uint64_t RemoteAddressSpace::getULEB128(pint_t , pint_t end) {
+typename P::uint_t OtherAddressSpace::getRegister(pint_t addr) {
+ return P::getRegister(*(uint64_t *)localCopy(addr));
+}
+
+template
+uint64_t OtherAddressSpace::getULEB128(pint_t , pint_t end) {
uintptr_t size = (end - addr);
LocalAddressSpace::pint_t laddr = (LocalAddressSpace::pint_t) localCopy(addr);
LocalAddressSpace::pint_t sladdr = laddr;
Index: include/__libunwind_config.h
===
--- include/__libunwind_config.h
+++ include/__libunwind_config.h
@@ -56,6 +56,11 @@
# define _LIBUNWIND_CONTEXT_SIZE 18
# define _LIBUNWIND_CURSOR_SIZE 29
#
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb marked 2 inline comments as done. bsdjhb added inline comments. Comment at: src/UnwindRegistersSave.S:100 +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push sdardis wrote: > After looking at another implementation of libunwind and the other platforms > that are supported, it seems to me that we need to save all the registers. I was about to ask if that would be better as well. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 119245. bsdjhb added a comment. - Save all of the general purpose registers. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set
[PATCH] D38900: libunwind: document tested FreeBSD configs and sort OS list
bsdjhb added a comment. FreeBSD/i386 also uses llvm libunwind by default. https://reviews.llvm.org/D38900 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 118960. bsdjhb added a comment. - Check _ABI* rather than _MIPS_SIM. - Save and restore lo/hi. - Expand FIXME comment for more missing registers. - Return UNW_SUCCESS from unw_getcontext(). - Use correct DWARF numbers for hi and lo and put hi first. - Bump highest DWARF number for hi and lo. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,90 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + # s0 - s7 + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + # gp + sw$28, (4 * 28)($4) + # sp + sw$29, (4 * 29)($4) + # fp + sw$30, (4 * 30)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + # s0 - s7 + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + # gp + sd$28, (8 * 28)($4) + # sp + sd$29, (8 * 29)($4) + # fp + sd$30, (8 * 30)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set push + .set noat + .set noreorder + .set nomacro + // restore hi and lo + lw$8, (4 * 33)($4) + mthi $8 + lw$8, (4 * 34)($4) + mtlo $8 + // r0 is zero + lw$1, (4 * 1)($4) + lw$2, (4 * 2)($4) + lw$3, (4 * 3)($4) + // skip a0 for now + lw$5, (4 * 5)($4) + lw$6, (4 * 6)($4) + lw$7, (4 * 7)($4) + lw$8, (4 * 8)($4) + lw$9, (4 * 9)($4) + lw$10, (4 * 10)($4) + lw$11, (4 * 11)($4) + lw$12, (4 * 12)($4) + lw$13, (4 * 13)($4) + lw$14, (4 * 14)($4) + lw$15, (4 * 15)($4) + lw$16, (4 * 16)($4) + lw$17, (4 * 17)($4) + lw$18, (4 * 18)($4) + lw$19, (4 *
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 118638. bsdjhb added a comment. - Add more soft-float checks. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,76 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + # gp + sw$28, (4 * 28)($4) + # sp + sw$29, (4 * 29)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + jr $31 + # fp (in delay slot) + sw$30, (4 * 30)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + # gp + sd$28, (8 * 28)($4) + # sp + sd$29, (8 * 29)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + jr $31 + # fp (in delay slot) + sd$30, (8 * 30)($4) + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,108 @@ l.jr r9 l.nop +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set push + .set noat + .set noreorder + .set nomacro + // r0 is zero + lw$1, (4 * 1)($4) + lw$2, (4 * 2)($4) + lw$3, (4 * 3)($4) + // skip a0 for now + lw$5, (4 * 5)($4) + lw$6, (4 * 6)($4) + lw$7, (4 * 7)($4) + lw$8, (4 * 8)($4) + lw$9, (4 * 9)($4) + lw$10, (4 * 10)($4) + lw$11, (4 * 11)($4) + lw$12, (4 * 12)($4) + lw$13, (4 * 13)($4) + lw$14, (4 * 14)($4) + lw$15, (4 * 15)($4) + lw$16, (4 * 16)($4) + lw$17, (4 * 17)($4) + lw$18, (4 * 18)($4) + lw$19, (4 * 19)($4) + lw$20, (4 * 20)($4) + lw$21, (4 * 21)($4) + lw$22, (4 * 22)($4) + lw$23, (4 * 23)($4) + lw$24, (4 * 24)($4) + lw$25, (4 * 25)($4) + lw$26, (4 * 26)($4) + lw$27, (4 * 27)($4) + lw$28, (4 * 28)($4) + lw$29, (4 * 29)($4) + lw$30, (4 * 30)($4) + // load new pc into ra + lw$31, (4 * 32)($4) + // jump to ra, load a0 in the delay slot + jr$31 + lw$4, (4 * 4)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) + +// +// void
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. I keep running into issues trying to cross-build LLVM (it keeps wanting to use /usr/bin/cc or host libraries even though cross-compiling is enabled). I wonder if the failures you saw Simon might be due to https://bugs.llvm.org/show_bug.cgi?id=33858? Could you try applying the patch from https://reviews.llvm.org/D37484 along with this patchset to see if it fixes the test failures for you? https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. FYI, I was able to do simple testing (C++ programs throwing exceptions) using GCC 6.3 to compile a FreeBSD userland for both O32 and N64. Still working on cross-compiling LLVM so I can run the tests under qemu. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb marked 14 inline comments as done. bsdjhb added a comment. I have only tested this (test programs as mentioned earlier) with clang 5.0.0 (with a few patches) on o32 and n64. I am in the process of performing the same tests with GCC 6.3.0. I will also spend some time figuring out how to cross-build libunwind tests and run them inside of a qemu instance. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 117438. bsdjhb added a comment. - Fixes from review feedback. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,76 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + # gp + sw$28, (4 * 28)($4) + # sp + sw$29, (4 * 29)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + jr $31 + # fp (in delay slot) + sw$30, (4 * 30)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + # gp + sd$28, (8 * 28)($4) + # sp + sd$29, (8 * 29)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + jr $31 + # fp (in delay slot) + sd$30, (8 * 30)($4) + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,108 @@ l.jr r9 l.nop +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set push + .set noat + .set noreorder + .set nomacro + // r0 is zero + lw$1, (4 * 1)($4) + lw$2, (4 * 2)($4) + lw$3, (4 * 3)($4) + // skip a0 for now + lw$5, (4 * 5)($4) + lw$6, (4 * 6)($4) + lw$7, (4 * 7)($4) + lw$8, (4 * 8)($4) + lw$9, (4 * 9)($4) + lw$10, (4 * 10)($4) + lw$11, (4 * 11)($4) + lw$12, (4 * 12)($4) + lw$13, (4 * 13)($4) + lw$14, (4 * 14)($4) + lw$15, (4 * 15)($4) + lw$16, (4 * 16)($4) + lw$17, (4 * 17)($4) + lw$18, (4 * 18)($4) + lw$19, (4 * 19)($4) + lw$20, (4 * 20)($4) + lw$21, (4 * 21)($4) + lw$22, (4 * 22)($4) + lw$23, (4 * 23)($4) + lw$24, (4 * 24)($4) + lw$25, (4 * 25)($4) + lw$26, (4 * 26)($4) + lw$27, (4 * 27)($4) + lw$28, (4 * 28)($4) + lw$29, (4 * 29)($4) + lw$30, (4 * 30)($4) + // load new pc into ra + lw$31, (4 * 32)($4) + // jump to ra, load a0 in the delay slot + jr$31 + lw$4, (4 * 4)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 + +// +// void libunwind::Registers_mips_n64::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +//
