[PATCH] D159167: [clang-repl][Orc] Export executable symbols in ClangReplInterpreterExceptionTests

[Kai Luo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGca8d2533c79c: [clang-repl][Orc] Export executable symbols 
in… (authored by lkail).

Repository:
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Files:
  clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt


Index: clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
===
--- clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
+++ clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
@@ -22,3 +22,5 @@
   clangFrontend
   )
 add_dependencies(ClangReplInterpreterExceptionTests clang-resource-headers)
+
+export_executable_symbols(ClangReplInterpreterExceptionTests)


Index: clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
===
--- clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
+++ clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
@@ -22,3 +22,5 @@
   clangFrontend
   )
 add_dependencies(ClangReplInterpreterExceptionTests clang-resource-headers)
+
+export_executable_symbols(ClangReplInterpreterExceptionTests)
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[PATCH] D159167: [clang-repl][Orc] Export executable symbols in ClangReplInterpreterExceptionTests

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Ping.


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[PATCH] D159167: [clang-repl][Orc] Export executable symbols in ClangReplInterpreterExceptionTests

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: lhames, v.g.vassilev.
Herald added a project: All.
lkail requested review of this revision.
Herald added subscribers: cfe-commits, wangpc.
Herald added a project: clang.

In Orc runtime, we use `dlopen(nullptr, ...)` to open current executable, this 
requires `-rdynamic` flag.

As `llvm/CMakeLists.txt` suggests

  # Make sure we don't get -rdynamic in every binary. For those that need it,
  # use export_executable_symbols(target).

This patch exports symbols in `ClangReplInterpreterExceptionTests`. This also 
fixes `ClangReplInterpreterExceptionTests` is skipped on ppc64 when jitlink is 
used.


Repository:
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https://reviews.llvm.org/D159167

Files:
  clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt


Index: clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
===
--- clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
+++ clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
@@ -22,3 +22,5 @@
   clangFrontend
   )
 add_dependencies(ClangReplInterpreterExceptionTests clang-resource-headers)
+
+export_executable_symbols(ClangReplInterpreterExceptionTests)


Index: clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
===
--- clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
+++ clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
@@ -22,3 +22,5 @@
   clangFrontend
   )
 add_dependencies(ClangReplInterpreterExceptionTests clang-resource-headers)
+
+export_executable_symbols(ClangReplInterpreterExceptionTests)
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[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1ceaec3e8104: [PowerPC][altivec] Optimize codegen of 
vec_promote (authored by lkail).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  llvm/test/CodeGen/PowerPC/vec-promote.ll

Index: llvm/test/CodeGen/PowerPC/vec-promote.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/vec-promote.ll
@@ -0,0 +1,276 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-LE
+
+define noundef <2 x double> @vec_promote_double_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfd 0, 0(3)
+; CHECK-BE-NEXT:xxlxor 1, 1, 1
+; CHECK-BE-NEXT:xxmrghd 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfd 0, 0(3)
+; CHECK-LE-NEXT:xxlxor 1, 1, 1
+; CHECK-LE-NEXT:xxmrghd 34, 1, 0
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> , double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <2 x double> @vec_promote_double(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lxvdsx 34, 0, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> poison, double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfs 1, 0(3)
+; CHECK-BE-NEXT:xxlxor 0, 0, 0
+; CHECK-BE-NEXT:xxspltd 2, 0, 0
+; CHECK-BE-NEXT:xxmrghd 0, 1, 0
+; CHECK-BE-NEXT:xvcvdpsp 34, 2
+; CHECK-BE-NEXT:xvcvdpsp 35, 0
+; CHECK-BE-NEXT:vmrgew 2, 3, 2
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfs 1, 0(3)
+; CHECK-LE-NEXT:xxlxor 0, 0, 0
+; CHECK-LE-NEXT:xxspltd 2, 0, 0
+; CHECK-LE-NEXT:xxmrghd 0, 0, 1
+; CHECK-LE-NEXT:xvcvdpsp 34, 2
+; CHECK-LE-NEXT:xvcvdpsp 35, 0
+; CHECK-LE-NEXT:vmrgew 2, 2, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> , float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfiwzx 0, 0, 3
+; CHECK-BE-NEXT:xxspltw 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfiwzx 0, 0, 3
+; CHECK-LE-NEXT:xxspltw 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> poison, float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:ld 3, 0(3)
+; CHECK-BE-NEXT:li 4, 0
+; CHECK-BE-NEXT:mtfprd 0, 4
+; CHECK-BE-NEXT:mtfprd 1, 3
+; CHECK-BE-NEXT:xxmrghd 34, 1, 0
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:ld 3, 0(3)
+; CHECK-LE-NEXT:li 4, 0
+; CHECK-LE-NEXT:mtfprd 0, 4
+; CHECK-LE-NEXT:mtfprd 1, 3
+; CHECK-LE-NEXT:xxmrghd 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load i64, ptr %p, align 8
+  %vecins.i = insertelement <2 x i64> , i64 %0, i64 0
+  ret <2 x i64> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_long_long:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lxvdsx 34, 0, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load i64, ptr %p, align 8
+  %vecins.i = insertelement 

[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

> but it might be a good idea to improve codegen for the insert which might be 
> more common.

Yes. Usually `insertelement` is transformed to `BUILD_VECTOR` is SDAG, 
currently we don't have much optimization for `BUILD_VECTOR` in special 
patterns.


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[PATCH] D158484: [PowerPC][altivec] Correct modulo number of vec_promote on vector char

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6b6ea93125bd: [PowerPC][altivec] Correct modulo number of 
vec_promote on vector char (authored by lkail).

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Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c


Index: clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
@@ -2250,18 +2250,18 @@
 
 res_vsc = vec_promote(asc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 
 res_vuc = vec_promote(auc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 }
 
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -14648,14 +14648,14 @@
 static __inline__ vector signed char __ATTRS_o_ai vec_promote(signed char __a,
   int __b) {
   vector signed char __res = (vector signed char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_promote(unsigned char __a, int __b) {
   vector unsigned char __res = (vector unsigned char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 


Index: clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
@@ -2250,18 +2250,18 @@
 
 res_vsc = vec_promote(asc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 
 res_vuc = vec_promote(auc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 }
 
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -14648,14 +14648,14 @@
 static __inline__ vector signed char __ATTRS_o_ai vec_promote(signed char __a,
   int __b) {
   vector signed char __res = (vector signed char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_promote(unsigned char __a, int __b) {
   vector unsigned char __res = (vector unsigned char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 
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[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/lib/Headers/altivec.h:14662
+  vector unsigned char __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1);

lkail wrote:
> qiucf wrote:
> > Could we just define it without initialization? This can also make 
> > undefined vector.
> Using `__builtin_shufflevector` generates poison values, which is stronger 
> than `undef`, exposing more optimizations in my view. See 
> https://llvm.org/docs/LangRef.html#id1781.
Also using `__builtin_shufflevector` is explicit, which has a formal 
specification 
https://clang.llvm.org/docs/LanguageExtensions.html#langext-builtin-shufflevector.


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[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/lib/Headers/altivec.h:14662
+  vector unsigned char __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1);

qiucf wrote:
> Could we just define it without initialization? This can also make undefined 
> vector.
Using `__builtin_shufflevector` generates poison values, which is stronger than 
`undef`, exposing more optimizations in my view. See 
https://llvm.org/docs/LangRef.html#id1781.



Comment at: llvm/test/CodeGen/PowerPC/vec-promote.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs -mcpu=pwr8 
\

qiucf wrote:
> We don't need this file because (1) no backend codegen changed; (2) further 
> changes to `altivec.h` will not change this file.
I prefer keeping this file
1. Backend lacks vec_promote equivalent tests.
2. to show different codegen of FE exposes different optimization opportunities 
to backend which is the core value of this patch. Codegen quality should be 
finally reflected by assembly.


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[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 552251.

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Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  llvm/test/CodeGen/PowerPC/vec-promote.ll

Index: llvm/test/CodeGen/PowerPC/vec-promote.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/vec-promote.ll
@@ -0,0 +1,276 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-LE
+
+define noundef <2 x double> @vec_promote_double_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfd 0, 0(3)
+; CHECK-BE-NEXT:xxlxor 1, 1, 1
+; CHECK-BE-NEXT:xxmrghd 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfd 0, 0(3)
+; CHECK-LE-NEXT:xxlxor 1, 1, 1
+; CHECK-LE-NEXT:xxmrghd 34, 1, 0
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> , double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <2 x double> @vec_promote_double(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lxvdsx 34, 0, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> poison, double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfs 1, 0(3)
+; CHECK-BE-NEXT:xxlxor 0, 0, 0
+; CHECK-BE-NEXT:xxspltd 2, 0, 0
+; CHECK-BE-NEXT:xxmrghd 0, 1, 0
+; CHECK-BE-NEXT:xvcvdpsp 34, 2
+; CHECK-BE-NEXT:xvcvdpsp 35, 0
+; CHECK-BE-NEXT:vmrgew 2, 3, 2
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfs 1, 0(3)
+; CHECK-LE-NEXT:xxlxor 0, 0, 0
+; CHECK-LE-NEXT:xxspltd 2, 0, 0
+; CHECK-LE-NEXT:xxmrghd 0, 0, 1
+; CHECK-LE-NEXT:xvcvdpsp 34, 2
+; CHECK-LE-NEXT:xvcvdpsp 35, 0
+; CHECK-LE-NEXT:vmrgew 2, 2, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> , float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfiwzx 0, 0, 3
+; CHECK-BE-NEXT:xxspltw 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfiwzx 0, 0, 3
+; CHECK-LE-NEXT:xxspltw 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> poison, float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:ld 3, 0(3)
+; CHECK-BE-NEXT:li 4, 0
+; CHECK-BE-NEXT:mtfprd 0, 4
+; CHECK-BE-NEXT:mtfprd 1, 3
+; CHECK-BE-NEXT:xxmrghd 34, 1, 0
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:ld 3, 0(3)
+; CHECK-LE-NEXT:li 4, 0
+; CHECK-LE-NEXT:mtfprd 0, 4
+; CHECK-LE-NEXT:mtfprd 1, 3
+; CHECK-LE-NEXT:xxmrghd 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load i64, ptr %p, align 8
+  %vecins.i = insertelement <2 x i64> , i64 %0, i64 0
+  ret <2 x i64> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_long_long:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lxvdsx 34, 0, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load i64, ptr %p, align 8
+  %vecins.i = insertelement <2 x i64> poison, i64 %0, i64 0
+  ret <2 x i64> %vecins.i
+}
+
+define noundef <4 x i32> @vec_promote_int_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_int_zeroed

[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 552226.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158487/new/

https://reviews.llvm.org/D158487

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  llvm/test/CodeGen/PowerPC/vec-promote.ll

Index: llvm/test/CodeGen/PowerPC/vec-promote.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/vec-promote.ll
@@ -0,0 +1,276 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-LE
+
+define noundef <2 x double> @vec_promote_double_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfd 0, 0(3)
+; CHECK-BE-NEXT:xxlxor 1, 1, 1
+; CHECK-BE-NEXT:xxmrghd 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfd 0, 0(3)
+; CHECK-LE-NEXT:xxlxor 1, 1, 1
+; CHECK-LE-NEXT:xxmrghd 34, 1, 0
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> , double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <2 x double> @vec_promote_double(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lxvdsx 34, 0, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> poison, double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfs 1, 0(3)
+; CHECK-BE-NEXT:xxlxor 0, 0, 0
+; CHECK-BE-NEXT:xxspltd 2, 0, 0
+; CHECK-BE-NEXT:xxmrghd 0, 1, 0
+; CHECK-BE-NEXT:xvcvdpsp 34, 2
+; CHECK-BE-NEXT:xvcvdpsp 35, 0
+; CHECK-BE-NEXT:vmrgew 2, 3, 2
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfs 1, 0(3)
+; CHECK-LE-NEXT:xxlxor 0, 0, 0
+; CHECK-LE-NEXT:xxspltd 2, 0, 0
+; CHECK-LE-NEXT:xxmrghd 0, 0, 1
+; CHECK-LE-NEXT:xvcvdpsp 34, 2
+; CHECK-LE-NEXT:xvcvdpsp 35, 0
+; CHECK-LE-NEXT:vmrgew 2, 2, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> , float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfiwzx 0, 0, 3
+; CHECK-BE-NEXT:xxspltw 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfiwzx 0, 0, 3
+; CHECK-LE-NEXT:xxspltw 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> poison, float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:ld 3, 0(3)
+; CHECK-BE-NEXT:li 4, 0
+; CHECK-BE-NEXT:mtfprd 0, 4
+; CHECK-BE-NEXT:mtfprd 1, 3
+; CHECK-BE-NEXT:xxmrghd 34, 1, 0
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:ld 3, 0(3)
+; CHECK-LE-NEXT:li 4, 0
+; CHECK-LE-NEXT:mtfprd 0, 4
+; CHECK-LE-NEXT:mtfprd 1, 3
+; CHECK-LE-NEXT:xxmrghd 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load i64, ptr %p, align 8
+  %vecins.i = insertelement <2 x i64> , i64 %0, i64 0
+  ret <2 x i64> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_long_long:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lxvdsx 34, 0, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load i64, ptr %p, align 8
+  %vecins.i = insertelement <2 x i64> poison, i64 %0, i64 0
+  ret <2 x i64> %vecins.i
+}
+
+define noundef <4 x i32> @vec_promote_int_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_int_zeroed

[PATCH] D158487: [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: nemanjai, shchenz, stefanp, PowerPC, amyk.
Herald added a subscriber: kbarton.
Herald added a project: All.
lkail requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

According to 
https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.1?topic=functions-vec-promote,
 elements not specified by the input index argument are undefined. So that we 
don't need to set these elements to be zeros.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158487

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
  llvm/test/CodeGen/PowerPC/vec-promote.ll

Index: llvm/test/CodeGen/PowerPC/vec-promote.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/vec-promote.ll
@@ -0,0 +1,276 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs -mcpu=pwr8 \
+; RUN:   < %s | FileCheck %s --check-prefix=CHECK-LE
+
+define noundef <2 x double> @vec_promote_double_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfd 0, 0(3)
+; CHECK-BE-NEXT:xxlxor 1, 1, 1
+; CHECK-BE-NEXT:xxmrghd 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfd 0, 0(3)
+; CHECK-LE-NEXT:xxlxor 1, 1, 1
+; CHECK-LE-NEXT:xxmrghd 34, 1, 0
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> , double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <2 x double> @vec_promote_double(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_double:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_double:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lxvdsx 34, 0, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load double, ptr %p, align 8
+  %vecins.i = insertelement <2 x double> poison, double %0, i64 0
+  ret <2 x double> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfs 1, 0(3)
+; CHECK-BE-NEXT:xxlxor 0, 0, 0
+; CHECK-BE-NEXT:xxspltd 2, 0, 0
+; CHECK-BE-NEXT:xxmrghd 0, 1, 0
+; CHECK-BE-NEXT:xvcvdpsp 34, 2
+; CHECK-BE-NEXT:xvcvdpsp 35, 0
+; CHECK-BE-NEXT:vmrgew 2, 3, 2
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfs 1, 0(3)
+; CHECK-LE-NEXT:xxlxor 0, 0, 0
+; CHECK-LE-NEXT:xxspltd 2, 0, 0
+; CHECK-LE-NEXT:xxmrghd 0, 0, 1
+; CHECK-LE-NEXT:xvcvdpsp 34, 2
+; CHECK-LE-NEXT:xvcvdpsp 35, 0
+; CHECK-LE-NEXT:vmrgew 2, 2, 3
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> , float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <4 x float> @vec_promote_float(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_float:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lfiwzx 0, 0, 3
+; CHECK-BE-NEXT:xxspltw 34, 0, 1
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_float:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:lfiwzx 0, 0, 3
+; CHECK-LE-NEXT:xxspltw 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load float, ptr %p, align 8
+  %vecins.i = insertelement <4 x float> poison, float %0, i64 0
+  ret <4 x float> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long_zeroed(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:ld 3, 0(3)
+; CHECK-BE-NEXT:li 4, 0
+; CHECK-BE-NEXT:mtfprd 0, 4
+; CHECK-BE-NEXT:mtfprd 1, 3
+; CHECK-BE-NEXT:xxmrghd 34, 1, 0
+; CHECK-BE-NEXT:blr
+;
+; CHECK-LE-LABEL: vec_promote_long_long_zeroed:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:ld 3, 0(3)
+; CHECK-LE-NEXT:li 4, 0
+; CHECK-LE-NEXT:mtfprd 0, 4
+; CHECK-LE-NEXT:mtfprd 1, 3
+; CHECK-LE-NEXT:xxmrghd 34, 0, 1
+; CHECK-LE-NEXT:blr
+entry:
+  %0 = load i64, ptr %p, align 8
+  %vecins.i = insertelement <2 x i64> , i64 %0, i64 0
+  ret <2 x i64> %vecins.i
+}
+
+define noundef <2 x i64> @vec_promote_long_long(ptr nocapture noundef readonly %p) {
+; CHECK-BE-LABEL: vec_promote_long_long:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvdsx 34, 0, 3
+; CHECK-BE-NEXT:blr
+;
+

[PATCH] D158484: [PowerPC][altivec] Correct modulo number of vector char

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: PowerPC, nemanjai, qiucf.
Herald added subscribers: sunshaoce, shchenz, kbarton.
Herald added a project: All.
lkail requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

According to 
https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.1?topic=functions-vec-promote,
 the index should be input modulo the number of elements in the vector. When 
the type is `vector char`, the number of elements should be 16.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158484

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c


Index: clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
@@ -2250,18 +2250,18 @@
 
 res_vsc = vec_promote(asc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 
 res_vuc = vec_promote(auc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 }
 
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -14648,14 +14648,14 @@
 static __inline__ vector signed char __ATTRS_o_ai vec_promote(signed char __a,
   int __b) {
   vector signed char __res = (vector signed char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_promote(unsigned char __a, int __b) {
   vector unsigned char __res = (vector unsigned char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 


Index: clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
===
--- clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
@@ -2250,18 +2250,18 @@
 
 res_vsc = vec_promote(asc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 
 res_vuc = vec_promote(auc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 }
 
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -14648,14 +14648,14 @@
 static __inline__ vector signed char __ATTRS_o_ai vec_promote(signed char __a,
   int __b) {
   vector signed char __res = (vector signed char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_promote(unsigned char __a, int __b) {
   vector unsigned char __res = (vector unsigned char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 
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[PATCH] D137536: [NFC] Replace use of PPC64 macro into powerpc64 in intrinsic headers

[Kai Luo via Phabricator via cfe-commits]

lkail accepted this revision as: lkail.
lkail added a comment.
This revision is now accepted and ready to land.

lgtm. Though `__PPC64__` is kept in https://reviews.llvm.org/D137511, we prefer 
to use `__powerpc64__` which is documented in https://reviews.llvm.org/D137511.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137536/new/

https://reviews.llvm.org/D137536

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[PATCH] D136229: [include-cleaner] Fix link errors when -DBUILD_SHARED_LIBS=ON

[Kai Luo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2e73129483c4: [include-cleaner] Fix link errors when 
-DBUILD_SHARED_LIBS=ON (authored by lkail).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136229/new/

https://reviews.llvm.org/D136229

Files:
  clang-tools-extra/include-cleaner/lib/CMakeLists.txt
  clang-tools-extra/include-cleaner/tool/CMakeLists.txt


Index: clang-tools-extra/include-cleaner/tool/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/tool/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/tool/CMakeLists.txt
@@ -4,6 +4,8 @@
 add_clang_tool(clang-include-cleaner IncludeCleaner.cpp)
 clang_target_link_libraries(clang-include-cleaner PRIVATE
   clangBasic
+  clangFrontend
+  clangSerialization
   clangTooling
   )
 target_link_libraries(clang-include-cleaner PRIVATE
Index: clang-tools-extra/include-cleaner/lib/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/lib/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/lib/CMakeLists.txt
@@ -6,7 +6,8 @@
   WalkAST.cpp
 
   LINK_LIBS
-  clangBasic
   clangAST
+  clangBasic
+  clangLex
   )
 


Index: clang-tools-extra/include-cleaner/tool/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/tool/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/tool/CMakeLists.txt
@@ -4,6 +4,8 @@
 add_clang_tool(clang-include-cleaner IncludeCleaner.cpp)
 clang_target_link_libraries(clang-include-cleaner PRIVATE
   clangBasic
+  clangFrontend
+  clangSerialization
   clangTooling
   )
 target_link_libraries(clang-include-cleaner PRIVATE
Index: clang-tools-extra/include-cleaner/lib/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/lib/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/lib/CMakeLists.txt
@@ -6,7 +6,8 @@
   WalkAST.cpp
 
   LINK_LIBS
-  clangBasic
   clangAST
+  clangBasic
+  clangLex
   )
 
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[PATCH] D136229: [include-cleaner] Fix link errors when -DBUILD_SHARED_LIBS=ON

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: hokein, sammccall, PowerPC.
Herald added a project: All.
lkail requested review of this revision.
Herald added a project: clang-tools-extra.
Herald added a subscriber: cfe-commits.

Fixed ppc buildbot https://lab.llvm.org/buildbot/#/builders/121/builds/24273 
which is using `-DBUILD_SHARED_LIBS=ON`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136229

Files:
  clang-tools-extra/include-cleaner/lib/CMakeLists.txt
  clang-tools-extra/include-cleaner/tool/CMakeLists.txt


Index: clang-tools-extra/include-cleaner/tool/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/tool/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/tool/CMakeLists.txt
@@ -4,6 +4,8 @@
 add_clang_tool(clang-include-cleaner IncludeCleaner.cpp)
 clang_target_link_libraries(clang-include-cleaner PRIVATE
   clangBasic
+  clangFrontend
+  clangSerialization
   clangTooling
   )
 target_link_libraries(clang-include-cleaner PRIVATE
Index: clang-tools-extra/include-cleaner/lib/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/lib/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/lib/CMakeLists.txt
@@ -6,7 +6,8 @@
   WalkAST.cpp
 
   LINK_LIBS
-  clangBasic
   clangAST
+  clangBasic
+  clangLex
   )
 


Index: clang-tools-extra/include-cleaner/tool/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/tool/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/tool/CMakeLists.txt
@@ -4,6 +4,8 @@
 add_clang_tool(clang-include-cleaner IncludeCleaner.cpp)
 clang_target_link_libraries(clang-include-cleaner PRIVATE
   clangBasic
+  clangFrontend
+  clangSerialization
   clangTooling
   )
 target_link_libraries(clang-include-cleaner PRIVATE
Index: clang-tools-extra/include-cleaner/lib/CMakeLists.txt
===
--- clang-tools-extra/include-cleaner/lib/CMakeLists.txt
+++ clang-tools-extra/include-cleaner/lib/CMakeLists.txt
@@ -6,7 +6,8 @@
   WalkAST.cpp
 
   LINK_LIBS
-  clangBasic
   clangAST
+  clangBasic
+  clangLex
   )
 
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[PATCH] D135848: [clang][Module][AIX] Mark test unsupported since objc doesn't have xcoff support

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe231a580139a: [clang][Module][AIX] Mark test unsupported 
since objc doesn't have xcoff support (authored by lkail).

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Files:
  clang/test/Modules/module-file-home-is-cwd.m


Index: clang/test/Modules/module-file-home-is-cwd.m
===
--- clang/test/Modules/module-file-home-is-cwd.m
+++ clang/test/Modules/module-file-home-is-cwd.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -zos, -aix
 // RUN: cd %S
 // RUN: %clang_cc1 -x objective-c -fmodules -fno-implicit-modules \
 // RUN: -fmodule-file-home-is-cwd -fmodule-name=libA -emit-module \


Index: clang/test/Modules/module-file-home-is-cwd.m
===
--- clang/test/Modules/module-file-home-is-cwd.m
+++ clang/test/Modules/module-file-home-is-cwd.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -zos, -aix
 // RUN: cd %S
 // RUN: %clang_cc1 -x objective-c -fmodules -fno-implicit-modules \
 // RUN: -fmodule-file-home-is-cwd -fmodule-name=libA -emit-module \
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[PATCH] D135848: [clang][Module][AIX] Mark test unsupported since objc doesn't have xcoff support

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/test/Modules/module-file-home-is-cwd.m:1
+// UNSUPPORTED: aix
 // RUN: cd %S

hubert.reinterpretcast wrote:
> We see GOFF in the same list.
Nice one.


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[PATCH] D135848: [clang][Module][AIX] Mark test unsupported since objc doesn't have xcoff support

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 467356.

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Files:
  clang/test/Modules/module-file-home-is-cwd.m


Index: clang/test/Modules/module-file-home-is-cwd.m
===
--- clang/test/Modules/module-file-home-is-cwd.m
+++ clang/test/Modules/module-file-home-is-cwd.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -zos, -aix
 // RUN: cd %S
 // RUN: %clang_cc1 -x objective-c -fmodules -fno-implicit-modules \
 // RUN: -fmodule-file-home-is-cwd -fmodule-name=libA -emit-module \


Index: clang/test/Modules/module-file-home-is-cwd.m
===
--- clang/test/Modules/module-file-home-is-cwd.m
+++ clang/test/Modules/module-file-home-is-cwd.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -zos, -aix
 // RUN: cd %S
 // RUN: %clang_cc1 -x objective-c -fmodules -fno-implicit-modules \
 // RUN: -fmodule-file-home-is-cwd -fmodule-name=libA -emit-module \
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[PATCH] D135848: [clang][Module][AIX] Mark test unsupported since objc doesn't have xcoff support

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: hubert.reinterpretcast, daltenty, stevewan.
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Herald added a project: clang.

Fixed error

  Command Output (stderr):
  --
  fatal error: error in backend: Objective-C support is unimplemented for 
object file format

Source code in `clang/lib/CodeGen/CGObjCMac.cpp:5080`

  c++
case llvm::Triple::Wasm:
case llvm::Triple::GOFF:
case llvm::Triple::SPIRV:
case llvm::Triple::XCOFF:
case llvm::Triple::DXContainer:
  llvm::report_fatal_error(
  "Objective-C support is unimplemented for object file format");
}


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Files:
  clang/test/Modules/module-file-home-is-cwd.m


Index: clang/test/Modules/module-file-home-is-cwd.m
===
--- clang/test/Modules/module-file-home-is-cwd.m
+++ clang/test/Modules/module-file-home-is-cwd.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: aix
 // RUN: cd %S
 // RUN: %clang_cc1 -x objective-c -fmodules -fno-implicit-modules \
 // RUN: -fmodule-file-home-is-cwd -fmodule-name=libA -emit-module \


Index: clang/test/Modules/module-file-home-is-cwd.m
===
--- clang/test/Modules/module-file-home-is-cwd.m
+++ clang/test/Modules/module-file-home-is-cwd.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: aix
 // RUN: cd %S
 // RUN: %clang_cc1 -x objective-c -fmodules -fno-implicit-modules \
 // RUN: -fmodule-file-home-is-cwd -fmodule-name=libA -emit-module \
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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1cbaf681b0f1: [clang][AIX] Add option to control quadword 
lock free atomics ABI on AIX (authored by lkail).

Repository:
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Files:
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Driver/aix-quadword-atomics-abi.c
  clang/test/Driver/ppc-unsupported.c
  clang/test/Sema/atomic-ops.c

Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -10,6 +10,12 @@
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
 // RUN:   -target-cpu pwr8 -DPPC64_PWR8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -target-cpu pwr8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -mabi=quadword-atomics -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/Driver/ppc-unsupported.c
===
--- clang/test/Driver/ppc-unsupported.c
+++ clang/test/Driver/ppc-unsupported.c
@@ -7,4 +7,14 @@
 // RUN:   -c %s 2>&1 | FileCheck %s
 // RUN: not %clang -target powerpc64le-unknown-linux -msvr4-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-freebsd -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-linux -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-unknown -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-aix -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
 // CHECK: unsupported option
Index: clang/test/Driver/aix-quadword-atomics-abi.c
===
--- /dev/null
+++ clang/test/Driver/aix-quadword-atomics-abi.c
@@ -0,0 +1,11 @@
+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc-unknown-aix -mabi=quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-TARGET %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -mabi=quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck %s --check-prefix=CHECK-QUADWORD-ATOMICS
+//
+// CHECK-UNSUPPORTED-TARGET: unsupported option '-mabi=quadword-atomics' for target 'powerpc-unknown-aix'
+// CHECK-NOT: "-mabi=quadword-atomics"
+// CHECK-QUADWORD-ATOMICS: "-cc1"
+// CHECK-QUADWORD-ATOMICS-SAME: "-mabi=quadword-atomics"
Index: clang/test/CodeGen/PowerPC/quadword-atomics.c
===
--- clang/test/CodeGen/PowerPC/quadword-atomics.c
+++ clang/test/CodeGen/PowerPC/quadword-atomics.c
@@ -1,9 +1,15 @@
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
-// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-QUADWORD-ATOMICS
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
 // RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
 // RUN:   -target-cpu pwr7 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -mabi=quadword-atomics -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s \
+// RUN:   --check-prefix=PPC64-QUADWORD-ATOMICS
+
 
 typedef struct {
   char x[16];
@@ -13,8 +19,8 @@
 
 typedef __int128_t int128_t;
 
-// PPC64-PWR8-LABEL: @test_load(
-// PPC64-PWR8:[[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_load(
+// PPC64-QUADWORD-ATO

[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/include/clang/Driver/Options.td:3611
   HelpText<"Enable the default Altivec ABI on AIX (AIX only). Uses only 
volatile vector registers.">;
+def maix_quadword_atomics : Flag<["-"], "maix64-quadword-atomics">,
+  Group, Flags<[CC1Option]>,

shchenz wrote:
> lkail wrote:
> > shchenz wrote:
> > > lkail wrote:
> > > > shchenz wrote:
> > > > > amyk wrote:
> > > > > > Would it be better if we called this `maix64-quadword-atomics` 
> > > > > > instead? 
> > > > > Do we need to change the backend check below too?
> > > > > ```
> > > > > bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
> > > > >   // TODO: 16-byte atomic type support for AIX is in progress; we 
> > > > > should be able
> > > > >   // to inline 16-byte atomic ops on AIX too in the future.
> > > > >   return Subtarget.isPPC64() &&
> > > > >  (EnableQuadwordAtomics || 
> > > > > !Subtarget.getTargetTriple().isOSAIX()) &&
> > > > >  Subtarget.hasQuadwordAtomics();
> > > > > }
> > > > > ```
> > > > We don't need to change this yet. When we are compiling a quadword lock 
> > > > free libatomic, we use options `-mabi=quadword-atomics -mllvm 
> > > > -ppc-quadword-atomics` to enforce generating quadword lock-free code on 
> > > > AIX.
> > > This makes me confuse. We need to two different options to control the 
> > > frontend and backend behavior?
> > > 
> > > Is it the final usage? Or we will add a follow up patch to map the 
> > > backend one to the FE one? IMO finally we only need the driver option 
> > > `-mabi=quadword-atomics` to control the final code generation for 128 bit 
> > > atomic operations, right?
> > > This makes me confuse. We need to two different options to control the 
> > > frontend and backend behavior?
> > 
> > This is multi-lang support consideration. clang is not the only frontend we 
> > have using LLVM as backend on AIX. If other language frontend generates 
> > `store atomic i128, ...`, the backend is supposed to generate libcalls into 
> > libatomic currently.
> > 
> > > Is it the final usage?
> > No. We finally want to achieve `-mabi=quadword-atomics` by default and 
> > generate inline atomic code for cpu above pwr7 by default(no need to take 
> > OS into consideration).
> I know what you mean. But I assume the driver option `-mabi=quadword-atomics` 
> will impact the assembly instead of just impact the frontend, right? Using 
> `-mllvm` option is not right as the final solution.
> 
> There are some driver options example, like `-gstrict-dwarf`, Frontend can 
> control the backend behavior and the backend can also change this option by 
> `-strict-dwarf`.
> 
> Could you please explain:
> 1: how the backend will handle `-mabi=quadword-atomics` in future?
> 2: on what condition, we can start to remove below TODOs:
> ```
> bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
> // TODO: 16-byte atomic type support for AIX is in progress;
> }
> ```
> 
> ```
> PPC64TargetInfo::setMaxAtomicWidth() {
> // TODO: We should allow AIX to inline quadword atomics in the future.
> }
> ```
1, 2 can be answered together. After we ship new libatomic to users(I assume 
that that isn't in near future, since this requires AIX OS upgrade), we can 
enable quadword lock free atomics in both clang and llvm backend by default. 
Backend isn't aware of `-mabi=quadword-atomics`. This option changes layout of 
quadword atomic types(align to 16 byte), and generate atomic LLVM IR rather 
than generating libcalls in LLVM IR.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/include/clang/Driver/Options.td:3611
   HelpText<"Enable the default Altivec ABI on AIX (AIX only). Uses only 
volatile vector registers.">;
+def maix_quadword_atomics : Flag<["-"], "maix64-quadword-atomics">,
+  Group, Flags<[CC1Option]>,

shchenz wrote:
> lkail wrote:
> > shchenz wrote:
> > > amyk wrote:
> > > > Would it be better if we called this `maix64-quadword-atomics` instead? 
> > > Do we need to change the backend check below too?
> > > ```
> > > bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
> > >   // TODO: 16-byte atomic type support for AIX is in progress; we should 
> > > be able
> > >   // to inline 16-byte atomic ops on AIX too in the future.
> > >   return Subtarget.isPPC64() &&
> > >  (EnableQuadwordAtomics || 
> > > !Subtarget.getTargetTriple().isOSAIX()) &&
> > >  Subtarget.hasQuadwordAtomics();
> > > }
> > > ```
> > We don't need to change this yet. When we are compiling a quadword lock 
> > free libatomic, we use options `-mabi=quadword-atomics -mllvm 
> > -ppc-quadword-atomics` to enforce generating quadword lock-free code on AIX.
> This makes me confuse. We need to two different options to control the 
> frontend and backend behavior?
> 
> Is it the final usage? Or we will add a follow up patch to map the backend 
> one to the FE one? IMO finally we only need the driver option 
> `-mabi=quadword-atomics` to control the final code generation for 128 bit 
> atomic operations, right?
> This makes me confuse. We need to two different options to control the 
> frontend and backend behavior?

This is multi-lang support consideration. clang is not the only frontend we 
have using LLVM as backend on AIX. If other language frontend generates `store 
atomic i128, ...`, the backend is supposed to generate libcalls into libatomic 
currently.

> Is it the final usage?
No. We finally want to achieve `-mabi=quadword-atomics` by default and generate 
inline atomic code for cpu above pwr7 by default(no need to take OS into 
consideration).


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/include/clang/Driver/Options.td:3611
   HelpText<"Enable the default Altivec ABI on AIX (AIX only). Uses only 
volatile vector registers.">;
+def maix_quadword_atomics : Flag<["-"], "maix64-quadword-atomics">,
+  Group, Flags<[CC1Option]>,

shchenz wrote:
> amyk wrote:
> > Would it be better if we called this `maix64-quadword-atomics` instead? 
> Do we need to change the backend check below too?
> ```
> bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
>   // TODO: 16-byte atomic type support for AIX is in progress; we should be 
> able
>   // to inline 16-byte atomic ops on AIX too in the future.
>   return Subtarget.isPPC64() &&
>  (EnableQuadwordAtomics || !Subtarget.getTargetTriple().isOSAIX()) &&
>  Subtarget.hasQuadwordAtomics();
> }
> ```
We don't need to change this yet. When we are compiling a quadword lock free 
libatomic, we use options `-mabi=quadword-atomics -mllvm -ppc-quadword-atomics` 
to enforce generating quadword lock-free code on AIX.



Comment at: clang/lib/Basic/Targets/PPC.cpp:854
+  HasQuadwordAtomics)
+MaxAtomicInlineWidth = 128;
 }

shchenz wrote:
> Can we set `MaxAtomicInlineWidth` in `PPC64TargetInfo::setMaxAtomicWidth()`? 
> There is a `TODO` there
The `TODO` marks our roadmap towards enabling quardword lock free atomics on 
AIX too. Putting adjustment here is implementation reason: we don't context of 
`LanguageOptions` in `PPC64TargetInfo::PPC64TargetInfo`.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

> Can we use the feature bit FeatureQuadwordAtomic to decide whether QuadAtomic 
> is supported or not on AIX? Like what we do for Linux.

`FeatureQuadwordAtomic` is for cpu level control, while 
`-mabi=quadword-atomics` is for ABI level. AIX running on pwr8+ also features 
`FeatureQuadwordAtomic`, but in the case described in the patch summary, 
sometimes we can't enable quadword lock free atomics on AIX by default, so that 
clang generate libcalls into libatomic rather than inlining lock free 
operations. libatomic has the final decision to use lock-free version or not.

> The reason we need this option is: we may need to compile a lock free 
> libatomic on a Power7 or below target?

We need to compile a quadword lock free libatomic for CPUs above pwr8.

> If so, do we have similar issue on Linux? Thanks.

On Linux, `clang` is linking against GNU's libatomic by default, that depends 
on GNU libatomic's behaviour.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Gentle ping.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Ping.


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[PATCH] D128652: [PowerPC] Finished kill_canary implementation and debugging

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Summary should be updated as @nemanjai has said.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 441293.
lkail added a comment.

Option name changed to `-mabi=quadword-atomics` as nemanja suggested.


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Files:
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Driver/aix-quadword-atomics-abi.c
  clang/test/Driver/ppc-unsupported.c
  clang/test/Sema/atomic-ops.c

Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -10,6 +10,12 @@
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
 // RUN:   -target-cpu pwr8 -DPPC64_PWR8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -target-cpu pwr8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -mabi=quadword-atomics -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/Driver/ppc-unsupported.c
===
--- clang/test/Driver/ppc-unsupported.c
+++ clang/test/Driver/ppc-unsupported.c
@@ -7,4 +7,14 @@
 // RUN:   -c %s 2>&1 | FileCheck %s
 // RUN: not %clang -target powerpc64le-unknown-linux -msvr4-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-freebsd -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-linux -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-unknown -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-aix -mabi=quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
 // CHECK: unsupported option
Index: clang/test/Driver/aix-quadword-atomics-abi.c
===
--- /dev/null
+++ clang/test/Driver/aix-quadword-atomics-abi.c
@@ -0,0 +1,11 @@
+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc-unknown-aix -mabi=quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-TARGET %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -mabi=quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck %s --check-prefix=CHECK-QUADWORD-ATOMICS
+//
+// CHECK-UNSUPPORTED-TARGET: unsupported option '-mabi=quadword-atomics' for target 'powerpc-unknown-aix'
+// CHECK-NOT: "-mabi=quadword-atomics"
+// CHECK-QUADWORD-ATOMICS: "-cc1"
+// CHECK-QUADWORD-ATOMICS-SAME: "-mabi=quadword-atomics"
Index: clang/test/CodeGen/PowerPC/quadword-atomics.c
===
--- clang/test/CodeGen/PowerPC/quadword-atomics.c
+++ clang/test/CodeGen/PowerPC/quadword-atomics.c
@@ -1,9 +1,15 @@
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
-// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-QUADWORD-ATOMICS
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
 // RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
 // RUN:   -target-cpu pwr7 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -mabi=quadword-atomics -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s \
+// RUN:   --check-prefix=PPC64-QUADWORD-ATOMICS
+
 
 typedef struct {
   char x[16];
@@ -13,8 +19,8 @@
 
 typedef __int128_t int128_t;
 
-// PPC64-PWR8-LABEL: @test_load(
-// PPC64-PWR8:[[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_load(
+// PPC64-QUADWORD-ATOMICS:[[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
 //
 // PPC64-LABEL: @test_load(
 // PPC

[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

> Is there any precedent for options that start with -maix or -m for any 
> other OS?

There is `-maix-struct-return`.

> Is quadword the best word to use? There is no type information and this is 
> restricted to integers. Would something like -maix-i128-atomics be a better 
> name?

'quadword' is used in ISA manual, so I follow it. Not merely `i128`, some 
struct types are also included, like

  struct Q {
char c[16];
  };



> Since this is kind of an ABI-related decision, would it make sense (and would 
> it be possible) to make this a further suboption to the -mabi option?

This makes sense. I'll try this solution.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 440860.
lkail added a comment.

Address comments.


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Files:
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Driver/aix-quadword-atomics-abi.c
  clang/test/Driver/ppc-unsupported.c
  clang/test/Sema/atomic-ops.c

Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -10,6 +10,12 @@
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
 // RUN:   -target-cpu pwr8 -DPPC64_PWR8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -target-cpu pwr8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -maix64-quadword-atomics -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/Driver/ppc-unsupported.c
===
--- clang/test/Driver/ppc-unsupported.c
+++ clang/test/Driver/ppc-unsupported.c
@@ -7,4 +7,14 @@
 // RUN:   -c %s 2>&1 | FileCheck %s
 // RUN: not %clang -target powerpc64le-unknown-linux -msvr4-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-freebsd -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-unknown -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-aix -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
 // CHECK: unsupported option
Index: clang/test/Driver/aix-quadword-atomics-abi.c
===
--- /dev/null
+++ clang/test/Driver/aix-quadword-atomics-abi.c
@@ -0,0 +1,11 @@
+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc-unknown-aix -maix64-quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-TARGET %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -maix64-quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck %s --check-prefix=CHECK-QUADWORD-ATOMICS
+//
+// CHECK-UNSUPPORTED-TARGET: unsupported option '-maix64-quadword-atomics' for target 'powerpc-unknown-aix'
+// CHECK-NOT: "-maix64-quadword-atomics"
+// CHECK-QUADWORD-ATOMICS: "-cc1"
+// CHECK-QUADWORD-ATOMICS-SAME: "-maix64-quadword-atomics"
Index: clang/test/CodeGen/PowerPC/quadword-atomics.c
===
--- clang/test/CodeGen/PowerPC/quadword-atomics.c
+++ clang/test/CodeGen/PowerPC/quadword-atomics.c
@@ -1,9 +1,15 @@
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
-// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-QUADWORD-ATOMICS
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
 // RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
 // RUN:   -target-cpu pwr7 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -maix64-quadword-atomics -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s \
+// RUN:   --check-prefix=PPC64-QUADWORD-ATOMICS
+
 
 typedef struct {
   char x[16];
@@ -13,8 +19,8 @@
 
 typedef __int128_t int128_t;
 
-// PPC64-PWR8-LABEL: @test_load(
-// PPC64-PWR8:[[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
+// PPC64-QUADWORD-ATOMICS-LABEL: @test_load(
+// PPC64-QUADWORD-ATOMICS:[[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
 //
 // PPC64-LABEL: @test_load(
 // PPC64:call void @__atomic_l

[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/test/Driver/ppc-unsupported.c:12
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s

amyk wrote:
> amyk wrote:
> > Should we have a big endian Linux check, too?
> Oh, sorry. I noticed there wasn't `powerpc64-unknown-linux` but I realized I 
> think `powerpc64-unknown-freebsd` is supposed to be the big endian 64-bit 
> Linux check, right?
Added OS check is following lines above. I'm ok to add 
`powerpc64-unknown-linux` too. Thanks for pointing it out.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Gentle ping.


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[PATCH] D127189: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: hubert.reinterpretcast, cebowleratibm, xingxue, PowerPC.
Herald added subscribers: kbarton, nemanjai.
Herald added a project: All.
lkail requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

We are supporting quadword lock free atomics on AIX. For the situation that 
users on AIX are using a libatomic that is lock-based for quadword types, we 
can't enable quadword lock free atomics by default on AIX in case user's new 
code and legacy code access the same shared atomic quadword variable, we can't 
guarentee atomicity. So we need an option to enable quadword lock free atomics 
on AIX, thus we can build a quadword lock-free libatomic for users to make the 
transition smooth.


Repository:
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https://reviews.llvm.org/D127189

Files:
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Driver/aix-quadword-atomics-abi.c
  clang/test/Driver/ppc-unsupported.c
  clang/test/Sema/atomic-ops.c

Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -10,6 +10,12 @@
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
 // RUN:   -target-cpu pwr8 -DPPC64_PWR8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -target-cpu pwr8
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-unknown-aix -std=c11 \
+// RUN:   -maix64-quadword-atomics -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/Driver/ppc-unsupported.c
===
--- clang/test/Driver/ppc-unsupported.c
+++ clang/test/Driver/ppc-unsupported.c
@@ -7,4 +7,12 @@
 // RUN:   -c %s 2>&1 | FileCheck %s
 // RUN: not %clang -target powerpc64le-unknown-linux -msvr4-struct-return \
 // RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64-unknown-freebsd -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc64le-unknown-linux -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-unknown -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
+// RUN: not %clang -target powerpc-unknown-aix -maix64-quadword-atomics \
+// RUN:   -c %s 2>&1 | FileCheck %s
 // CHECK: unsupported option
Index: clang/test/Driver/aix-quadword-atomics-abi.c
===
--- /dev/null
+++ clang/test/Driver/aix-quadword-atomics-abi.c
@@ -0,0 +1,11 @@
+// RUN:  %clang -### -target powerpc-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -S %s 2>&1 | FileCheck %s
+// RUN:  %clang -### -target powerpc-unknown-aix -maix64-quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck --check-prefix=CHECK-UNSUPPORTED-TARGET %s
+// RUN:  %clang -### -target powerpc64-unknown-aix -maix64-quadword-atomics -S \
+// RUN:%s 2>&1 | FileCheck %s --check-prefix=CHECK-QUADWORD-ATOMICS
+//
+// CHECK-UNSUPPORTED-TARGET: unsupported option '-maix64-quadword-atomics' for target 'powerpc-unknown-aix'
+// CHECK-NOT: "-maix64-quadword-atomics"
+// CHECK-QUADWORD-ATOMICS: "-cc1"
+// CHECK-QUADWORD-ATOMICS-SAME: "-maix64-quadword-atomics"
Index: clang/test/CodeGen/PowerPC/quadword-atomics.c
===
--- clang/test/CodeGen/PowerPC/quadword-atomics.c
+++ clang/test/CodeGen/PowerPC/quadword-atomics.c
@@ -1,9 +1,15 @@
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
-// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-QUADWORD-ATOMICS
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
 // RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
 // RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
 // RUN:   -target-cpu pwr7 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -no-opaque-pointers -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -maix64-quadword-atomics -t

[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG549e118e93c6: [PowerPC] Support 16-byte lock free atomics on 
pwr8 and up (authored by lkail).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

Index: llvm/test/CodeGen/PowerPC/atomics-i128.ll
===
--- llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -5,6 +5,22 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
 ; RUN:   -ppc-asm-full-reg-names -ppc-quadword-atomics \
 ; RUN:   -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=AIX64-PWR8 %s
+
+; On 32-bit PPC platform, 16-byte lock free atomic instructions are not available,
+; it's expected not to generate inlined lock-free code on such platforms, even arch level
+; is pwr8+ and `-ppc-quadword-atomics` is on.
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
+; RUN:   -ppc-quadword-atomics -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
 
 
 define i128 @swap(i128* %a, i128 %x) {
@@ -39,6 +55,62 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: swap:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB0_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:mr r9, r4
+; LE-PWR8-NEXT:mr r8, r5
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB0_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: swap:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
+;
+; PPC-PWR8-LABEL: swap:
+; PPC-PWR8:   # %bb.0: # %entry
+; PPC-PWR8-NEXT:mflr r0
+; PPC-PWR8-NEXT:stw r0, 4(r1)
+; PPC-PWR8-NEXT:stwu r1, -48(r1)
+; PPC-PWR8-NEXT:.cfi_def_cfa_offset 48
+; PPC-PWR8-NEXT:.cfi_offset lr, 4
+; PPC-PWR8-NEXT:mr r4, r3
+; PPC-PWR8-NEXT:stw r7, 40(r1)
+; PPC-PWR8-NEXT:stw r6, 36(r1)
+; PPC-PWR8-NEXT:addi r6, r1, 16
+; PPC-PWR8-NEXT:li r3, 16
+; PPC-PWR8-NEXT:li r7, 5
+; PPC-PWR8-NEXT:stw r5, 32(r1)
+; PPC-PWR8-NEXT:addi r5, r1, 32
+; PPC-PWR8-NEXT:stw r8, 44(r1)
+; PPC-PWR8-NEXT:bl __atomic_exchange
+; PPC-PWR8-NEXT:lwz r6, 28(r1)
+; PPC-PWR8-NEXT:lwz r5, 24(r1)
+; PPC-PWR8-NEXT:lwz r4, 20(r1)
+; PPC-PWR8-NEXT:lwz r3, 16(r1)
+; PPC-PWR8-NEXT:lwz r0, 52(r1)
+; PPC-PWR8-NEXT:addi r1, r1, 48
+; PPC-PWR8-NEXT:mtlr r0
+; PPC-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw xchg i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -76,6 +148,109 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: add:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB1_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:addc r9, r4, r7
+; LE-PWR8-NEXT:adde r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB1_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: add:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+;

[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 421385.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

Index: llvm/test/CodeGen/PowerPC/atomics-i128.ll
===
--- llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -5,6 +5,22 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
 ; RUN:   -ppc-asm-full-reg-names -ppc-quadword-atomics \
 ; RUN:   -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=AIX64-PWR8 %s
+
+; On 32-bit PPC platform, 16-byte lock free atomic instructions are not available,
+; it's expected not to generate inlined lock-free code on such platforms, even arch level
+; is pwr8+ and `-ppc-quadword-atomics` is on.
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
+; RUN:   -ppc-quadword-atomics -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
 
 
 define i128 @swap(i128* %a, i128 %x) {
@@ -39,6 +55,62 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: swap:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB0_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:mr r9, r4
+; LE-PWR8-NEXT:mr r8, r5
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB0_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: swap:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
+;
+; PPC-PWR8-LABEL: swap:
+; PPC-PWR8:   # %bb.0: # %entry
+; PPC-PWR8-NEXT:mflr r0
+; PPC-PWR8-NEXT:stw r0, 4(r1)
+; PPC-PWR8-NEXT:stwu r1, -48(r1)
+; PPC-PWR8-NEXT:.cfi_def_cfa_offset 48
+; PPC-PWR8-NEXT:.cfi_offset lr, 4
+; PPC-PWR8-NEXT:mr r4, r3
+; PPC-PWR8-NEXT:stw r7, 40(r1)
+; PPC-PWR8-NEXT:stw r6, 36(r1)
+; PPC-PWR8-NEXT:addi r6, r1, 16
+; PPC-PWR8-NEXT:li r3, 16
+; PPC-PWR8-NEXT:li r7, 5
+; PPC-PWR8-NEXT:stw r5, 32(r1)
+; PPC-PWR8-NEXT:addi r5, r1, 32
+; PPC-PWR8-NEXT:stw r8, 44(r1)
+; PPC-PWR8-NEXT:bl __atomic_exchange
+; PPC-PWR8-NEXT:lwz r6, 28(r1)
+; PPC-PWR8-NEXT:lwz r5, 24(r1)
+; PPC-PWR8-NEXT:lwz r4, 20(r1)
+; PPC-PWR8-NEXT:lwz r3, 16(r1)
+; PPC-PWR8-NEXT:lwz r0, 52(r1)
+; PPC-PWR8-NEXT:addi r1, r1, 48
+; PPC-PWR8-NEXT:mtlr r0
+; PPC-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw xchg i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -76,6 +148,109 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: add:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB1_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:addc r9, r4, r7
+; LE-PWR8-NEXT:adde r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB1_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: add:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_fetch_and_add_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8

[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 421384.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

Index: llvm/test/CodeGen/PowerPC/atomics-i128.ll
===
--- llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -5,6 +5,22 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
 ; RUN:   -ppc-asm-full-reg-names -ppc-quadword-atomics \
 ; RUN:   -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=AIX64-PWR8 %s
+
+; On 32-bit PPC platform, 16-byte lock free atomic instructions are not available,
+; it's expected not to generate inlined lock-free code on such platforms, even arch level
+; is pwr8+ and `-ppc-quadword-atomics` is on.
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
+; RUN:   -ppc-quadword-atomics -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
 
 
 define i128 @swap(i128* %a, i128 %x) {
@@ -39,6 +55,62 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: swap:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB0_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:mr r9, r4
+; LE-PWR8-NEXT:mr r8, r5
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB0_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: swap:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
+;
+; PPC-PWR8-LABEL: swap:
+; PPC-PWR8:   # %bb.0: # %entry
+; PPC-PWR8-NEXT:mflr r0
+; PPC-PWR8-NEXT:stw r0, 4(r1)
+; PPC-PWR8-NEXT:stwu r1, -48(r1)
+; PPC-PWR8-NEXT:.cfi_def_cfa_offset 48
+; PPC-PWR8-NEXT:.cfi_offset lr, 4
+; PPC-PWR8-NEXT:mr r4, r3
+; PPC-PWR8-NEXT:stw r7, 40(r1)
+; PPC-PWR8-NEXT:stw r6, 36(r1)
+; PPC-PWR8-NEXT:addi r6, r1, 16
+; PPC-PWR8-NEXT:li r3, 16
+; PPC-PWR8-NEXT:li r7, 5
+; PPC-PWR8-NEXT:stw r5, 32(r1)
+; PPC-PWR8-NEXT:addi r5, r1, 32
+; PPC-PWR8-NEXT:stw r8, 44(r1)
+; PPC-PWR8-NEXT:bl __atomic_exchange
+; PPC-PWR8-NEXT:lwz r6, 28(r1)
+; PPC-PWR8-NEXT:lwz r5, 24(r1)
+; PPC-PWR8-NEXT:lwz r4, 20(r1)
+; PPC-PWR8-NEXT:lwz r3, 16(r1)
+; PPC-PWR8-NEXT:lwz r0, 52(r1)
+; PPC-PWR8-NEXT:addi r1, r1, 48
+; PPC-PWR8-NEXT:mtlr r0
+; PPC-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw xchg i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -76,6 +148,109 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: add:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB1_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:addc r9, r4, r7
+; LE-PWR8-NEXT:adde r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB1_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: add:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_fetch_and_add_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8

[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 421088.
lkail added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

Index: llvm/test/CodeGen/PowerPC/atomics-i128.ll
===
--- llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -5,6 +5,22 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
 ; RUN:   -ppc-asm-full-reg-names -ppc-quadword-atomics \
 ; RUN:   -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=AIX64-PWR8 %s
+
+; On 32-bit PPC platform, 16-byte lock free atomic instructions are not available,
+; it's expected not to generate inlined lock-free code on such platforms, even arch level
+; is pwr8+ and `-ppc-quadword-atomics` is on.
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
+; RUN:   -ppc-quadword-atomics -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
 
 
 define i128 @swap(i128* %a, i128 %x) {
@@ -39,6 +55,62 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: swap:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB0_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:mr r9, r4
+; LE-PWR8-NEXT:mr r8, r5
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB0_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: swap:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
+;
+; PPC-PWR8-LABEL: swap:
+; PPC-PWR8:   # %bb.0: # %entry
+; PPC-PWR8-NEXT:mflr r0
+; PPC-PWR8-NEXT:stw r0, 4(r1)
+; PPC-PWR8-NEXT:stwu r1, -48(r1)
+; PPC-PWR8-NEXT:.cfi_def_cfa_offset 48
+; PPC-PWR8-NEXT:.cfi_offset lr, 4
+; PPC-PWR8-NEXT:mr r4, r3
+; PPC-PWR8-NEXT:stw r7, 40(r1)
+; PPC-PWR8-NEXT:stw r6, 36(r1)
+; PPC-PWR8-NEXT:addi r6, r1, 16
+; PPC-PWR8-NEXT:li r3, 16
+; PPC-PWR8-NEXT:li r7, 5
+; PPC-PWR8-NEXT:stw r5, 32(r1)
+; PPC-PWR8-NEXT:addi r5, r1, 32
+; PPC-PWR8-NEXT:stw r8, 44(r1)
+; PPC-PWR8-NEXT:bl __atomic_exchange
+; PPC-PWR8-NEXT:lwz r6, 28(r1)
+; PPC-PWR8-NEXT:lwz r5, 24(r1)
+; PPC-PWR8-NEXT:lwz r4, 20(r1)
+; PPC-PWR8-NEXT:lwz r3, 16(r1)
+; PPC-PWR8-NEXT:lwz r0, 52(r1)
+; PPC-PWR8-NEXT:addi r1, r1, 48
+; PPC-PWR8-NEXT:mtlr r0
+; PPC-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw xchg i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -76,6 +148,109 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: add:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB1_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:addc r9, r4, r7
+; LE-PWR8-NEXT:adde r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB1_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: add:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_fetch_and_add_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX6

[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/atomics-i128.ll:77
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop

hubert.reinterpretcast wrote:
> What library is this expected to provide this symbol?
As far as I know, should be none on AIX. This issue is fixed in 
https://reviews.llvm.org/D122868.


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[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.h:440
 if (Triple.isOSAIX() || Triple.isOSLinux())
   DataLayout += "-S128-v256:256:256-v512:512:512";
 resetDataLayout(DataLayout);

adalava wrote:
> I don't understand what DataLayout does mean, but I'm wondering why FreeBSD 
> doesn't append this as well.  Is it expected to be AIX() and Linux only?
As maskray has pointed out, usually using `isOSBinFormatELF` rather than 
`isOSLinux` can cover freebsd as well. This snippet of code might be beyond 
this patch, we might post another one to address this issue.


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[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 420687.
lkail added a comment.

Address comments.


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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

Index: llvm/test/CodeGen/PowerPC/atomics-i128.ll
===
--- llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -5,6 +5,18 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
 ; RUN:   -ppc-asm-full-reg-names -ppc-quadword-atomics \
 ; RUN:   -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=AIX64-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
+; RUN:   -ppc-quadword-atomics -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: | FileCheck --check-prefix=AIX32-PWR8 %s
 
 
 define i128 @swap(i128* %a, i128 %x) {
@@ -39,6 +51,62 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: swap:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB0_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:mr r9, r4
+; LE-PWR8-NEXT:mr r8, r5
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB0_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: swap:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
+;
+; AIX32-PWR8-LABEL: swap:
+; AIX32-PWR8:   # %bb.0: # %entry
+; AIX32-PWR8-NEXT:mflr r0
+; AIX32-PWR8-NEXT:stw r0, 4(r1)
+; AIX32-PWR8-NEXT:stwu r1, -48(r1)
+; AIX32-PWR8-NEXT:.cfi_def_cfa_offset 48
+; AIX32-PWR8-NEXT:.cfi_offset lr, 4
+; AIX32-PWR8-NEXT:mr r4, r3
+; AIX32-PWR8-NEXT:stw r7, 40(r1)
+; AIX32-PWR8-NEXT:stw r6, 36(r1)
+; AIX32-PWR8-NEXT:addi r6, r1, 16
+; AIX32-PWR8-NEXT:li r3, 16
+; AIX32-PWR8-NEXT:li r7, 5
+; AIX32-PWR8-NEXT:stw r5, 32(r1)
+; AIX32-PWR8-NEXT:addi r5, r1, 32
+; AIX32-PWR8-NEXT:stw r8, 44(r1)
+; AIX32-PWR8-NEXT:bl __atomic_exchange
+; AIX32-PWR8-NEXT:lwz r6, 28(r1)
+; AIX32-PWR8-NEXT:lwz r5, 24(r1)
+; AIX32-PWR8-NEXT:lwz r4, 20(r1)
+; AIX32-PWR8-NEXT:lwz r3, 16(r1)
+; AIX32-PWR8-NEXT:lwz r0, 52(r1)
+; AIX32-PWR8-NEXT:addi r1, r1, 48
+; AIX32-PWR8-NEXT:mtlr r0
+; AIX32-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw xchg i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -76,6 +144,109 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: add:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB1_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:addc r9, r4, r7
+; LE-PWR8-NEXT:adde r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB1_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: add:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_fetch_and_add_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
+;
+; AIX32-PWR8-LABEL: add:
+; AIX32-PWR8:   # %bb.0: # %entry
+; AIX32-PWR8-NE

[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

In D122377#3428533 , 
@hubert.reinterpretcast wrote:

> I am not sure that the choice of `isOSBinFormatELF` to (afaik) primarily 
> scope this change from affecting AIX (where we know the library calls are not 
> implemented to be lock-free yet) is better than alternative where the 
> condition is for little-endian mode or specifically for not AIX.

I agree with we should exclude AIX explicitly(use `!isOSAIX()` rather than 
`isOSBinFormatELF()`) for current situation where AIX's support is on progress 
as we have known. What is unknown at present is the impact on freebsd.


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[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail marked an inline comment as done.
lkail added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.h:448
+  void setMaxAtomicWidth() override {
+// For layout on ELF targets, we support up to 16 bytes.
+if (getTriple().isOSBinFormatELF())

hubert.reinterpretcast wrote:
> I believe this should be presented more as this override being implemented 
> currently only for ELF targets. The current presentation seems to imply more 
> design intent for non-ELF targets than there is consensus for.
> 
> For example:
> ```
> if (!getTriple().isOSBinFormatELF())
>   return PPCTargetInfo::setMaxAtomicWidth();
> ```
It looks a chance to adjust according to arch level to me(Considering we 
finally will make xcoff and elf targets consistent here). If you have strong 
opinion on this, I'll make a change here.



Comment at: clang/test/CodeGen/PowerPC/atomic-alignment.c:34
 
 // PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
 // PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}

hubert.reinterpretcast wrote:
> Just noting that GCC increases the alignment even for ppc32:
> ```
> typedef struct A8 { char x[8]; } A8;
> typedef struct A16 { char x[16]; } A16;
> extern char q8[_Alignof(_Atomic(A8))], q8[8]; // okay for GCC targeting ppc32
> extern char q16[_Alignof(_Atomic(A16))], q16[16]; // okay for GCC targeting 
> ppc32
> ```
> 
> Apparently, the change for i686 in GCC occurred with version 11.
> https://godbolt.org/z/fTTGoqWW1
I'll post another patch to address ppc32 issue.


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[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 419618.
lkail retitled this revision from "[PowerPC][Linux] Support 16-byte lock free 
atomics on pwr8 and up" to "[PowerPC] Support 16-byte lock free atomics on pwr8 
and up".
lkail edited the summary of this revision.
lkail added a comment.

Make 16-byte atomic type aligned to 16-byte on PPC64.


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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

Index: llvm/test/CodeGen/PowerPC/atomics-i128.ll
===
--- llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -5,6 +5,18 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
 ; RUN:   -ppc-asm-full-reg-names -ppc-quadword-atomics \
 ; RUN:   -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=AIX64-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
+; RUN:   -ppc-quadword-atomics -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: | FileCheck --check-prefix=AIX32-PWR8 %s
 
 
 define i128 @swap(i128* %a, i128 %x) {
@@ -39,6 +51,62 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: swap:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB0_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:mr r9, r4
+; LE-PWR8-NEXT:mr r8, r5
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB0_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: swap:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
+;
+; AIX32-PWR8-LABEL: swap:
+; AIX32-PWR8:   # %bb.0: # %entry
+; AIX32-PWR8-NEXT:mflr r0
+; AIX32-PWR8-NEXT:stw r0, 4(r1)
+; AIX32-PWR8-NEXT:stwu r1, -48(r1)
+; AIX32-PWR8-NEXT:.cfi_def_cfa_offset 48
+; AIX32-PWR8-NEXT:.cfi_offset lr, 4
+; AIX32-PWR8-NEXT:mr r4, r3
+; AIX32-PWR8-NEXT:stw r7, 40(r1)
+; AIX32-PWR8-NEXT:stw r6, 36(r1)
+; AIX32-PWR8-NEXT:addi r6, r1, 16
+; AIX32-PWR8-NEXT:li r3, 16
+; AIX32-PWR8-NEXT:li r7, 5
+; AIX32-PWR8-NEXT:stw r5, 32(r1)
+; AIX32-PWR8-NEXT:addi r5, r1, 32
+; AIX32-PWR8-NEXT:stw r8, 44(r1)
+; AIX32-PWR8-NEXT:bl __atomic_exchange
+; AIX32-PWR8-NEXT:lwz r6, 28(r1)
+; AIX32-PWR8-NEXT:lwz r5, 24(r1)
+; AIX32-PWR8-NEXT:lwz r4, 20(r1)
+; AIX32-PWR8-NEXT:lwz r3, 16(r1)
+; AIX32-PWR8-NEXT:lwz r0, 52(r1)
+; AIX32-PWR8-NEXT:addi r1, r1, 48
+; AIX32-PWR8-NEXT:mtlr r0
+; AIX32-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw xchg i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -76,6 +144,109 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: add:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB1_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:addc r9, r4, r7
+; LE-PWR8-NEXT:adde r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB1_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: add:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_fetch_and_add_16[PR]
+; AIX64-PWR8-NEXT:nop
+

[PATCH] D122377: [PowerPC][Linux] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 418537.
lkail added a comment.

Thanks @efriedma for pointing out. Updated guard code. Also adjust backend to 
reflect ABI change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

Index: llvm/test/CodeGen/PowerPC/atomics-i128.ll
===
--- llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -5,6 +5,15 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
 ; RUN:   -ppc-asm-full-reg-names -ppc-quadword-atomics \
 ; RUN:   -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=LE-PWR8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
+; RUN:   -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN:   --check-prefix=AIX64-PWR8 %s
 
 
 define i128 @swap(i128* %a, i128 %x) {
@@ -39,6 +48,36 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: swap:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB0_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:mr r9, r4
+; LE-PWR8-NEXT:mr r8, r5
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB0_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: swap:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_lock_test_and_set_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw xchg i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -76,6 +115,36 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: add:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB1_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:addc r9, r4, r7
+; LE-PWR8-NEXT:adde r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB1_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: add:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_fetch_and_add_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw add i128* %a, i128 %x seq_cst, align 16
   ret i128 %0
@@ -113,6 +182,36 @@
 ; PWR7-NEXT:ld r0, 16(r1)
 ; PWR7-NEXT:mtlr r0
 ; PWR7-NEXT:blr
+;
+; LE-PWR8-LABEL: sub:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:sync
+; LE-PWR8-NEXT:  .LBB2_1: # %entry
+; LE-PWR8-NEXT:#
+; LE-PWR8-NEXT:lqarx r6, 0, r3
+; LE-PWR8-NEXT:subc r9, r7, r4
+; LE-PWR8-NEXT:subfe r8, r5, r6
+; LE-PWR8-NEXT:stqcx. r8, 0, r3
+; LE-PWR8-NEXT:bne cr0, .LBB2_1
+; LE-PWR8-NEXT:  # %bb.2: # %entry
+; LE-PWR8-NEXT:lwsync
+; LE-PWR8-NEXT:mr r3, r7
+; LE-PWR8-NEXT:mr r4, r6
+; LE-PWR8-NEXT:blr
+;
+; AIX64-PWR8-LABEL: sub:
+; AIX64-PWR8:   # %bb.0: # %entry
+; AIX64-PWR8-NEXT:mflr r0
+; AIX64-PWR8-NEXT:std r0, 16(r1)
+; AIX64-PWR8-NEXT:stdu r1, -112(r1)
+; AIX64-PWR8-NEXT:sync
+; AIX64-PWR8-NEXT:bl .__sync_fetch_and_sub_16[PR]
+; AIX64-PWR8-NEXT:nop
+; AIX64-PWR8-NEXT:lwsync
+; AIX64-PWR8-NEXT:addi r1, r1, 112
+; AIX64-PWR8-NEXT:ld r0, 16(r1)
+; AIX64-PWR8-NEXT:mtlr r0
+; AIX64-PWR8-NEXT:blr
 entry:
   %0 = atomicrmw sub i128* %a,

[PATCH] D122377: [PowerPC][Linux] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Removed alter of `-ppc-quadword-atomcis` in backend to decouple from frontend.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D122377: [PowerPC][Linux] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 418142.
lkail added reviewers: dim, pkubaj.
lkail set the repository for this revision to rG LLVM Github Monorepo.
lkail added subscribers: pkubaj, dim.
lkail added a comment.

@dim  @pkubaj We are modifying layout of 16-byte atomic type on Linux to be 
consistent with GCC, I don't know if it also applies to freebsd as @MaskRay 
pointed out.
To be more specific, on Linux, for arch level supporting 16-byte lock free 
atomics, 16-byte atomic type is properly aligned.

  #include 
  
  int printf(const char *, ...);
  
  typedef struct A {
char x[16];
  } A;
  
  typedef struct B {
char q;
_Atomic(A) a;
  } B;
  
  int main(void) {
_Atomic(A) *p = 0;
printf("aligned: %d\n", __builtin_offsetof(B, a) % 16 == 0);
  #if __clang__
printf("lock free (size built-in): %d\n", 
__c11_atomic_is_lock_free(sizeof(*p)));
  #endif
printf("lock free (type query using pointer): %d\n", 
atomic_is_lock_free(p));
  }

Current clang gives

  aligned: 0
  lock free (size built-in): 1
  lock free (type query using pointer): 1

GCC gives

  aligned: 1
  lock free (type query using pointer): 1

This patch also modifies the query of `__atomic_always_lock_free(16, 0)` to 
return true for supported arch level.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Driver/ppc-quadword-atomics.c
  clang/test/Sema/atomic-ops.c

Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -9,7 +9,7 @@
 // RUN:   -target-cpu pwr7
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
-// RUN:   -target-cpu pwr8
+// RUN:   -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
@@ -47,7 +47,11 @@
 _Static_assert(__c11_atomic_is_lock_free(3), ""); // expected-error {{not an integral constant expression}}
 _Static_assert(__c11_atomic_is_lock_free(4), "");
 _Static_assert(__c11_atomic_is_lock_free(8), "");
+#ifndef PPC64_PWR8
 _Static_assert(__c11_atomic_is_lock_free(16), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(__c11_atomic_is_lock_free(16), ""); // expected-no-error
+#endif
 _Static_assert(__c11_atomic_is_lock_free(17), ""); // expected-error {{not an integral constant expression}}
 
 _Static_assert(__atomic_is_lock_free(1, 0), "");
@@ -55,15 +59,23 @@
 _Static_assert(__atomic_is_lock_free(3, 0), ""); // expected-error {{not an integral constant expression}}
 _Static_assert(__atomic_is_lock_free(4, 0), "");
 _Static_assert(__atomic_is_lock_free(8, 0), "");
+#ifndef PPC64_PWR8
 _Static_assert(__atomic_is_lock_free(16, 0), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(__atomic_is_lock_free(16, 0), ""); // expected-no-error
+#endif
 _Static_assert(__atomic_is_lock_free(17, 0), ""); // expected-error {{not an integral constant expression}}
 
 _Static_assert(atomic_is_lock_free((atomic_char*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_short*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_int*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_long*)0), "");
+#ifndef PPC64_PWR8
 // noi128-error@+1 {{__int128 is not supported on this target}}
 _Static_assert(atomic_is_lock_free((_Atomic(__int128)*)0), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(atomic_is_lock_free((_Atomic(__int128)*)0), ""); // expected-no-error
+#endif
 _Static_assert(atomic_is_lock_free(0 + (atomic_char*)0), "");
 
 char i8;
@@ -88,7 +100,11 @@
 _Static_assert(!__atomic_always_lock_free(3, 0), "");
 _Static_assert(__atomic_always_lock_free(4, 0), "");
 _Static_assert(__atomic_always_lock_free(8, 0), "");
+#ifndef PPC64_PWR8
 _Static_assert(!__atomic_always_lock_free(16, 0), "");
+#else
+_Static_assert(__atomic_always_lock_free(16, 0), "");
+#endif
 _Static_assert(!__atomic_always_lock_free(17, 0), "");
 
 _Static_assert(__atomic_always_lock_free(1, incomplete), "");
Index: clang/test/Driver/ppc-quadword-atomics.c
===
--- /dev/null
+++ clang/test/Driver/ppc-quadword-atomics.c
@@ -0,0 +1,17 @@
+// RUN: %clang -### -target powerpc-unknown-unknown -S %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=NO-QUADWORD-ATOMICS
+// RUN: %clang -### -target powerpc64-unknown-aix -S %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=NO-QUADWORD-ATOMICS
+// RUN: %clang -### -target powerpc64-unknown-unknown -S %s 2>&1 | \
+// RUN:   FileCheck %s
+// RUN: %clang -### -target powerpc64le-unknown-unknown -S %s 2>&1

[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

[Kai Luo via Phabricator via cfe-commits]

lkail abandoned this revision.
lkail added a comment.
Herald added a project: All.

Most are covered by https://reviews.llvm.org/D122377 already.


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[PATCH] D122377: [PowerPC][Linux] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 417868.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -123,7 +123,7 @@
 
 static cl::opt EnableQuadwordAtomics(
 "ppc-quadword-atomics",
-cl::desc("enable quadword lock-free atomic operations"), cl::init(false),
+cl::desc("enable quadword lock-free atomic operations"), cl::init(true),
 cl::Hidden);
 
 static cl::opt
Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -9,7 +9,7 @@
 // RUN:   -target-cpu pwr7
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
-// RUN:   -target-cpu pwr8
+// RUN:   -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
@@ -47,7 +47,11 @@
 _Static_assert(__c11_atomic_is_lock_free(3), ""); // expected-error {{not an integral constant expression}}
 _Static_assert(__c11_atomic_is_lock_free(4), "");
 _Static_assert(__c11_atomic_is_lock_free(8), "");
+#ifndef PPC64_PWR8
 _Static_assert(__c11_atomic_is_lock_free(16), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(__c11_atomic_is_lock_free(16), ""); // expected-no-error
+#endif
 _Static_assert(__c11_atomic_is_lock_free(17), ""); // expected-error {{not an integral constant expression}}
 
 _Static_assert(__atomic_is_lock_free(1, 0), "");
@@ -55,15 +59,23 @@
 _Static_assert(__atomic_is_lock_free(3, 0), ""); // expected-error {{not an integral constant expression}}
 _Static_assert(__atomic_is_lock_free(4, 0), "");
 _Static_assert(__atomic_is_lock_free(8, 0), "");
+#ifndef PPC64_PWR8
 _Static_assert(__atomic_is_lock_free(16, 0), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(__atomic_is_lock_free(16, 0), ""); // expected-no-error
+#endif
 _Static_assert(__atomic_is_lock_free(17, 0), ""); // expected-error {{not an integral constant expression}}
 
 _Static_assert(atomic_is_lock_free((atomic_char*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_short*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_int*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_long*)0), "");
+#ifndef PPC64_PWR8
 // noi128-error@+1 {{__int128 is not supported on this target}}
 _Static_assert(atomic_is_lock_free((_Atomic(__int128)*)0), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(atomic_is_lock_free((_Atomic(__int128)*)0), ""); // expected-no-error
+#endif
 _Static_assert(atomic_is_lock_free(0 + (atomic_char*)0), "");
 
 char i8;
@@ -88,7 +100,11 @@
 _Static_assert(!__atomic_always_lock_free(3, 0), "");
 _Static_assert(__atomic_always_lock_free(4, 0), "");
 _Static_assert(__atomic_always_lock_free(8, 0), "");
+#ifndef PPC64_PWR8
 _Static_assert(!__atomic_always_lock_free(16, 0), "");
+#else
+_Static_assert(__atomic_always_lock_free(16, 0), "");
+#endif
 _Static_assert(!__atomic_always_lock_free(17, 0), "");
 
 _Static_assert(__atomic_always_lock_free(1, incomplete), "");
Index: clang/test/CodeGen/PowerPC/quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/quadword-atomics.c
@@ -0,0 +1,90 @@
+// RUN: %clang_cc1 -verify -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN: %clang_cc1 -verify -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
+// RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+
+typedef struct {
+  char x[16];
+} Q;
+
+typedef _Atomic(Q) AtomicQ;
+
+typedef __int128_t int128_t;
+
+// PPC64-PWR8-LABEL: @test_load(
+// PPC64-PWR8:[[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
+//
+// PPC64-LABEL: @test_load(
+// PPC64:call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP3:%.*]], i8* noundef [[TMP4:%.*]], i32 noundef signext 2)
+//
+Q test_load(AtomicQ *ptr) {
+  // expected-no-diagnostics
+  return __c11_atomic_load(ptr, __ATOMIC_ACQUIRE);
+}
+
+// PPC64-PWR8-LABEL: @test_store(
+// PPC64-PWR8:store atomic i128 [[TMP6:%.*]], i128* [[TMP4:%.*]] release, align 16
+//
+// PPC64-LABEL: @test_store(
+// PPC64:call void @__atomic_store(i64 noundef 16, i8* noundef [[TMP6:%.*]], i8* noundef [[TMP7:%.*]], i32 noundef signext 3)
+//
+void test_store(Q val, AtomicQ *ptr) {
+  // expected-no-diagnostics
+  __c11_

[PATCH] D122377: [PowerPC][Linux] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: hubert.reinterpretcast, jsji, xingxue, PowerPC.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
Herald added a project: All.
lkail requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Enable clang of Linux on POWER supports 16-byte lock free atomics on power8 and 
up, so that clang can be consistent with GCC of Linux on POWER.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122377

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/CodeGen/PowerPC/quadword-atomics.c
  clang/test/Sema/atomic-ops.c
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -123,7 +123,7 @@
 
 static cl::opt EnableQuadwordAtomics(
 "ppc-quadword-atomics",
-cl::desc("enable quadword lock-free atomic operations"), cl::init(false),
+cl::desc("enable quadword lock-free atomic operations"), cl::init(true),
 cl::Hidden);
 
 static cl::opt
Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -9,7 +9,7 @@
 // RUN:   -target-cpu pwr7
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
-// RUN:   -target-cpu pwr8
+// RUN:   -target-cpu pwr8 -DPPC64_PWR8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
@@ -47,7 +47,11 @@
 _Static_assert(__c11_atomic_is_lock_free(3), ""); // expected-error {{not an integral constant expression}}
 _Static_assert(__c11_atomic_is_lock_free(4), "");
 _Static_assert(__c11_atomic_is_lock_free(8), "");
+#ifndef PPC64_PWR8
 _Static_assert(__c11_atomic_is_lock_free(16), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(__c11_atomic_is_lock_free(16), ""); // expected-no-error
+#endif
 _Static_assert(__c11_atomic_is_lock_free(17), ""); // expected-error {{not an integral constant expression}}
 
 _Static_assert(__atomic_is_lock_free(1, 0), "");
@@ -55,15 +59,23 @@
 _Static_assert(__atomic_is_lock_free(3, 0), ""); // expected-error {{not an integral constant expression}}
 _Static_assert(__atomic_is_lock_free(4, 0), "");
 _Static_assert(__atomic_is_lock_free(8, 0), "");
+#ifndef PPC64_PWR8
 _Static_assert(__atomic_is_lock_free(16, 0), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(__atomic_is_lock_free(16, 0), ""); // expected-no-error
+#endif
 _Static_assert(__atomic_is_lock_free(17, 0), ""); // expected-error {{not an integral constant expression}}
 
 _Static_assert(atomic_is_lock_free((atomic_char*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_short*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_int*)0), "");
 _Static_assert(atomic_is_lock_free((atomic_long*)0), "");
+#ifndef PPC64_PWR8
 // noi128-error@+1 {{__int128 is not supported on this target}}
 _Static_assert(atomic_is_lock_free((_Atomic(__int128)*)0), ""); // expected-error {{not an integral constant expression}}
+#else
+_Static_assert(atomic_is_lock_free((_Atomic(__int128)*)0), ""); // expected-no-error
+#endif
 _Static_assert(atomic_is_lock_free(0 + (atomic_char*)0), "");
 
 char i8;
@@ -88,7 +100,11 @@
 _Static_assert(!__atomic_always_lock_free(3, 0), "");
 _Static_assert(__atomic_always_lock_free(4, 0), "");
 _Static_assert(__atomic_always_lock_free(8, 0), "");
+#ifndef PPC64_PWR8
 _Static_assert(!__atomic_always_lock_free(16, 0), "");
+#else
+_Static_assert(__atomic_always_lock_free(16, 0), "");
+#endif
 _Static_assert(!__atomic_always_lock_free(17, 0), "");
 
 _Static_assert(__atomic_always_lock_free(1, incomplete), "");
Index: clang/test/CodeGen/PowerPC/quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/quadword-atomics.c
@@ -0,0 +1,91 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -verify -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN: %clang_cc1 -verify -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
+// RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+
+typedef struct {
+  char x[16];
+} Q;
+
+typedef _Atomic(Q) AtomicQ;
+
+typedef __int128_t int128_t;
+
+// PPC64-PWR8-LABEL: @test_load(
+// PPC64-PWR8:[[TMP3:%.*]] = load atomic i128, i128* [[TMP1:%.*]] acquire, align 16
+//
+// PPC64-LABEL: @test_load(
+// PPC64:call void @__atomic_load(i64 noundef 16, i8* noundef [[TMP3:%.*]], i8* noundef [[TMP4:%.*]], i32 noundef signext 2)
+//
+Q test_l

[PATCH] D121441: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9247145fbae7: [PowerPC][NFC] Add atomic alignments and ops 
tests for powerpc (authored by lkail).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121441/new/

https://reviews.llvm.org/D121441

Files:
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/Sema/atomic-ops.c


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,12 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr7
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -verify -triple powerpc-unknown-unknown -emit-llvm -o - %s 
| \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - 
%s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c; // expected-no-diagnostics
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s; // expected-no-diagnostics
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i; // expected-no-diagnostics
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l; // expected-no-diagnostics
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll; // expected-no-diagnostics
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o; // expected-no-diagnostics
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q; // expected-no-diagnostics


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,12 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr7
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -verify -triple powerpc-unknown-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c; // expected-no-diagnostics
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s; // expected-no-diagnostics
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i; // expected-no-diagnostics
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l; // expected-no-diagnostics
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll; // expected-no-diagnostics
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o; // expected-no-diagnostics
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q; // expected-no-diagnostics
___
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[PATCH] D121441: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/test/CodeGen/PowerPC/atomic-alignment.c:1
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -verify -triple powerpc-unkonwn-unknown -emit-llvm -o - %s 
| \

hubert.reinterpretcast wrote:
> hubert.reinterpretcast wrote:
> > I am not sure about having a `CodeGen` test for this when a `-fsyntax-only` 
> > `Layout` test would do. I believe that also removes the need for 
> > `powerpc-registered-target`.
> I will note that there is a concept of "preferred alignment" or "complete 
> object alignment" that may differ from "required alignment". A `CodeGen` test 
> like this can miss issues if the "required alignment" is wrong but the 
> "preferred alignment" or "complete object alignment" matches what is expected.
That's a good point. However currently, I haven't found any tests in 
`test/Sema` performing such check and I have't figure out a way to add such 
check. Maybe checking `__alignof__() % (expected_align) == 0` is more practical.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D121441: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 415684.
lkail added a comment.

Fix typo; Add `pwr7` and `pwr8` as `-target-cpu`.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/Sema/atomic-ops.c


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,12 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr7
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -verify -triple powerpc-unknown-unknown -emit-llvm -o - %s 
| \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - 
%s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c; // expected-no-diagnostics
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s; // expected-no-diagnostics
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i; // expected-no-diagnostics
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l; // expected-no-diagnostics
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll; // expected-no-diagnostics
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o; // expected-no-diagnostics
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q; // expected-no-diagnostics


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,12 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr7
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -verify -triple powerpc-unknown-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c; // expected-no-diagnostics
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s; // expected-no-diagnostics
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i; // expected-no-diagnostics
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l; // expected-no-diagnostics
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll; // expected-no-diagnostics
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o; // expected-no-diagnostics
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q; // expected-no-diagnostics
___
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[PATCH] D121441: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 414583.
lkail added a comment.

Add `-verify`.


Repository:
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Files:
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/Sema/atomic-ops.c


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -verify -triple powerpc-unkonwn-unknown -emit-llvm -o - %s 
| \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unkonwn-linux -emit-llvm -o - 
%s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c; // expected-no-diagnostics
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s; // expected-no-diagnostics
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i; // expected-no-diagnostics
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l; // expected-no-diagnostics
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll; // expected-no-diagnostics
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o; // expected-no-diagnostics
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q; // expected-no-diagnostics


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -verify -triple powerpc-unkonwn-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unkonwn-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c; // expected-no-diagnostics
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s; // expected-no-diagnostics
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i; // expected-no-diagnostics
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l; // expected-no-diagnostics
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll; // expected-no-diagnostics
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o; // expected-no-diagnostics
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q; // expected-no-diagnostics
___
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[PATCH] D121441: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 414575.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121441/new/

https://reviews.llvm.org/D121441

Files:
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/Sema/atomic-ops.c


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unkonwn-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -triple powerpc64le-unkonwn-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c;
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s;
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i;
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l;
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll;
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o;
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q;


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unkonwn-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -triple powerpc64le-unkonwn-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c;
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s;
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i;
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l;
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll;
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o;
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q;
___
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[PATCH] D121441: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 414574.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121441/new/

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Files:
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/Sema/atomic-ops.c


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unkonwn-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -triple powerpc64le-unkonwn-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c;
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s;
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i;
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l;
+
+// PPC: @ll = global i64 0, align 8
+_Atomic(long long) ll;
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o;
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q;


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unkonwn-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -triple powerpc64le-unkonwn-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c;
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s;
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i;
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l;
+
+// PPC: @ll = global i64 0, align 8
+_Atomic(long long) ll;
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o;
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q;
___
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[PATCH] D121441: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: hubert.reinterpretcast, jsji, xingxue, PowerPC.
Herald added subscribers: steven.zhang, shchenz, nemanjai.
Herald added a project: All.
lkail requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

PowerPC is lacking tests checking `_Atomic` alignment in cfe. Adding these 
tests since we're going to make change to align with gcc on Linux.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121441

Files:
  clang/test/CodeGen/PowerPC/atomic-alignment.c
  clang/test/Sema/atomic-ops.c


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -verify -triple powerpc-unkonwn-unknown -emit-llvm -o - %s 
| \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unkonwn-linux -emit-llvm -o - 
%s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1
+_Atomic(char) c;
+
+// PPC: @s = global i16 0, align 2
+_Atomic(short) s;
+
+// PPC: @i = global i32 0, align 4
+_Atomic(int) i;
+
+// PPC32: @l = global i32 0, align 4
+// PPC64: @l = global i64 0, align 8
+_Atomic(long) l;
+
+// PPC: @ll = global i64 0, align 8
+_Atomic(long long) ll;
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1
+// PPC64: @o = global %struct.O zeroinitializer, align 8
+_Atomic(O) o;
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1
+_Atomic(Q) q;


Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -4,6 +4,8 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
Index: clang/test/CodeGen/PowerPC/atomic-alignment.c
===
--- /dev/null
+++ clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,38 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -verify -triple powerpc-unkonwn-unknown -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unkonwn-linux -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unkonwn-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1
+_Atomic(char) c;
+
+// PPC: @s = global i16 0, align 2
+_Atomic(short) s;
+
+// PPC: @i = global i32 0, align 4
+_Atomic(int) i;
+
+// PPC32: @l = global i32 0, align 4
+// PPC64: @l = global i64 0, align 8
+_Atomic(long) l;
+
+// PPC: @ll = global i64 0, align 8
+_Atomic(long long) ll;
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1
+// PPC64: @o = global %struct.O zeroinitializer, align 8
+_Atomic(O) o;
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1
+_Atomic(Q) q;
___
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[PATCH] D28213: [Frontend] Correct values of ATOMIC_*_LOCK_FREE to match builtin

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Hi, is this patch ready to land?


Repository:
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[Diffusion] rGc93f93b2e3f2: Revert "Revert "Recommit "Revert "[CVP] processSwitch: Remove default case when…

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Looks a more general way should be implemented in tailduplicator to avoid 
adding quadratic edges in CFGs.


BRANCHES
  EmptyLineAfterFunctionDefinition, fix_asan, main

Users:
  junparser (Author)

https://reviews.llvm.org/rGc93f93b2e3f2

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[PATCH] D114207: [clang] fix regression deducing pack expansion arguments introduced by D110216

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Confirmed it solves our internal regressions, thanks!


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[PATCH] D113049: [AIX] Disable tests that fail because of no 64-bit XCOFF object file support

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Is there any way to filter these tests out on AIX in `lit.local.cfg`?


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[PATCH] D110216: [clang] retain type sugar in auto / template argument deduction

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

Hi we found regression in our internal tests. It compiles with clang-13.0.0 
https://godbolt.org/z/3abGrcf7o and gcc https://godbolt.org/z/K9oj3Grs1, but 
fails with clang-trunk https://godbolt.org/z/1Tehxa1x9. Is it an intended 
change? If so, do we have to document this?


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[PATCH] D113654: [AIX] Set D111860's test unsupported on AIX

[Kai Luo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG72362736c380: [AIX] Set D111860's test unsupported on 
AIX (authored by lkail).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/Modules/merge-objc-protocol-visibility.m


Index: clang/test/Modules/merge-objc-protocol-visibility.m
===
--- clang/test/Modules/merge-objc-protocol-visibility.m
+++ clang/test/Modules/merge-objc-protocol-visibility.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -aix
 // RUN: rm -rf %t
 // RUN: split-file %s %t
 // RUN: %clang_cc1 -emit-llvm -o %t/test.bc -F%t/Frameworks %t/test.m 
-Werror=objc-method-access -DHIDDEN_FIRST=1 \


Index: clang/test/Modules/merge-objc-protocol-visibility.m
===
--- clang/test/Modules/merge-objc-protocol-visibility.m
+++ clang/test/Modules/merge-objc-protocol-visibility.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -aix
 // RUN: rm -rf %t
 // RUN: split-file %s %t
 // RUN: %clang_cc1 -emit-llvm -o %t/test.bc -F%t/Frameworks %t/test.m -Werror=objc-method-access -DHIDDEN_FIRST=1 \
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[PATCH] D113654: [AIX] Set D111860's test unsupported on AIX

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: PowerPC, jsji.
lkail requested review of this revision.
Herald added a project: clang.
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https://reviews.llvm.org/D113654

Files:
  clang/test/Modules/merge-objc-protocol-visibility.m


Index: clang/test/Modules/merge-objc-protocol-visibility.m
===
--- clang/test/Modules/merge-objc-protocol-visibility.m
+++ clang/test/Modules/merge-objc-protocol-visibility.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -aix
 // RUN: rm -rf %t
 // RUN: split-file %s %t
 // RUN: %clang_cc1 -emit-llvm -o %t/test.bc -F%t/Frameworks %t/test.m 
-Werror=objc-method-access -DHIDDEN_FIRST=1 \


Index: clang/test/Modules/merge-objc-protocol-visibility.m
===
--- clang/test/Modules/merge-objc-protocol-visibility.m
+++ clang/test/Modules/merge-objc-protocol-visibility.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -aix
 // RUN: rm -rf %t
 // RUN: split-file %s %t
 // RUN: %clang_cc1 -emit-llvm -o %t/test.bc -F%t/Frameworks %t/test.m -Werror=objc-method-access -DHIDDEN_FIRST=1 \
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[PATCH] D112400: [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall

[Kai Luo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6ea2431d3f10: [clang][compiler-rt][atomics] Add 
`__c11_atomic_fetch_nand` builtin and support… (authored by lkail).

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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang/Basic/Builtins.def
  clang/lib/AST/Expr.cpp
  clang/lib/CodeGen/CGAtomic.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/atomic-implicit-seq_cst.c
  clang/test/Sema/atomic-ops.c
  compiler-rt/lib/builtins/atomic.c
  compiler-rt/test/builtins/Unit/atomic_test.c

Index: compiler-rt/test/builtins/Unit/atomic_test.c
===
--- compiler-rt/test/builtins/Unit/atomic_test.c
+++ compiler-rt/test/builtins/Unit/atomic_test.c
@@ -96,6 +96,11 @@
 uint32_t __atomic_fetch_xor_4(uint32_t *ptr, uint32_t val, int model);
 uint64_t __atomic_fetch_xor_8(uint64_t *ptr, uint64_t val, int model);
 
+uint8_t __atomic_fetch_nand_1(uint8_t *ptr, uint8_t val, int model);
+uint16_t __atomic_fetch_nand_2(uint16_t *ptr, uint16_t val, int model);
+uint32_t __atomic_fetch_nand_4(uint32_t *ptr, uint32_t val, int model);
+uint64_t __atomic_fetch_nand_8(uint64_t *ptr, uint64_t val, int model);
+
 // We conditionally test the *_16 atomic function variants based on the same
 // condition that compiler_rt (atomic.c) uses to conditionally generate them.
 // Currently atomic.c tests if __SIZEOF_INT128__ is defined (which can be the
@@ -119,6 +124,7 @@
 uint128_t __atomic_fetch_and_16(uint128_t *ptr, uint128_t val, int model);
 uint128_t __atomic_fetch_or_16(uint128_t *ptr, uint128_t val, int model);
 uint128_t __atomic_fetch_xor_16(uint128_t *ptr, uint128_t val, int model);
+uint128_t __atomic_fetch_nand_16(uint128_t *ptr, uint128_t val, int model);
 #else
 typedef uint64_t maxuint_t;
 #endif
@@ -540,6 +546,28 @@
   abort();
 #endif
 
+// Fetch nand.
+
+set_a_values(V + m);
+set_b_values(0);
+b8 = __atomic_fetch_nand_1(&a8, U8(ONES), model);
+if (b8 != U8(V + m) || a8 != U8(~((V + m) & ONES)))
+  abort();
+b16 = __atomic_fetch_nand_2(&a16, U16(ONES), model);
+if (b16 != U16(V + m) || a16 != U16(~((V + m) & ONES)))
+  abort();
+b32 = __atomic_fetch_nand_4(&a32, U32(ONES), model);
+if (b32 != U32(V + m) || a32 != U32(~((V + m) & ONES)))
+  abort();
+b64 = __atomic_fetch_nand_8(&a64, U64(ONES), model);
+if (b64 != U64(V + m) || a64 != U64(~((V + m) & ONES)))
+  abort();
+#ifdef TEST_16
+b128 = __atomic_fetch_nand_16(&a128, ONES, model);
+if (b128 != (V + m) || a128 != ~((V + m) & ONES))
+  abort();
+#endif
+
 // Check signed integer overflow behavior
 
 set_a_values(V + m);
Index: compiler-rt/lib/builtins/atomic.c
===
--- compiler-rt/lib/builtins/atomic.c
+++ compiler-rt/lib/builtins/atomic.c
@@ -336,6 +336,18 @@
 return tmp;\
   }
 
+#define ATOMIC_RMW_NAND(n, lockfree, type) \
+  type __atomic_fetch_nand_##n(type *ptr, type val, int model) {   \
+if (lockfree(ptr)) \
+  return __c11_atomic_fetch_nand((_Atomic(type) *)ptr, val, model);\
+Lock *l = lock_for_pointer(ptr);   \
+lock(l);   \
+type tmp = *ptr;   \
+*ptr = ~(tmp & val);   \
+unlock(l); \
+return tmp;\
+  }
+
 #define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW(n, lockfree, type, add, +)
 OPTIMISED_CASES
 #undef OPTIMISED_CASE
@@ -351,3 +363,6 @@
 #define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW(n, lockfree, type, xor, ^)
 OPTIMISED_CASES
 #undef OPTIMISED_CASE
+#define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW_NAND(n, lockfree, type)
+OPTIMISED_CASES
+#undef OPTIMISED_CASE
Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -362,6 +362,13 @@
   (void)__c11_atomic_fetch_xor(Ap, val, memory_order_acq_rel);
   (void)__c11_atomic_fetch_xor(Ap, val, memory_order_seq_cst);
 
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_relaxed);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_acquire);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_consume);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_release);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_acq_rel);
+  (void)

[PATCH] D112400: [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: compiler-rt/lib/builtins/atomic.c:339
 
+#define ATOMIC_RMW_NAND(n, lockfree, type) 
\
+  type __atomic_fetch_nand_##n(type *ptr, type val, int model) {   
\

jyknight wrote:
> Same as ATOMIC_RMW now, isn't it?
Not totally. The `ATOMIC_RMW` macro also accept binary op sign as its argument, 
i.e., in the form `a op b`. However, nand is `~(a & b)`.


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[PATCH] D112400: [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 382624.

Repository:
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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang/Basic/Builtins.def
  clang/lib/AST/Expr.cpp
  clang/lib/CodeGen/CGAtomic.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/atomic-implicit-seq_cst.c
  clang/test/Sema/atomic-ops.c
  compiler-rt/lib/builtins/atomic.c
  compiler-rt/test/builtins/Unit/atomic_test.c

Index: compiler-rt/test/builtins/Unit/atomic_test.c
===
--- compiler-rt/test/builtins/Unit/atomic_test.c
+++ compiler-rt/test/builtins/Unit/atomic_test.c
@@ -96,6 +96,11 @@
 uint32_t __atomic_fetch_xor_4(uint32_t *ptr, uint32_t val, int model);
 uint64_t __atomic_fetch_xor_8(uint64_t *ptr, uint64_t val, int model);
 
+uint8_t __atomic_fetch_nand_1(uint8_t *ptr, uint8_t val, int model);
+uint16_t __atomic_fetch_nand_2(uint16_t *ptr, uint16_t val, int model);
+uint32_t __atomic_fetch_nand_4(uint32_t *ptr, uint32_t val, int model);
+uint64_t __atomic_fetch_nand_8(uint64_t *ptr, uint64_t val, int model);
+
 // We conditionally test the *_16 atomic function variants based on the same
 // condition that compiler_rt (atomic.c) uses to conditionally generate them.
 // Currently atomic.c tests if __SIZEOF_INT128__ is defined (which can be the
@@ -119,6 +124,7 @@
 uint128_t __atomic_fetch_and_16(uint128_t *ptr, uint128_t val, int model);
 uint128_t __atomic_fetch_or_16(uint128_t *ptr, uint128_t val, int model);
 uint128_t __atomic_fetch_xor_16(uint128_t *ptr, uint128_t val, int model);
+uint128_t __atomic_fetch_nand_16(uint128_t *ptr, uint128_t val, int model);
 #else
 typedef uint64_t maxuint_t;
 #endif
@@ -540,6 +546,28 @@
   abort();
 #endif
 
+// Fetch nand.
+
+set_a_values(V + m);
+set_b_values(0);
+b8 = __atomic_fetch_nand_1(&a8, U8(ONES), model);
+if (b8 != U8(V + m) || a8 != U8(~((V + m) & ONES)))
+  abort();
+b16 = __atomic_fetch_nand_2(&a16, U16(ONES), model);
+if (b16 != U16(V + m) || a16 != U16(~((V + m) & ONES)))
+  abort();
+b32 = __atomic_fetch_nand_4(&a32, U32(ONES), model);
+if (b32 != U32(V + m) || a32 != U32(~((V + m) & ONES)))
+  abort();
+b64 = __atomic_fetch_nand_8(&a64, U64(ONES), model);
+if (b64 != U64(V + m) || a64 != U64(~((V + m) & ONES)))
+  abort();
+#ifdef TEST_16
+b128 = __atomic_fetch_nand_16(&a128, ONES, model);
+if (b128 != (V + m) || a128 != ~((V + m) & ONES))
+  abort();
+#endif
+
 // Check signed integer overflow behavior
 
 set_a_values(V + m);
Index: compiler-rt/lib/builtins/atomic.c
===
--- compiler-rt/lib/builtins/atomic.c
+++ compiler-rt/lib/builtins/atomic.c
@@ -336,6 +336,18 @@
 return tmp;\
   }
 
+#define ATOMIC_RMW_NAND(n, lockfree, type) \
+  type __atomic_fetch_nand_##n(type *ptr, type val, int model) {   \
+if (lockfree(ptr)) \
+  return __c11_atomic_fetch_nand((_Atomic(type) *)ptr, val, model);\
+Lock *l = lock_for_pointer(ptr);   \
+lock(l);   \
+type tmp = *ptr;   \
+*ptr = ~(tmp & val);   \
+unlock(l); \
+return tmp;\
+  }
+
 #define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW(n, lockfree, type, add, +)
 OPTIMISED_CASES
 #undef OPTIMISED_CASE
@@ -351,3 +363,6 @@
 #define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW(n, lockfree, type, xor, ^)
 OPTIMISED_CASES
 #undef OPTIMISED_CASE
+#define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW_NAND(n, lockfree, type)
+OPTIMISED_CASES
+#undef OPTIMISED_CASE
Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -362,6 +362,13 @@
   (void)__c11_atomic_fetch_xor(Ap, val, memory_order_acq_rel);
   (void)__c11_atomic_fetch_xor(Ap, val, memory_order_seq_cst);
 
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_relaxed);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_acquire);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_consume);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_release);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_acq_rel);
+  (void)__c11_atomic_fetch_nand(Ap, val, memory_order_seq_cst);
+
   (void)__c11_atomic_fetch_min(Ap, val, memory_order_relaxed);
   (void)__c11_atomic_fetch_min(Ap, val, mem

[PATCH] D112400: [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

> The GCC builtins paint the ABI into a corner.  They accept 
> non-`_Atomic`-qualified types (the C11 spec guarantees only that these 
> operations work on `_Atomic` types).  The goal of the original C++ 
> specification was to allow implementations to use atomic operations for 
> register-sized chunks and fall back to an implementation with an inline lock 
> for larger types, so `std::atomic` would either have a single field of `T` 
> or a `std::atomic_flag` field and a `T` field, depending on the size of `T`.  
> The goal of the C11 import was to allow `_Atomic(T)` to be ABI-compatible 
> with `std::atomic`.  Implementing this requires that `_Atomic(T)` be 
> allowed to have a different representation to `T`.  GCC messed this up and 
> defined builtins that took a `T*`, not an `_Atomic(T*)`, which forced all 
> GCC-compatible ABIs to have the same representation for `T` and `_Atomic(T)`. 
>  This, in turn, meant that the atomics support library couldn't use inline 
> locks, and had to maintain a pool of locks to use for different types.  This, 
> in turn, means that `_Atomic(T)` silently fails in surprising ways in shared 
> memory, some of the time, depending on the target CPU.  This is a horrible 
> mess and I would like to ensure that we always provide builtins that allow 
> target ABIs to do the right thing, even if Linux and *BSD are trapped in a 
> broken ABI by GCC and legacy compatibility.

Good to know, thanks for your detailed explanation!


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[PATCH] D112400: [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 382618.
lkail retitled this revision from "[compiler-rt][atomics] Support 
__atomic_fetch_nand" to "[clang][compiler-rt][atomics] Add 
`__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall".
lkail edited the summary of this revision.
lkail added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add `__c11_atomic_fetch_nand` in clang; Use `__c11_atomic_fetch_nand` to 
implement lock-free `__atomic_fetch_nand` libcall; Updated 
`LanguageExtensions.rst`.


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Files:
  clang/docs/LanguageExtensions.rst
  clang/include/clang/Basic/Builtins.def
  clang/lib/AST/Expr.cpp
  clang/lib/CodeGen/CGAtomic.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/atomic-implicit-seq_cst.c
  clang/test/Sema/atomic-ops.c
  compiler-rt/lib/builtins/atomic.c
  compiler-rt/test/builtins/Unit/atomic_test.c

Index: compiler-rt/test/builtins/Unit/atomic_test.c
===
--- compiler-rt/test/builtins/Unit/atomic_test.c
+++ compiler-rt/test/builtins/Unit/atomic_test.c
@@ -96,6 +96,11 @@
 uint32_t __atomic_fetch_xor_4(uint32_t *ptr, uint32_t val, int model);
 uint64_t __atomic_fetch_xor_8(uint64_t *ptr, uint64_t val, int model);
 
+uint8_t __atomic_fetch_nand_1(uint8_t *ptr, uint8_t val, int model);
+uint16_t __atomic_fetch_nand_2(uint16_t *ptr, uint16_t val, int model);
+uint32_t __atomic_fetch_nand_4(uint32_t *ptr, uint32_t val, int model);
+uint64_t __atomic_fetch_nand_8(uint64_t *ptr, uint64_t val, int model);
+
 // We conditionally test the *_16 atomic function variants based on the same
 // condition that compiler_rt (atomic.c) uses to conditionally generate them.
 // Currently atomic.c tests if __SIZEOF_INT128__ is defined (which can be the
@@ -119,6 +124,7 @@
 uint128_t __atomic_fetch_and_16(uint128_t *ptr, uint128_t val, int model);
 uint128_t __atomic_fetch_or_16(uint128_t *ptr, uint128_t val, int model);
 uint128_t __atomic_fetch_xor_16(uint128_t *ptr, uint128_t val, int model);
+uint128_t __atomic_fetch_nand_16(uint128_t *ptr, uint128_t val, int model);
 #else
 typedef uint64_t maxuint_t;
 #endif
@@ -540,6 +546,28 @@
   abort();
 #endif
 
+// Fetch nand.
+
+set_a_values(V + m);
+set_b_values(0);
+b8 = __atomic_fetch_nand_1(&a8, U8(ONES), model);
+if (b8 != U8(V + m) || a8 != U8(~((V + m) & ONES)))
+  abort();
+b16 = __atomic_fetch_nand_2(&a16, U16(ONES), model);
+if (b16 != U16(V + m) || a16 != U16(~((V + m) & ONES)))
+  abort();
+b32 = __atomic_fetch_nand_4(&a32, U32(ONES), model);
+if (b32 != U32(V + m) || a32 != U32(~((V + m) & ONES)))
+  abort();
+b64 = __atomic_fetch_nand_8(&a64, U64(ONES), model);
+if (b64 != U64(V + m) || a64 != U64(~((V + m) & ONES)))
+  abort();
+#ifdef TEST_16
+b128 = __atomic_fetch_nand_16(&a128, ONES, model);
+if (b128 != (V + m) || a128 != ~((V + m) & ONES))
+  abort();
+#endif
+
 // Check signed integer overflow behavior
 
 set_a_values(V + m);
Index: compiler-rt/lib/builtins/atomic.c
===
--- compiler-rt/lib/builtins/atomic.c
+++ compiler-rt/lib/builtins/atomic.c
@@ -336,6 +336,18 @@
 return tmp;\
   }
 
+#define ATOMIC_RMW_NAND(n, lockfree, type) \
+  type __atomic_fetch_nand_##n(type *ptr, type val, int model) {   \
+if (lockfree(ptr)) \
+  return __c11_atomic_fetch_nand((_Atomic(type) *)ptr, val, model);\
+Lock *l = lock_for_pointer(ptr);   \
+lock(l);   \
+type tmp = *ptr;   \
+*ptr = ~(tmp & val);   \
+unlock(l); \
+return tmp;\
+  }
+
 #define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW(n, lockfree, type, add, +)
 OPTIMISED_CASES
 #undef OPTIMISED_CASE
@@ -351,3 +363,6 @@
 #define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW(n, lockfree, type, xor, ^)
 OPTIMISED_CASES
 #undef OPTIMISED_CASE
+#define OPTIMISED_CASE(n, lockfree, type) ATOMIC_RMW_NAND(n, lockfree, type)
+OPTIMISED_CASES
+#undef OPTIMISED_CASE
Index: clang/test/Sema/atomic-ops.c
===
--- clang/test/Sema/atomic-ops.c
+++ clang/test/Sema/atomic-ops.c
@@ -362,6 +362,13 @@
   (void)__c11_atomic_fetch_xor(Ap, val, memory_order_acq_rel);
   (void)__c11_atomic_fetch_xor(Ap, val, memory_order_seq_cst)

[PATCH] D111078: [AIX] Enable int128 in 64 bit mode

[Kai Luo via Phabricator via cfe-commits]

lkail accepted this revision as: lkail.
lkail added a comment.
This revision is now accepted and ready to land.

This LGTM as the start point to support int128 on AIX. We might need more 
patches involving libraries in the LLVM monorepo, we can do that progressively.


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[PATCH] D111078: [AIX] Enable int128 in 64 bit mode

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

I would like to see more aix triple added to existing tests involving ABI in 
`llvm/test/CodeGen/PowerPC`(such as ppc64-i128-abi.ll), since AIX has 
independent calling convention lowering and is different from linux.


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[PATCH] D109139: [AIX][RFC] Undefine __STDC_NO_ATOMICS__ to enable c11 atomics functionality

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: PowerPC, hubert.reinterpretcast, jsji, cebowleratibm, 
Jake-Egan.
Herald added subscribers: jfb, kbarton, nemanjai.
lkail requested review of this revision.
Herald added a project: clang.
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In https://reviews.llvm.org/D103707, `__STDC_NO_ATOMICS__` is predefined to 
indicate clang on AIX doesn't support `_Atomic` and not shipped with 
`stdatomic.h` yet. Actually `_Atomic` is already supported. For `stdatomic.h`, 
clang has implemented one in `clang/lib/Headers/stdatomic.h`. The remaining 
problem is

  void atomic_thread_fence(memory_order);
  void atomic_signal_fence(memory_order);
  _Bool atomic_flag_test_and_set(volatile atomic_flag *);
  _Bool atomic_flag_test_and_set_explicit(volatile atomic_flag *, memory_order);

are defined as macros and don't have external linkage required by C11 standard, 
since current libc of AIX doesn't have them now. So is it worthwhile to violate 
the standard a bit, but make c11's atomics functionality available to users? If 
not, we may have to wait for upgrading of AIX's libc to define above routines.


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Files:
  clang/lib/Basic/Targets/OSTargets.h
  clang/test/Preprocessor/init-ppc.c


Index: clang/test/Preprocessor/init-ppc.c
===
--- clang/test/Preprocessor/init-ppc.c
+++ clang/test/Preprocessor/init-ppc.c
@@ -755,11 +755,9 @@
 // RUN: %clang_cc1 -x c -std=c11 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC %s
 // RUN: %clang_cc1 -x c -std=gnu11 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC %s
 // RUN: %clang_cc1 -x c -std=c17 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC %s
-// PPC-AIX-STDC:#define __STDC_NO_ATOMICS__ 1
 // PPC-AIX-STDC:#define __STDC_NO_THREADS__ 1
 
 // RUN: %clang_cc1 -x c -std=c99 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC-N %s
-// PPC-AIX-STDC-N-NOT:#define __STDC_NO_ATOMICS__ 1
 // PPC-AIX-STDC-N-NOT:#define __STDC_NO_THREADS__ 1
 
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-ibm-aix7.1.0.0 
-mlong-double-64 < /dev/null | FileCheck -match-full-lines -check-prefix 
PPC-AIX-LD64 %s
Index: clang/lib/Basic/Targets/OSTargets.h
===
--- clang/lib/Basic/Targets/OSTargets.h
+++ clang/lib/Basic/Targets/OSTargets.h
@@ -679,10 +679,8 @@
 Builder.defineMacro("__TOS_AIX__");
 Builder.defineMacro("__HOS_AIX__");
 
-if (Opts.C11) {
-  Builder.defineMacro("__STDC_NO_ATOMICS__");
+if (Opts.C11)
   Builder.defineMacro("__STDC_NO_THREADS__");
-}
 
 if (Opts.EnableAIXExtendedAltivecABI)
   Builder.defineMacro("__EXTABI__");


Index: clang/test/Preprocessor/init-ppc.c
===
--- clang/test/Preprocessor/init-ppc.c
+++ clang/test/Preprocessor/init-ppc.c
@@ -755,11 +755,9 @@
 // RUN: %clang_cc1 -x c -std=c11 -E -dM -ffreestanding -triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC-AIX-STDC %s
 // RUN: %clang_cc1 -x c -std=gnu11 -E -dM -ffreestanding -triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC-AIX-STDC %s
 // RUN: %clang_cc1 -x c -std=c17 -E -dM -ffreestanding -triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC-AIX-STDC %s
-// PPC-AIX-STDC:#define __STDC_NO_ATOMICS__ 1
 // PPC-AIX-STDC:#define __STDC_NO_THREADS__ 1
 
 // RUN: %clang_cc1 -x c -std=c99 -E -dM -ffreestanding -triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC-AIX-STDC-N %s
-// PPC-AIX-STDC-N-NOT:#define __STDC_NO_ATOMICS__ 1
 // PPC-AIX-STDC-N-NOT:#define __STDC_NO_THREADS__ 1
 
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-ibm-aix7.1.0.0 -mlong-double-64 < /dev/null | FileCheck -match-full-lines -check-prefix PPC-AIX-LD64 %s
Index: clang/lib/Basic/Targets/OSTargets.h
===
--- clang/lib/Basic/Targets/OSTargets.h
+++ clang/lib/Basic/Targets/OSTargets.h
@@ -679,10 +679,8 @@
 Builder.defineMacro("__TOS_AIX__");
 Builder.defineMacro("__HOS_AIX__");
 
-if (Opts.C11) {
-  Builder.defineMacro("__STDC_NO_ATOMICS__");
+if (Opts.C11)
   Builder.defineMacro("__STDC_NO_THREADS__");
-}
 
 if (Opts.EnableAIXExtendedAltivecABI)
   Builder.defineMacro("__EXTABI__");
___
cfe-com

[PATCH] D107764: [OpenMP][OpenMPIRBuilder] Implement loop unrolling.

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

This looks has broken build if `-DBUILD_SHARED_LIBS=On` is specified.

  CMake Error: The inter-target dependency graph contains the following 
strongly connected component (cycle):
"LLVMFrontendOpenMP" of type SHARED_LIBRARY
  depends on "LLVMPasses" (weak)
"LLVMipo" of type SHARED_LIBRARY
  depends on "LLVMFrontendOpenMP" (weak)
"LLVMCoroutines" of type SHARED_LIBRARY
  depends on "LLVMipo" (weak)
"LLVMPasses" of type SHARED_LIBRARY
  depends on "LLVMCoroutines" (weak)
  depends on "LLVMipo" (weak)
  At least one of these targets is not a STATIC_LIBRARY.  Cyclic dependencies 
are allowed only among static libraries.
  CMake Generate step failed.  Build files cannot be regenerated correctly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107764/new/

https://reviews.llvm.org/D107764

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[PATCH] D107077: [PowerPC] Fix return type of XL compat CAS

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe4902e69e99d: [PowerPC] Fix return type of XL compat CAS 
(authored by lkail).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107077/new/

https://reviews.llvm.org/D107077

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cas.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -20,10 +20,11 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
-  __compare_and_swap(&a, &b, c);
+int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
+  return __compare_and_swap(&a, &b, c);
 }
 
 
@@ -41,9 +42,10 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
-  __compare_and_swaplp(&a, &b, c);
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c);
 }
 
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15808,7 +15808,7 @@
 // store.
 Value *LoadedVal = Pair.first.getScalarVal();
 Builder.CreateStore(LoadedVal, OldValAddr);
-return Pair.second;
+return Builder.CreateZExt(Pair.second, Builder.getInt32Ty());
   }
   case PPC::BI__builtin_ppc_fetch_and_add:
   case PPC::BI__builtin_ppc_fetch_and_addlp: {


Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -20,10 +20,11 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
-  __compare_and_swap(&a, &b, c);
+int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
+  return __compare_and_swap(&a, &b, c);
 }
 
 
@@ -41,9 +42,10 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
-  __compare_and_swaplp(&a, &b, c);
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c);
 }
 
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15808,7 +15808,7 @@
 // store.
 Value *LoadedVal = Pair.first.getScalarVal();
 Builder.CreateStore(LoadedVal, OldValAddr);
-return Pair.second;
+return Builder.CreateZExt(Pair.second, Builder.getInt32Ty());
   }
   case PPC::BI__builtin_ppc_fetch_and_add:
   case PPC::BI__builtin_ppc_fetch_and_addlp: {
___
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[PATCH] D107077: [PowerPC] Fix return type of XL compat CAS

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: jsji, PowerPC.
Herald added subscribers: shchenz, kbarton, nemanjai.
lkail requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

`__compare_and_swap*` should return `i32` rather than `i1`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107077

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cas.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -20,10 +20,11 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
-  __compare_and_swap(&a, &b, c);
+int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
+  return __compare_and_swap(&a, &b, c);
 }
 
 
@@ -41,9 +42,10 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
-  __compare_and_swaplp(&a, &b, c);
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c);
 }
 
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15808,7 +15808,7 @@
 // store.
 Value *LoadedVal = Pair.first.getScalarVal();
 Builder.CreateStore(LoadedVal, OldValAddr);
-return Pair.second;
+return Builder.CreateZExt(Pair.second, Builder.getInt32Ty());
   }
   case PPC::BI__builtin_ppc_fetch_and_add:
   case PPC::BI__builtin_ppc_fetch_and_addlp: {


Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -20,10 +20,11 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
-  __compare_and_swap(&a, &b, c);
+int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
+  return __compare_and_swap(&a, &b, c);
 }
 
 
@@ -41,9 +42,10 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
-  __compare_and_swaplp(&a, &b, c);
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c);
 }
 
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15808,7 +15808,7 @@
 // store.
 Value *LoadedVal = Pair.first.getScalarVal();
 Builder.CreateStore(LoadedVal, OldValAddr);
-return Pair.second;
+return Builder.CreateZExt(Pair.second, Builder.getInt32Ty());
   }
   case PPC::BI__builtin_ppc_fetch_and_add:
   case PPC::BI__builtin_ppc_fetch_and_addlp: {
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[PATCH] D106344: [PowerPC] Implement XL compatible behavior of __compare_and_swap

[Kai Luo via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe4ed93cb25ac: [PowerPC] Implement XL compatible behavior of 
__compare_and_swap (authored by lkail).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106344/new/

https://reviews.llvm.org/D106344

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
  llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll

Index: llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -enable-new-pm=1 -S -passes='default' %s -o - | FileCheck %s
+define void @test_builtin_ppc_compare_and_swaplp(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+; CHECK-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+; CHECK-NEXT:[[TMP0:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[B:%.*]], i64 [[C:%.*]] monotonic monotonic, align 8
+; CHECK-NEXT:ret void
+;
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  store i64 %a, i64* %a.addr, align 8
+  store i64 %b, i64* %b.addr, align 8
+  store i64 %c, i64* %c.addr, align 8
+  %0 = load i64, i64* %c.addr, align 8
+  %1 = load i64, i64* %b.addr, align 8
+  %2 = cmpxchg weak volatile i64* %a.addr, i64 %1, i64 %0 monotonic monotonic, align 8
+  %3 = extractvalue { i64, i1 } %2, 0
+  %4 = extractvalue { i64, i1 } %2, 1
+  store i64 %3, i64* %b.addr, align 8
+  ret void
+}
+
+define dso_local void @test_builtin_ppc_compare_and_swaplp_loop(i64* %a) {
+; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp_loop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[CALL:%.*]] = tail call i64 bitcast (i64 (...)* @bar to i64 ()*)()
+; CHECK-NEXT:br label [[DO_BODY:%.*]]
+; CHECK:   do.body:
+; CHECK-NEXT:[[X_0:%.*]] = phi i64 [ [[CALL]], [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[DO_BODY]] ]
+; CHECK-NEXT:[[ADD:%.*]] = add nsw i64 [[X_0]], 1
+; CHECK-NEXT:[[TMP0:%.*]] = cmpxchg weak volatile i64* [[A:%.*]], i64 [[X_0]], i64 [[ADD]] monotonic monotonic, align 8
+; CHECK-NEXT:[[TMP1]] = extractvalue { i64, i1 } [[TMP0]], 0
+; CHECK-NEXT:[[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
+; CHECK-NEXT:br i1 [[TMP2]], label [[DO_BODY]], label [[DO_END:%.*]]
+; CHECK:   do.end:
+; CHECK-NEXT:ret void
+;
+entry:
+  %a.addr = alloca i64*, align 8
+  %x = alloca i64, align 8
+  store i64* %a, i64** %a.addr, align 8
+  %call = call i64 bitcast (i64 (...)* @bar to i64 ()*)()
+  store i64 %call, i64* %x, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.cond, %entry
+  br label %do.cond
+
+do.cond:  ; preds = %do.body
+  %0 = load i64*, i64** %a.addr, align 8
+  %1 = load i64, i64* %x, align 8
+  %add = add nsw i64 %1, 1
+  %2 = load i64*, i64** %a.addr, align 8
+  %3 = load i64, i64* %x, align 8
+  %4 = cmpxchg weak volatile i64* %2, i64 %3, i64 %add monotonic monotonic, align 8
+  %5 = extractvalue { i64, i1 } %4, 0
+  %6 = extractvalue { i64, i1 } %4, 1
+  store i64 %5, i64* %x, align 8
+  %tobool = icmp ne i1 %6, false
+  br i1 %tobool, label %do.body, label %do.end
+
+do.end:   ; preds = %do.cond
+  ret void
+}
+
+declare i64 @bar(...)
Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -19,6 +19,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 [[TMP1]], i32 [[TMP0]] monotonic monotonic, align 4
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
@@ -39,6 +40,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[TMP1]], i64 [[TMP0]] monotonic monotonic, align 8
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGB

[PATCH] D106344: [PowerPC] Implement XL compatible behavior of __compare_and_swap

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 360721.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106344/new/

https://reviews.llvm.org/D106344

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
  llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll

Index: llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -enable-new-pm=1 -S -passes='default' %s -o - | FileCheck %s
+define void @test_builtin_ppc_compare_and_swaplp(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+; CHECK-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+; CHECK-NEXT:[[TMP0:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[B:%.*]], i64 [[C:%.*]] monotonic monotonic, align 8
+; CHECK-NEXT:ret void
+;
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  store i64 %a, i64* %a.addr, align 8
+  store i64 %b, i64* %b.addr, align 8
+  store i64 %c, i64* %c.addr, align 8
+  %0 = load i64, i64* %c.addr, align 8
+  %1 = load i64, i64* %b.addr, align 8
+  %2 = cmpxchg weak volatile i64* %a.addr, i64 %1, i64 %0 monotonic monotonic, align 8
+  %3 = extractvalue { i64, i1 } %2, 0
+  %4 = extractvalue { i64, i1 } %2, 1
+  store i64 %3, i64* %b.addr, align 8
+  ret void
+}
+
+define dso_local void @test_builtin_ppc_compare_and_swaplp_loop(i64* %a) {
+; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp_loop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[CALL:%.*]] = tail call i64 bitcast (i64 (...)* @bar to i64 ()*)()
+; CHECK-NEXT:br label [[DO_BODY:%.*]]
+; CHECK:   do.body:
+; CHECK-NEXT:[[X_0:%.*]] = phi i64 [ [[CALL]], [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[DO_BODY]] ]
+; CHECK-NEXT:[[ADD:%.*]] = add nsw i64 [[X_0]], 1
+; CHECK-NEXT:[[TMP0:%.*]] = cmpxchg weak volatile i64* [[A:%.*]], i64 [[X_0]], i64 [[ADD]] monotonic monotonic, align 8
+; CHECK-NEXT:[[TMP1]] = extractvalue { i64, i1 } [[TMP0]], 0
+; CHECK-NEXT:[[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
+; CHECK-NEXT:br i1 [[TMP2]], label [[DO_BODY]], label [[DO_END:%.*]]
+; CHECK:   do.end:
+; CHECK-NEXT:ret void
+;
+entry:
+  %a.addr = alloca i64*, align 8
+  %x = alloca i64, align 8
+  store i64* %a, i64** %a.addr, align 8
+  %call = call i64 bitcast (i64 (...)* @bar to i64 ()*)()
+  store i64 %call, i64* %x, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.cond, %entry
+  br label %do.cond
+
+do.cond:  ; preds = %do.body
+  %0 = load i64*, i64** %a.addr, align 8
+  %1 = load i64, i64* %x, align 8
+  %add = add nsw i64 %1, 1
+  %2 = load i64*, i64** %a.addr, align 8
+  %3 = load i64, i64* %x, align 8
+  %4 = cmpxchg weak volatile i64* %2, i64 %3, i64 %add monotonic monotonic, align 8
+  %5 = extractvalue { i64, i1 } %4, 0
+  %6 = extractvalue { i64, i1 } %4, 1
+  store i64 %5, i64* %x, align 8
+  %tobool = icmp ne i1 %6, false
+  br i1 %tobool, label %do.body, label %do.end
+
+do.end:   ; preds = %do.cond
+  ret void
+}
+
+declare i64 @bar(...)
Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -19,6 +19,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 [[TMP1]], i32 [[TMP0]] monotonic monotonic, align 4
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
@@ -39,6 +40,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[TMP1]], i64 [[TMP0]] monotonic monotonic, align 8
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15662,6 +15662,15 @@
 auto Pair = EmitAtomicCompareExchange(
 LV, RValue::get(OldVal), RValue::get(Ops[2]), E->getExprLoc(),
 llvm::AtomicOrdering::Monotonic, llvm::Atomic

[PATCH] D106344: [PowerPC] Implement XL compatible behavior of __compare_and_swap

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 360699.
lkail added a comment.
Herald added a project: LLVM.

Discussed with @jsji about the details of codegen and inspect XL's codegen at 
different opt level, add an `opt` test from jinsong to demonstrate the store 
can be eliminated.


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Files:
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  clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
  llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll


Index: llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -enable-new-pm=1 -S -passes='default' %s -o - | FileCheck %s
+define void @test_builtin_ppc_compare_and_swaplp(i64 %a, i64 %b, i64 %c) #0 {
+; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+; CHECK-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+; CHECK-NEXT:[[TMP0:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 
[[B:%.*]], i64 [[C:%.*]] monotonic monotonic, align 8
+; CHECK-NEXT:ret void
+;
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  store i64 %a, i64* %a.addr, align 8
+  store i64 %b, i64* %b.addr, align 8
+  store i64 %c, i64* %c.addr, align 8
+  %0 = load i64, i64* %c.addr, align 8
+  %1 = load i64, i64* %b.addr, align 8
+  %2 = cmpxchg weak volatile i64* %a.addr, i64 %1, i64 %0 monotonic monotonic, 
align 8
+  %3 = extractvalue { i64, i1 } %2, 0
+  %4 = extractvalue { i64, i1 } %2, 1
+  store i64 %3, i64* %b.addr, align 8
+  ret void
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -19,6 +19,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 
[[TMP1]], i32 [[TMP0]] monotonic monotonic, align 4
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
@@ -39,6 +40,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 
[[TMP1]], i64 [[TMP0]] monotonic monotonic, align 8
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15662,6 +15662,15 @@
 auto Pair = EmitAtomicCompareExchange(
 LV, RValue::get(OldVal), RValue::get(Ops[2]), E->getExprLoc(),
 llvm::AtomicOrdering::Monotonic, llvm::AtomicOrdering::Monotonic, 
true);
+// Unlike c11's atomic_compare_exchange, accroding to
+// 
https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1?topic=functions-compare-swap-compare-swaplp
+// > In either case, the contents of the memory location specified by addr
+// > are copied into the memory location specified by old_val_addr.
+// But it hasn't specified storing to OldValAddr is atomic or not and
+// which order to use. Now following XL's codegen, treat it as a normal
+// store.
+Value *LoadedVal = Pair.first.getScalarVal();
+Builder.CreateStore(LoadedVal, OldValAddr);
 return Pair.second;
   }
   case PPC::BI__builtin_ppc_fetch_and_add:


Index: llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -enable-new-pm=1 -S -passes='default' %s -o - | FileCheck %s
+define void @test_builtin_ppc_compare_and_swaplp(i64 %a, i64 %b, i64 %c) #0 {
+; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+; CHECK-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+; CHECK-NEXT:[[TMP0:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[B:%.*]], i64 [[C:%.*]] monotonic monotonic, align 8
+; CHECK-NEXT:ret void
+;
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca 

[PATCH] D106344: [PowerPC] Implement XL compatible behavior of __compare_and_swap

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

In D106344#2894755 , @jsji wrote:

> Doesn't look good enough to me,  the assembly code sequence generated is not 
> clean enough.

I'm assuming you mean the second `stdcx.`, that looks like a historical issue 
which exists for 13yrs. According to 
https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and what xlc generates 
for CAS, it should not exist.

  commit 166d6cb1fad159b1aedb3801ecaecb62000979d1
  Author: Dale Johannesen 
  Date:   Mon Aug 25 18:53:26 2008 +
  
  It's important for the cmp-and-swap to balance
  loads and stores but it's even more important for
  it to store the right value.:(
  
  llvm-svn: 55319


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Kai Luo via Phabricator via cfe-commits]

lkail accepted this revision.
lkail added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Kai Luo via Phabricator via cfe-commits]

lkail requested changes to this revision.
lkail added a comment.
This revision now requires changes to proceed.

Looks we should put it in `llvm/test/CodeGen/PowerPC`.


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[PATCH] D105926: [PowerPC] Extra test case for LDARX

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \

This looks problematic, we should not generate `llc`'s output in clang's test.


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[PATCH] D106344: [PowerPC] Correct behavior of __compare_and_swap

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: jsji, nemanjai, w2yehia, shchenz, PowerPC.
Herald added subscribers: jfb, kbarton.
lkail requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

XL's `__compare_and_swap` has a weird behavior that

> In either case, the contents of the memory location specified by addr are 
> copied into the memory location specified by old_val_addr.

This patch let clang's implementation follow this behavior.


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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cas.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -19,6 +19,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 
[[TMP1]], i32 [[TMP0]] monotonic monotonic, align 4
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
@@ -39,6 +40,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 
[[TMP1]], i64 [[TMP0]] monotonic monotonic, align 8
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15590,6 +15590,15 @@
 auto Pair = EmitAtomicCompareExchange(
 LV, RValue::get(OldVal), RValue::get(Ops[2]), E->getExprLoc(),
 llvm::AtomicOrdering::Monotonic, llvm::AtomicOrdering::Monotonic, 
true);
+// FIXME:
+// Unlike c11's atomic_compare_exchange, accroding to
+// 
https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1?topic=functions-compare-swap-compare-swaplp
+// > In either case, the contents of the memory location specified by addr
+// > are copied into the memory location specified by old_val_addr.
+// But it hasn't specified storing to OldValAddr is atomic or not and
+// which order to use.
+Value *LoadedVal = Pair.first.getScalarVal();
+Builder.CreateStore(LoadedVal, OldValAddr);
 return Pair.second;
   }
   case PPC::BI__builtin_ppc_fetch_and_add:


Index: clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -19,6 +19,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 [[TMP1]], i32 [[TMP0]] monotonic monotonic, align 4
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
@@ -39,6 +40,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[TMP1]], i64 [[TMP0]] monotonic monotonic, align 8
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15590,6 +15590,15 @@
 auto Pair = EmitAtomicCompareExchange(
 LV, RValue::get(OldVal), RValue::get(Ops[2]), E->getExprLoc(),
 llvm::AtomicOrdering::Monotonic, llvm::AtomicOrdering::Monotonic, true);
+// FIXME:
+// Unlike c11's atomic_compare_exchange, accroding to
+// https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1?topic=functions-compare-swap-compare-swaplp
+// > In either case, the contents of the memory location specified by addr
+// > are copied into the memory location specified by old_val_addr.
+// But it hasn't specified storing to OldValAddr is atomic or not and
+// which order to use.
+Value *LoadedVal = Pair.first.getScalarVal();
+Builder.CreateStore(LoadedVal, OldValAddr);
 return Pair.second;
   }
   case PPC::BI__builtin_ppc_fetch_and_add:
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[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:1015
+break;
+  }
+

Adding `default: llvm_unreachable` would be nice.


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[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:997
 
+static llvm::Value *emitLoadReserveIntrinsic(CodeGenFunction &CGF,
+ unsigned BuiltinID,

Maybe rename to `emitPPCLoadReserveIntrinsic` should be more appropriate, since 
other targets also have similar load-reserve/load-linked/load-acquire notions 
and what this function does is ad hoc to PPC.


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[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1535
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }

Just curious, compiler optimizes the instruction out even setting 
`IntrArgMemOnly` and `IntrReadMem` here?


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[PATCH] D105236: [PowerPC] Implement Load and Reserve and Store Conditional Builtins

[Kai Luo via Phabricator via cfe-commits]

lkail accepted this revision.
lkail added a comment.

lgtm,thanks.


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[PATCH] D105236: [PowerPC] Implament Atomic Load and Stores Builtins

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

The wording might be inaccurate. It's better to rephrase to 'Load and Reserve 
and Store Conditional'.




Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1724
+
+let Predicates = [HasP8Altivec] in {
+  def : Pat<(int_ppc_stdcx xoaddr:$dst, g8rc:$A),

IIRC, `l(w|d)arx`, `st(w|d)cx` are supported very early and don't need altivec 
support.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore-64-only.ll:7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK
+

Is `-mcpu=pwr9` necessary?


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[PATCH] D104991: [PowerPC] Add XL Compat fetch builtins

[Kai Luo via Phabricator via cfe-commits]

lkail accepted this revision.
lkail added a comment.

LGTM, thanks.


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/test/CodeGen/ppc64-quadword-atomics.c:10
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics

hubert.reinterpretcast wrote:
> Can you add a link to something that demonstrates that the implementation of 
> `__atomic_exchange` is also lock-free when running on `pwr8` and up?
https://reviews.llvm.org/D103614#C2646926NL5 All related lock-free codegen is 
in the parent revision.


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

[Kai Luo via Phabricator via cfe-commits]

lkail added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:336
 .Default(false);
+  Features["quadword-atomics"] = llvm::StringSwitch(CPU)
+ .Case("pwr10", true)

qiucf wrote:
> What about `ppc64`?
> 
> Also, seems there's no need to add `pwr10` here.
> What about ppc64?


Instructions needed for inline quadword atomics like `lqarx` and `stqcx` are 
only user-space viable in pwr8 and above. However, pwr6 and pwr7 also feature 
ppc64.


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

[Kai Luo via Phabricator via cfe-commits]

lkail updated this revision to Diff 353268.
lkail added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103501/new/

https://reviews.llvm.org/D103501

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/ppc64-quadword-atomics.c


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, &new, &old, __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+// FIXME: Current only support quadword inline atomics on AIX.
+if (getTriple().isOSAIX() && hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtrBuiltinVaList;
   }
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,8 @@
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+quadword-atomics") {
+  HasQuadwordAtomics = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -352,6 +354,11 @@
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
+  Features["quadword-atomics"] =
+  getTriple().isArch64Bit() && llvm::StringSwitch(CPU)
+   .Case("pwr9", true)
+   .Case("pwr8", true)
+   .Default(false);
 
   // ROP Protect is off by default.
   Features["rop-protect"] = false;
@@ -449,6 +456,7 @@
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
+  .Case("quadword-atomics", HasQuadwordAtomics)
   .Default(false);
 }
 


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, &new, &old, __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+// FIXME: Current only support quadword inline atomics on AIX.
+if (getTriple().isOSAIX() && hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtrBuiltinVaList;
   }
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,8 @@
   HasROPProtect = true;

[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: nemanjai, jsji, xingxue, hubert.reinterpretcast, 
cebowleratibm, PowerPC.
Herald added subscribers: jfb, kbarton.
Herald added a reviewer: jfb.
lkail requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

If target cpu is pwr8+, we can generate inlined quadword lock free atomic 
operations, thus no need to generate libcalls into libatomic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103501

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/ppc64-quadword-atomics.c


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, &new, &old, __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+if (getTriple().isOSAIX() && getTriple().isArch64Bit() &&
+hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtrBuiltinVaList;
   }
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,8 @@
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+quadword-atomics") {
+  HasQuadwordAtomics = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -331,6 +333,11 @@
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
+  Features["quadword-atomics"] = llvm::StringSwitch(CPU)
+ .Case("pwr10", true)
+ .Case("pwr9", true)
+ .Case("pwr8", true)
+ .Default(false);
 
   // ROP Protect is off by default.
   Features["rop-protect"] = false;
@@ -428,6 +435,7 @@
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
+  .Case("quadword-atomics", HasQuadwordAtomics)
   .Default(false);
 }
 


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, &new, &old, __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+if (getTriple().isOSAIX() && getTriple().isArch64Bit() &&
+hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtr

[PATCH] D81355: [PowerPC] Enable -fstack-clash-protection option for ppc64

[Kai Luo via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG68e07da3e5d5: [clang][PowerPC] Enable 
-fstack-clash-protection option for ppc64 (authored by lkail).

Changed prior to commit:
  https://reviews.llvm.org/D81355?vs=269094&id=275538#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81355/new/

https://reviews.llvm.org/D81355

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/stack-clash-protection.c


Index: clang/test/CodeGen/stack-clash-protection.c
===
--- clang/test/CodeGen/stack-clash-protection.c
+++ clang/test/CodeGen/stack-clash-protection.c
@@ -1,6 +1,8 @@
 // Check the correct function attributes are generated
 // RUN: %clang_cc1 -triple x86_64-linux -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
 // RUN: %clang_cc1 -triple s390x-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
 
 // CHECK: define void @large_stack() #[[A:.*]] {
 void large_stack() {
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2966,7 +2966,8 @@
   if (!EffectiveTriple.isOSLinux())
 return;
 
-  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ())
+  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ() &&
+  !EffectiveTriple.isPPC64())
 return;
 
   if (Args.hasFlag(options::OPT_fstack_clash_protection,
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -343,6 +343,10 @@
   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
 
   bool hasExtIntType() const override { return true; }
+
+  bool isSPRegName(StringRef RegName) const override {
+return RegName.equals("r1") || RegName.equals("x1");
+  }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -94,8 +94,8 @@
 --
 
 - -fstack-clash-protection will provide a protection against the stack clash
-  attack for x86 and s390x architectures through automatic probing of each page
-  of allocated stack.
+  attack for x86, s390x and ppc64 architectures through automatic probing of
+  each page of allocated stack.
 
 - -ffp-exception-behavior={ignore,maytrap,strict} allows the user to specify
   the floating-point exception behavior. The default setting is ``ignore``.


Index: clang/test/CodeGen/stack-clash-protection.c
===
--- clang/test/CodeGen/stack-clash-protection.c
+++ clang/test/CodeGen/stack-clash-protection.c
@@ -1,6 +1,8 @@
 // Check the correct function attributes are generated
 // RUN: %clang_cc1 -triple x86_64-linux -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
 // RUN: %clang_cc1 -triple s390x-linux-gnu -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-gnu -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-linux-gnu -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
 
 // CHECK: define void @large_stack() #[[A:.*]] {
 void large_stack() {
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2966,7 +2966,8 @@
   if (!EffectiveTriple.isOSLinux())
 return;
 
-  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ())
+  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ() &&
+  !EffectiveTriple.isPPC64())
 return;
 
   if (Args.hasFlag(options::OPT_fstack_clash_protection,
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -343,6 +343,10 @@
   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
 
   bool hasExtIntType() const override { return true; }
+
+  bool isSPRegName(StringRef RegName) const override {
+return RegName.equals("r1") || RegName.equals("x1");
+  }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
Index: clang/docs/ReleaseNotes.rst
==

[PATCH] D81355: [PowerPC] Enable -fstack-clash-protection option for ppc64

[Kai Luo via Phabricator via cfe-commits]

lkail added a comment.

In D81355#2078752 , @steven.zhang 
wrote:

> Shouldn't this be the last patch to commit after the backend supporting this 
> feature ?


Yes, I've updated the parent revision.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81355/new/

https://reviews.llvm.org/D81355



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[PATCH] D81355: [PowerPC] Enable -fstack-clash-protection option for ppc64

[Kai Luo via Phabricator via cfe-commits]

lkail created this revision.
lkail added reviewers: PowerPC, hfinkel, jonpa, serge-sans-paille.
Herald added subscribers: cfe-commits, shchenz, kbarton, nemanjai.
Herald added a project: clang.

Open `-fstack-clash-protection` option in clang for ppc64 arch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81355

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/PPC.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/CodeGen/stack-clash-protection.c


Index: clang/test/CodeGen/stack-clash-protection.c
===
--- clang/test/CodeGen/stack-clash-protection.c
+++ clang/test/CodeGen/stack-clash-protection.c
@@ -1,6 +1,8 @@
 // Check the correct function attributes are generated
 // RUN: %clang_cc1 -triple x86_64-linux -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
 // RUN: %clang_cc1 -triple s390x-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
 
 // CHECK: define void @large_stack() #[[A:.*]] {
 void large_stack() {
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2999,7 +2999,8 @@
   if (!EffectiveTriple.isOSLinux())
 return;
 
-  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ())
+  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ() &&
+  !EffectiveTriple.isPPC64())
 return;
 
   if (Args.hasFlag(options::OPT_fstack_clash_protection,
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -342,6 +342,10 @@
   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
 
   bool hasExtIntType() const override { return true; }
+
+  bool isSPRegName(StringRef RegName) const override {
+return RegName.equals("r1") || RegName.equals("x1");
+  }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -94,8 +94,8 @@
 --
 
 - -fstack-clash-protection will provide a protection against the stack clash
-  attack for x86 and s390x architectures through automatic probing of each page
-  of allocated stack.
+  attack for x86, s390x and ppc64 architectures through automatic
+  probing of each page of allocated stack.
 
 - -ffp-exception-behavior={ignore,maytrap,strict} allows the user to specify
   the floating-point exception behavior. The default setting is ``ignore``.


Index: clang/test/CodeGen/stack-clash-protection.c
===
--- clang/test/CodeGen/stack-clash-protection.c
+++ clang/test/CodeGen/stack-clash-protection.c
@@ -1,6 +1,8 @@
 // Check the correct function attributes are generated
 // RUN: %clang_cc1 -triple x86_64-linux -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
 // RUN: %clang_cc1 -triple s390x-linux-gnu -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-gnu -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-linux-gnu -O0 -S -emit-llvm -o- %s -fstack-clash-protection | FileCheck %s
 
 // CHECK: define void @large_stack() #[[A:.*]] {
 void large_stack() {
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2999,7 +2999,8 @@
   if (!EffectiveTriple.isOSLinux())
 return;
 
-  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ())
+  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ() &&
+  !EffectiveTriple.isPPC64())
 return;
 
   if (Args.hasFlag(options::OPT_fstack_clash_protection,
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -342,6 +342,10 @@
   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
 
   bool hasExtIntType() const override { return true; }
+
+  bool isSPRegName(StringRef RegName) const override {
+return RegName.equals("r1") || RegName.equals("x1");
+  }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseN