[PATCH] D97912: [doc] Document that __fp16 will apply default argument promotion rule.

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ACLE didn't specify the default argument promotion rule on __fp16, but
the current implementation both on GCC and clang are applied default
argument promotion rule on __fp16, so I think it should document that.


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  clang/docs/LanguageExtensions.rst


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -569,12 +569,13 @@
 ``3.14f16``.
 
 Because default argument promotion only applies to the standard floating-point
-types, ``_Float16`` values are not promoted to ``double`` when passed as 
variadic
-or untyped arguments.  As a consequence, some caution must be taken when using
-certain library facilities with ``_Float16``; for example, there is no 
``printf`` format
-specifier for ``_Float16``, and (unlike ``float``) it will not be implicitly 
promoted to
-``double`` when passed to ``printf``, so the programmer must explicitly cast 
it to
-``double`` before using it with an ``%f`` or similar specifier.
+types and ``__fp16``, ``_Float16`` values are not promoted to ``double`` when
+passed as variadic or untyped arguments.  As a consequence, some caution must
+be taken when using certain library facilities with ``_Float16``; for example,
+there is no ``printf`` format specifier for ``_Float16``, and (unlike 
``float``)
+it will not be implicitly promoted to ``double`` when passed to ``printf``, so
+the programmer must explicitly cast it to ``double`` before using it with an
+``%f`` or similar specifier.
 
 Messages on ``deprecated`` and ``unavailable`` Attributes
 =


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -569,12 +569,13 @@
 ``3.14f16``.
 
 Because default argument promotion only applies to the standard floating-point
-types, ``_Float16`` values are not promoted to ``double`` when passed as variadic
-or untyped arguments.  As a consequence, some caution must be taken when using
-certain library facilities with ``_Float16``; for example, there is no ``printf`` format
-specifier for ``_Float16``, and (unlike ``float``) it will not be implicitly promoted to
-``double`` when passed to ``printf``, so the programmer must explicitly cast it to
-``double`` before using it with an ``%f`` or similar specifier.
+types and ``__fp16``, ``_Float16`` values are not promoted to ``double`` when
+passed as variadic or untyped arguments.  As a consequence, some caution must
+be taken when using certain library facilities with ``_Float16``; for example,
+there is no ``printf`` format specifier for ``_Float16``, and (unlike ``float``)
+it will not be implicitly promoted to ``double`` when passed to ``printf``, so
+the programmer must explicitly cast it to ``double`` before using it with an
+``%f`` or similar specifier.
 
 Messages on ``deprecated`` and ``unavailable`` Attributes
 =
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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Could you also update macros and attributes which implemented in 
https://reviews.llvm.org/D94403 and https://reviews.llvm.org/D94931


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[PATCH] D94403: [RISCV] Implement new architecture extension macros

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kito-cheng accepted this revision.
kito-cheng added a comment.

LGTM


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[PATCH] D94583: [RISCV] Update V extension to v1.0-draft 08a0b464.

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kito-cheng added a comment.

@jrtc27 just let you know I have same concern too, that's one major reason why 
we don't upstream those extension on GNU toolchain... we are intend to 
introduce an internal revision number on ELF attribute in near future, e.g. 
v-ext 0.9.1 / v0p9p1 to prevent compatible issue here.


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[PATCH] D94403: [RISCV] Implement new architecture extension macros

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

In D94403#2512232 , @asb wrote:

> @kito-cheng could you please confirm that this patch handles sub-extensions 
> in the same way GCC does. i.e. -march=rv32izbb0p92 defines `__riscv_zbb` but 
> NOT `__riscv_b`?

Yes :)


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[PATCH] D94403: [RISCV] Implement new architecture extension macros

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kito-cheng accepted this revision.
kito-cheng added a comment.

I believe the behavior has aligned to GCC now.


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[PATCH] D94403: [RISCV] Implement new architecture extension macros

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kito-cheng added a comment.

Just note how current GCC implemented, GCC implement that like implied 
extension, e.g. `V` implied `Zvamo` and `Zvlsseg`, so `__riscv_zvamo` is 
naturally defined when `V`-ext is enabled.




Comment at: clang/lib/Basic/Targets/RISCV.cpp:148
+  if (HasB) {
+Builder.defineMacro("__riscv_b", "92000");
 Builder.defineMacro("__riscv_bitmanip");

kito-cheng wrote:
> Could you add all subset included in `B`, like zba, zbb, zbc, zbp...
I expect there `HasB` also define `__riscv_zbb`, `__riscv_zbc`... as well here.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:153
+  if (HasV) {
+Builder.defineMacro("__riscv_v", "9000");
 Builder.defineMacro("__riscv_vector");

kito-cheng wrote:
> Could you add all subset included in `V`, `Zvamo` and `Zvlsseg`.
Ditto, I expect there `HasV` also define `__riscv_zvamo`, `__riscv_zvlsseg`... 
as well here.


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[PATCH] D94403: [RISCV] Implement new architecture extension macros

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

That's my fault, I didn't specify the behavior of sub-extension clearly on the 
spec, but I think it would be great if we also define sub-extension marcos, 
since it would be easier to check when some core only implement sub-extension, 
and the code can just check the sub-extensio rather than check both.




Comment at: clang/lib/Basic/Targets/RISCV.cpp:148
+  if (HasB) {
+Builder.defineMacro("__riscv_b", "92000");
 Builder.defineMacro("__riscv_bitmanip");

Could you add all subset included in `B`, like zba, zbb, zbc, zbp...



Comment at: clang/lib/Basic/Targets/RISCV.cpp:153
+  if (HasV) {
+Builder.defineMacro("__riscv_v", "9000");
 Builder.defineMacro("__riscv_vector");

Could you add all subset included in `V`, `Zvamo` and `Zvlsseg`.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Do you have implement register pair for rv32ifd_zfinx? I didn't saw the related 
implementation, but I could be wrong since I am not LLVM expert, in case you 
have implemented, you need a test case for that.


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[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

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kito-cheng added inline comments.



Comment at: clang/include/clang/Basic/RISCVVTypes.def:67
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t",  RvvInt8m2,  RvvInt8m2Ty,  16,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t",  RvvInt8m4,  RvvInt8m4Ty,  32,  8, 1, 
true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t",  RvvInt8m8,  RvvInt8m8Ty,  64,  8, 1, 
true)

khchen wrote:
> evandro wrote:
> > craig.topper wrote:
> > > craig.topper wrote:
> > > > jrtc27 wrote:
> > > > > liaolucy wrote:
> > > > > > RISC-V V has too many types, more than 200. All types use builtin 
> > > > > > types? Is it possible to reduce the number of builtin types?
> > > > > Indeed this is madness, what's wrong with just using 
> > > > > `__attribute__((vector_size(n)))` on the right type? We should not be 
> > > > > encouraging people to write code with architecture-specific types... 
> > > > > but if we _really_ need these because RISC-V GCC decided this is how 
> > > > > RISC-V V is going to look them can we not just shove them all in a 
> > > > > header as typedef's for the architecture-independent attributed types 
> > > > > and push that complexity out of the compiler itself?
> > > > We are using  to specify types in IR. The size of the 
> > > > fixed part is being used to control the LMUL parameter. There is 
> > > > currently no way to spell a scalable vector type in C in a generic way.
> > > > 
> > > > Alternatively I guess we could make LMUL a parameter to the intrinsic 
> > > > and create the scalable IR types in the frontend based on it?
> > > I do wonder why we bothered to have signed and unsigned types. The 
> > > signedness of the operation should be carried in the intrinsic name.
> > Some integer operations distinguish between signed and unsigned.  
> > I do wonder why we bothered to have signed and unsigned types. The 
> > signedness of the operation should be carried in the intrinsic name.
> 
> I think the only good thing for supporting both signed and unsigned type is 
> that are more readable and compiler can does type checking for programmer. 
> 
> maybe the alternative way is changing intrinsic naming rule like 
> 
> ```
> vint32m1_t a, b, c;
> a = vadd_i32m1(b, c);
> vuint32m1_t a, b, c;
> a = vadd_u32m1(b, c);
> vfloat32m1_t a, b, c;
> a = vadd_f32m1(b, c);
> ```
One quick thought about this, if the concern is too much built-in types are 
introduced in clang, maybe we could add a new attribute like 
`__attribute__((vector_size(n)))`, maybe named 
`__attribute__((riscv_scaleble_vector("[1|2|4|8|f2|f4|f8]")))`? and use that to 
define vector types like `typedef int 
__attribute__((riscv_scaleble_vector("2"))) vintm2_t`.


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[PATCH] D89025: [RISCV] Add -mtune support

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kito-cheng marked an inline comment as done.
kito-cheng added a comment.

@MaskRay Thanks, that's first time I know the suffix `-SAME`  :P


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[PATCH] D89025: [RISCV] Add -mtune support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 298293.
kito-cheng added a comment.

ChangeLog:

- Update testcase according to MaskRay's suggestion.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -75,13 +75,16 @@
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function ) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU =
   CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+  std::string TuneCPU =
+  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
   FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
-  std::string Key = CPU + FS;
+  std::string Key = CPU + TuneCPU + FS;
   auto  = SubtargetMap[Key];
   if (!I) {
 // This needs to be done before we create a new subtarget since any
@@ -98,7 +101,7 @@
   }
   ABIName = ModuleTargetABI->getString();
 }
-I = std::make_unique(TargetTriple, CPU, FS, ABIName, *this);
+I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
   }
   return I.get();
 }
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -71,13 +71,15 @@
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget (const Triple ,
-  StringRef CPU, StringRef FS,
+  StringRef CPU,
+  StringRef TuneCPU,
+  StringRef FS,
   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
-  RISCVSubtarget(const Triple , StringRef CPU, StringRef FS,
- StringRef ABIName, const TargetMachine );
+  RISCVSubtarget(const Triple , StringRef CPU, StringRef TuneCPU,
+ StringRef FS, StringRef ABIName, const TargetMachine );
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -30,13 +30,16 @@
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget ::initializeSubtargetDependencies(
-const Triple , StringRef CPU, StringRef FS, StringRef ABIName) {
+const Triple , StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
   std::string CPUName = std::string(CPU);
+  std::string TuneCPUName = std::string(TuneCPU);
   if (CPUName.empty())
 CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  if (TuneCPUName.empty())
+TuneCPUName = CPUName;
+  ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
   if (Is64Bit) {
 XLenVT = MVT::i64;
 XLen = 64;
@@ -47,11 +50,12 @@
   return *this;
 }
 
-RISCVSubtarget::RISCVSubtarget(const Triple , StringRef CPU, StringRef FS,
+RISCVSubtarget::RISCVSubtarget(const Triple , StringRef CPU,
+   StringRef TuneCPU, StringRef FS,
StringRef ABIName, const TargetMachine )
-: RISCVGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
   UserReservedRegister(RISCV::NUM_TARGET_REGS),
-  FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
+  FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new 

[PATCH] D89025: [RISCV] Add -mtune support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked 3 inline comments as done.
kito-cheng added a comment.

In D89025#2327749 , @luismarques wrote:

> In D89025#2324334 , @khchen wrote:
>
>> RISCV supports `-mcpu` with default empty arch to align gcc's `-mtune` 
>> behavior since clang didn't support `-mtune` before. But now clang has 
>> `-mtune`, is it a good idea to remove those options? (ex. 
>> `rocket-rv32/rv64`, `sifive-7-rv32/64`)
>
> If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or 
> unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang 
> with GCC. But I wonder if this might be too problematic, in terms of 
> compatibility.

Personally I would like to remove `rocket-rv32/rv64`, `sifive-7-rv32/64`, but I 
didn't remove `rocket-rv32/rv64`, `sifive-7-rv32/64` in version 2 patch,  since 
I concern about compatibility too, Clang/LLVM 11 already included that, I would 
prefer create another patch to remove that and discuss that issue.


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[PATCH] D89025: [RISCV] Add -mtune support

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kito-cheng updated this revision to Diff 298060.
kito-cheng added a comment.

ChangeLog

- Fix wording in comment
- Add more comment in testcase
- Fix format issue.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -75,13 +75,16 @@
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function ) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU =
   CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+  std::string TuneCPU =
+  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
   FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
-  std::string Key = CPU + FS;
+  std::string Key = CPU + TuneCPU + FS;
   auto  = SubtargetMap[Key];
   if (!I) {
 // This needs to be done before we create a new subtarget since any
@@ -98,7 +101,7 @@
   }
   ABIName = ModuleTargetABI->getString();
 }
-I = std::make_unique(TargetTriple, CPU, FS, ABIName, *this);
+I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
   }
   return I.get();
 }
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -71,13 +71,15 @@
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget (const Triple ,
-  StringRef CPU, StringRef FS,
+  StringRef CPU,
+  StringRef TuneCPU,
+  StringRef FS,
   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
-  RISCVSubtarget(const Triple , StringRef CPU, StringRef FS,
- StringRef ABIName, const TargetMachine );
+  RISCVSubtarget(const Triple , StringRef CPU, StringRef TuneCPU,
+ StringRef FS, StringRef ABIName, const TargetMachine );
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -30,13 +30,16 @@
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget ::initializeSubtargetDependencies(
-const Triple , StringRef CPU, StringRef FS, StringRef ABIName) {
+const Triple , StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
   std::string CPUName = std::string(CPU);
+  std::string TuneCPUName = std::string(TuneCPU);
   if (CPUName.empty())
 CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  if (TuneCPUName.empty())
+TuneCPUName = CPUName;
+  ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
   if (Is64Bit) {
 XLenVT = MVT::i64;
 XLen = 64;
@@ -47,11 +50,12 @@
   return *this;
 }
 
-RISCVSubtarget::RISCVSubtarget(const Triple , StringRef CPU, StringRef FS,
+RISCVSubtarget::RISCVSubtarget(const Triple , StringRef CPU,
+   StringRef TuneCPU, StringRef FS,
StringRef ABIName, const TargetMachine )
-: RISCVGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
   UserReservedRegister(RISCV::NUM_TARGET_REGS),
-  FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
+  FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
 

[PATCH] D89025: [RISCV] Add -mtune support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

> If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or 
> unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang 
> with GCC. But I wonder if this might be too problematic, in terms of 
> compatibility.

I am also working on `-mcpu` support for RISC-V GCC, and I expect it would 
included in next GCC release, so `-mcpu` and `-mtune` would align between both 
compilers.
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556058.html


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[PATCH] D89025: [RISCV] Add -mtune support

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, evandro, lenary, khchen.
kito-cheng added projects: LLVM, clang.
Herald added subscribers: llvm-commits, cfe-commits, dang, luismarques, apazos, 
sameer.abuasal, pzheng, pengfei, s.egerton, Jim, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
kito-cheng requested review of this revision.
Herald added a subscriber: MaskRay.

- The goal of this patch is improve option compatible with RISCV-V GCC, -mcpu 
support on GCC side will sent patch in next few days.
- -mtune only affect the pipeline model and non-arch/extension related target 
feature, e.g. instruction fusion; in td file it called TuneFeatures, which is 
introduced by X86 back-end[1].
- -mtune accept all valid option for -mcpu and extra alias processor option, 
e.g. `generic`, `rocket` and `sifive-7-series`, the purpose is option 
compatible with RISCV-V GCC.
- Processor alias for -mtune will resolve according the current target arch, 
rv32 or rv64, e.g. `rocket` will resolve to `rocket-rv32` or `rocket-rv64`.
- Interaction between -mcpu and -mtune:
  - -mtune has higher priority than -mcpu for pipeline model and  
TuneFeatures.

[1] https://reviews.llvm.org/D85165


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89025

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -75,13 +75,16 @@
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function ) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU =
   CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+  std::string TuneCPU =
+  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
   FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
-  std::string Key = CPU + FS;
+  std::string Key = CPU + TuneCPU + FS;
   auto  = SubtargetMap[Key];
   if (!I) {
 // This needs to be done before we create a new subtarget since any
@@ -98,7 +101,7 @@
   }
   ABIName = ModuleTargetABI->getString();
 }
-I = std::make_unique(TargetTriple, CPU, FS, ABIName, *this);
+I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
   }
   return I.get();
 }
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -71,13 +71,15 @@
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget (const Triple ,
-  StringRef CPU, StringRef FS,
+  StringRef CPU,
+  StringRef TuneCPU,
+  StringRef FS,
   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
-  RISCVSubtarget(const Triple , StringRef CPU, StringRef FS,
- StringRef ABIName, const TargetMachine );
+  RISCVSubtarget(const Triple , StringRef CPU, StringRef TuneCPU,
+ StringRef FS, StringRef ABIName, const TargetMachine );
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -30,13 +30,16 @@
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget ::initializeSubtargetDependencies(
-const Triple , StringRef CPU, StringRef FS, StringRef ABIName) {
+const Triple , StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
   std::string CPUName = std::string(CPU);
+  

[PATCH] D71124: [RISCV] support clang driver to select cpu

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:478
   // 1. Explicit choices using `--with-abi=`
-  // 2. A default based on `--with-arch=`, if provided
-  // 3. A default based on the target triple's arch
+  // 2. A default based on arch
   //

I think it worth to keep this comment untouched, since it describing GCC's 
behavior.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:531
+  // 3. A default based on `--with-abi=`, if provided
+  // 4. A default based on the target triple's arch
   //

This part seems like is describing about GCC's behavior, so it should not 
change unless GCC changed?


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[PATCH] D71124: [RISCV] support clang driver to select cpu

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Another proposal for -mcpu and -mtune:

Decoupling the -mcpu and -mtune option, -mcpu only accept concrete CPU, and 
-mtune for micro-arch/pipeline model, they accept different option set.

e.g.
-mcpu=sifive-e24 # Imply -march=rv32imafc -mtune=sifive-2-series
-mtune=sifive-2-series # no effect on arch
-mtune=rocket # no effect on arch

So -mcpu=rocket is invalid, since it's micro-arch/pipeline model only,
and -mtune=sifive-e24 is invalid too, because it's CPU not a micro-arch.


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[PATCH] D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Seems like this patch mixed with LTO related changes? Could you clean it up?


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[PATCH] D67508: [RISCV] support mutilib in baremetal environment

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1548
+{M.gccSuffix(),
+ "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix()});
+  });

It could be "riscv32-unknown-elf" other than "riscv64-unknown-elf".



Comment at: clang/lib/Driver/ToolChains/RISCVToolchain.cpp:129
+  }
+
   std::string Linker = getToolChain().GetProgramPath(getShortName());

This change seems like unrelated to multi-lib, could you split this change into 
new patch and add a test for that?



Comment at: clang/lib/Driver/ToolChains/RISCVToolchain.cpp:132
 
   if (D.isUsingLTO()) {
 assert(!Inputs.empty() && "Must have at least one input.");

This part will conflict when apply patch, you might generate patch with 
https://reviews.llvm.org/D67409, could you rebase the patch with current trunk?


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[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:387
+
+void riscv::addGoldOptions(const ToolChain ,
+   const llvm::opt::ArgList ,

MaskRay wrote:
> gold doesn't support RISC-V, does it?
Gold doesn't support RISC-V , but ld.bfd supported same plugin API, so this 
made clang can run LTO with ld.bfd.


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[PATCH] D67066: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: cfe-commits, pzheng, s.egerton, lenary, Jim, benna, 
psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, 
johnrusso, rbar.
Herald added a project: clang.
kito-cheng added a parent revision: D67065: [RISCV] Define 
__riscv_cmodel_medlow and __riscv_cmodel_medany correctly.

RISC-V GCC use -mcmodel=medany and -mcmodel=medlow, but LLVM use -mcmodel=small 
and -mcmodel=medium.

Add those two option aliases to provide same user interface between GCC and 
LLVM.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67066

Files:
  clang/include/clang/Driver/Options.td
  clang/test/Preprocessor/riscv-cmodel.c


Index: clang/test/Preprocessor/riscv-cmodel.c
===
--- clang/test/Preprocessor/riscv-cmodel.c
+++ clang/test/Preprocessor/riscv-cmodel.c
@@ -8,6 +8,11 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=medlow -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=medlow -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
 // CHECK-MEDLOW: #define __riscv_cmodel_medlow 1
 // CHECK-MEDLOW-NOT: __riscv_cmodel_medany
 
@@ -16,5 +21,10 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=medany -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=medany -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+
 // CHECK-MEDANY: #define __riscv_cmodel_medany 1
 // CHECK-MEDANY-NOT: __riscv_cmodel_medlow
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2166,6 +2166,12 @@
   HelpText<"Enable using library calls for save and restore">;
 def mno_save_restore : Flag<["-"], "mno-save-restore">, 
Group,
   HelpText<"Disable using library calls for save and restore">;
+def mcmodel_EQ_medlow : Flag<["-"], "mcmodel=medlow">, 
Group,
+  Flags<[CC1Option]>, Alias, AliasArgs<["small"]>,
+  HelpText<"Equivalent to -mcmodel=small, compatible with RISC-V gcc.">;
+def mcmodel_EQ_medany : Flag<["-"], "mcmodel=medany">, 
Group,
+  Flags<[CC1Option]>, Alias, AliasArgs<["medium"]>,
+  HelpText<"Equivalent to -mcmodel=medium, compatible with RISC-V gcc.">;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, 
Group,
   HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64 only)">;


Index: clang/test/Preprocessor/riscv-cmodel.c
===
--- clang/test/Preprocessor/riscv-cmodel.c
+++ clang/test/Preprocessor/riscv-cmodel.c
@@ -8,6 +8,11 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=medlow -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=medlow -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
 // CHECK-MEDLOW: #define __riscv_cmodel_medlow 1
 // CHECK-MEDLOW-NOT: __riscv_cmodel_medany
 
@@ -16,5 +21,10 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=medany -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=medany -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+
 // CHECK-MEDANY: #define __riscv_cmodel_medany 1
 // CHECK-MEDANY-NOT: __riscv_cmodel_medlow
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2166,6 +2166,12 @@
   HelpText<"Enable using library calls for save and restore">;
 def mno_save_restore : Flag<["-"], "mno-save-restore">, Group,
   HelpText<"Disable using library calls for save and restore">;
+def mcmodel_EQ_medlow : Flag<["-"], "mcmodel=medlow">, Group,
+  Flags<[CC1Option]>, Alias, AliasArgs<["small"]>,
+  

[PATCH] D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos, lewis-revill.
Herald added subscribers: cfe-commits, pzheng, s.egerton, lenary, Jim, benna, 
psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, MaskRay, jrtc27, shiva0217, niosHD, sabuasal, simoncook, 
johnrusso, rbar.
Herald added a project: clang.

RISC-V LLVM was only implement small/medlow code model, so it defined
__riscv_cmodel_medlow directly without check.

Now, we have medium/medany code model in RISC-V back-end, it should
define according the actually code model.


Repository:
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https://reviews.llvm.org/D67065

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/Preprocessor/riscv-cmodel.c


Index: clang/test/Preprocessor/riscv-cmodel.c
===
--- /dev/null
+++ clang/test/Preprocessor/riscv-cmodel.c
@@ -0,0 +1,20 @@
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
+// CHECK-MEDLOW: #define __riscv_cmodel_medlow 1
+// CHECK-MEDLOW-NOT: __riscv_cmodel_medany
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+
+// CHECK-MEDANY: #define __riscv_cmodel_medany 1
+// CHECK-MEDANY-NOT: __riscv_cmodel_medlow
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -89,7 +89,14 @@
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
   // TODO: modify when more code models are supported.
-  Builder.defineMacro("__riscv_cmodel_medlow");
+  StringRef CodeModel = getTargetOpts().CodeModel;
+  if (CodeModel == "default")
+CodeModel = "small";
+
+  if (CodeModel == "small")
+Builder.defineMacro("__riscv_cmodel_medlow");
+  else if (CodeModel == "medium")
+Builder.defineMacro("__riscv_cmodel_medany");
 
   StringRef ABIName = getABI();
   if (ABIName == "ilp32f" || ABIName == "lp64f")


Index: clang/test/Preprocessor/riscv-cmodel.c
===
--- /dev/null
+++ clang/test/Preprocessor/riscv-cmodel.c
@@ -0,0 +1,20 @@
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
+// CHECK-MEDLOW: #define __riscv_cmodel_medlow 1
+// CHECK-MEDLOW-NOT: __riscv_cmodel_medany
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+
+// CHECK-MEDANY: #define __riscv_cmodel_medany 1
+// CHECK-MEDANY-NOT: __riscv_cmodel_medlow
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -89,7 +89,14 @@
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
   // TODO: modify when more code models are supported.
-  Builder.defineMacro("__riscv_cmodel_medlow");
+  StringRef CodeModel = getTargetOpts().CodeModel;
+  if (CodeModel == "default")
+CodeModel = "small";
+
+  if (CodeModel == "small")
+Builder.defineMacro("__riscv_cmodel_medlow");
+  else if (CodeModel == "medium")
+Builder.defineMacro("__riscv_cmodel_medany");
 
   StringRef ABIName = getABI();
   if (ABIName == "ilp32f" || ABIName == "lp64f")
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[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 161990.
kito-cheng added a comment.
Herald added subscribers: jocewei, the_o, brucehoult, MartinMosbeck, mgrang, 
edward-jones, zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar.

Changes:

- Add test.


https://reviews.llvm.org/D50043

Files:
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/riscv32-toolchain.c


Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -9,6 +9,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32 %s
 
+// C-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // C-RV32-BAREMETAL-ILP32: 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // C-RV32-BAREMETAL-ILP32: 
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // C-RV32-BAREMETAL-ILP32: 
"{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
@@ -24,6 +25,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
+// CXX-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: 
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
@@ -40,6 +42,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32 %s
 
+// C-RV32-LINUX-MULTI-ILP32: "-fuse-init-array"
 // C-RV32-LINUX-MULTI-ILP32: 
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../../../riscv64-unknown-linux-gnu/bin{{/|}}ld"
 // C-RV32-LINUX-MULTI-ILP32: 
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
 // C-RV32-LINUX-MULTI-ILP32: "-m" "elf32lriscv"
@@ -55,6 +58,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32D %s
 
+// C-RV32-LINUX-MULTI-ILP32D: "-fuse-init-array"
 // C-RV32-LINUX-MULTI-ILP32D: 
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../../../riscv64-unknown-linux-gnu/bin{{/|}}ld"
 // C-RV32-LINUX-MULTI-ILP32D: 
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
 // C-RV32-LINUX-MULTI-ILP32D: "-m" "elf32lriscv"
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2554,7 +2554,9 @@
   getTriple().getOS() == llvm::Triple::NaCl ||
   (getTriple().getVendor() == llvm::Triple::MipsTechnologies &&
!getTriple().hasEnvironment()) ||
-  getTriple().getOS() == llvm::Triple::Solaris;
+  getTriple().getOS() == llvm::Triple::Solaris ||
+  getTriple().getArch() == llvm::Triple::riscv32 ||
+  getTriple().getArch() == llvm::Triple::riscv64;
 
   if (DriverArgs.hasFlag(options::OPT_fuse_init_array,
  options::OPT_fno_use_init_array, UseInitArrayDefault))


Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -9,6 +9,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32 %s
 
+// C-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // C-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // C-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // C-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
@@ -24,6 +25,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
+// CXX-RV32-BAREMETAL-ILP32: "-fuse-init-array"
 // CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
@@ -40,6 +42,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32 %s
 
+// C-RV32-LINUX-MULTI-ILP32: 

[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: cfe-commits, rkruppe, rogfer01, shiva0217, 
fedor.sergeev.

RISC-V target using -fuse-init-array even for bare-mental target.


Repository:
  rC Clang

https://reviews.llvm.org/D50043

Files:
  lib/Driver/ToolChains/Gnu.cpp


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2553,7 +2553,9 @@
   getTriple().getOS() == llvm::Triple::NaCl ||
   (getTriple().getVendor() == llvm::Triple::MipsTechnologies &&
!getTriple().hasEnvironment()) ||
-  getTriple().getOS() == llvm::Triple::Solaris;
+  getTriple().getOS() == llvm::Triple::Solaris ||
+  getTriple().getArch() == llvm::Triple::riscv32 ||
+  getTriple().getArch() == llvm::Triple::riscv64;
 
   if (DriverArgs.hasFlag(options::OPT_fuse_init_array,
  options::OPT_fno_use_init_array, UseInitArrayDefault))


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2553,7 +2553,9 @@
   getTriple().getOS() == llvm::Triple::NaCl ||
   (getTriple().getVendor() == llvm::Triple::MipsTechnologies &&
!getTriple().hasEnvironment()) ||
-  getTriple().getOS() == llvm::Triple::Solaris;
+  getTriple().getOS() == llvm::Triple::Solaris ||
+  getTriple().getArch() == llvm::Triple::riscv32 ||
+  getTriple().getArch() == llvm::Triple::riscv64;
 
   if (DriverArgs.hasFlag(options::OPT_fuse_init_array,
  options::OPT_fno_use_init_array, UseInitArrayDefault))
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[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.
Herald added subscribers: rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, 
jrtc27.

ping, Alex, could you commit that?


Repository:
  rC Clang

https://reviews.llvm.org/D46822



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[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:130
+  // which may override the defaults.
+  handleTargetFeaturesGroup(Args, Features, 
options::OPT_m_riscv_Features_Group);
 }

This part should  move to the begin of the function, otherwise it never 
executed if `Exts` is empty string.



Repository:
  rL LLVM

https://reviews.llvm.org/D44888



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[PATCH] D45284: [RISCV] More validations on the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Long time ago, GCC also accept upper case too, but I have no idea why Andrew 
change that? I guess one possible reason is because multi-lib?

[1] 
https://github.com/riscv/riscv-gcc/commit/6531a11f03ec3a95cd8b9033daeab0ebf23b5472


https://reviews.llvm.org/D45284



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[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 140959.
kito-cheng added a comment.

Changes:

- Reorder marco define into canonical order which specified in ISA manual.
- Add missing test for marco.


Repository:
  rC Clang

https://reviews.llvm.org/D44727

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/Modules/Inputs/module.map
  test/Modules/target-features.m
  test/Preprocessor/riscv-target-features.c

Index: test/Preprocessor/riscv-target-features.c
===
--- /dev/null
+++ test/Preprocessor/riscv-target-features.c
@@ -0,0 +1,49 @@
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -o - | FileCheck %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -o - | FileCheck %s
+
+// CHECK-NOT: __riscv_div
+// CHECK-NOT: __riscv_mul
+// CHECK-NOT: __riscv_muldiv
+// CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_flen
+// CHECK-NOT: __riscv_fdiv
+// CHECK-NOT: __riscv_fsqrt
+// CHECK-NOT: __riscv_atomic
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
+// CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_mul 1
+// CHECK-M-EXT: __riscv_muldiv 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_atomic 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_fdiv 1
+// CHECK-F-EXT: __riscv_flen 32
+// CHECK-F-EXT: __riscv_fsqrt 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_fdiv 1
+// CHECK-D-EXT: __riscv_flen 64
+// CHECK-D-EXT: __riscv_fsqrt 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_compressed 1
Index: test/Modules/target-features.m
===
--- test/Modules/target-features.m
+++ test/Modules/target-features.m
@@ -1,6 +1,7 @@
 // REQUIRES: x86-registered-target
 // REQUIRES: arm-registered-target
 // REQUIRES: aarch64-registered-target
+// REQUIRES: riscv-registered-target
 
 // RUN: rm -rf %t
 
@@ -17,45 +18,84 @@
 // RUN: FileCheck %s -check-prefix=X86_32 < %t.x86_32
 // RUN: not %clang_cc1 -triple x86_64-unknown-unknown -fmodules -fmodules-cache-path=%t -fimplicit-module-maps -I %S/Inputs -fsyntax-only  %s 2> %t.x86_64
 // RUN: FileCheck %s -check-prefix=X86_64 < %t.x86_64
+// RUN: not %clang_cc1 -triple riscv32-unknown-unknown -fmodules -fmodules-cache-path=%t -fimplicit-module-maps -I %S/Inputs -fsyntax-only  %s 2> %t.riscv32
+// RUN: FileCheck %s -check-prefix=RISCV32 < %t.riscv32
+// RUN: not %clang_cc1 -triple riscv64-unknown-unknown -fmodules -fmodules-cache-path=%t -fimplicit-module-maps -I %S/Inputs -fsyntax-only  %s 2> %t.riscv64
+// RUN: FileCheck %s -check-prefix=RISCV64 < %t.riscv64
 
 #ifndef SANITY_CHECK
 @import TargetFeatures;
 // AARCH32-NOT: module 'TargetFeatures' requires
 // AARCH64-NOT: module 'TargetFeatures' requires
 // X86_32-NOT: module 'TargetFeatures' requires
 // X86_64-NOT: module 'TargetFeatures' requires
+// RISCV32-NOT: module 'TargetFeatures' requires
+// RISCV64-NOT: module 'TargetFeatures' requires
 @import TargetFeatures.arm;
 // AARCH32-NOT: module 'TargetFeatures.arm' requires
 // AARCH64-NOT: module 'TargetFeatures.arm' requires
 // X86_32: module 'TargetFeatures.arm' requires feature 'arm'
 // X86_64: module 'TargetFeatures.arm' requires feature 'arm'
+// RISCV32: module 'TargetFeatures.arm' requires
+// RISCV64: module 'TargetFeatures.arm' requires
 @import TargetFeatures.arm.aarch32;
 // AARCH32-NOT: module 'TargetFeatures.arm.aarch32' requires
 // AARCH64: module 'TargetFeatures.arm.aarch32' requires feature 'aarch32'
 // X86_32: module 'TargetFeatures.arm.aarch32' requires feature 
 // X86_64: module 'TargetFeatures.arm.aarch32' requires feature
+// RISCV32: module 'TargetFeatures.arm.aarch32' requires feature
+// RISCV64: 

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 140913.
kito-cheng added a comment.

Changes:

- Add testcase for TargetFeature: riscv, riscv32 and riscv64


Repository:
  rC Clang

https://reviews.llvm.org/D44727

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/Modules/Inputs/module.map
  test/Modules/target-features.m

Index: test/Modules/target-features.m
===
--- test/Modules/target-features.m
+++ test/Modules/target-features.m
@@ -1,6 +1,7 @@
 // REQUIRES: x86-registered-target
 // REQUIRES: arm-registered-target
 // REQUIRES: aarch64-registered-target
+// REQUIRES: riscv-registered-target
 
 // RUN: rm -rf %t
 
@@ -17,45 +18,84 @@
 // RUN: FileCheck %s -check-prefix=X86_32 < %t.x86_32
 // RUN: not %clang_cc1 -triple x86_64-unknown-unknown -fmodules -fmodules-cache-path=%t -fimplicit-module-maps -I %S/Inputs -fsyntax-only  %s 2> %t.x86_64
 // RUN: FileCheck %s -check-prefix=X86_64 < %t.x86_64
+// RUN: not %clang_cc1 -triple riscv32-unknown-unknown -fmodules -fmodules-cache-path=%t -fimplicit-module-maps -I %S/Inputs -fsyntax-only  %s 2> %t.riscv32
+// RUN: FileCheck %s -check-prefix=RISCV32 < %t.riscv32
+// RUN: not %clang_cc1 -triple riscv64-unknown-unknown -fmodules -fmodules-cache-path=%t -fimplicit-module-maps -I %S/Inputs -fsyntax-only  %s 2> %t.riscv64
+// RUN: FileCheck %s -check-prefix=RISCV64 < %t.riscv64
 
 #ifndef SANITY_CHECK
 @import TargetFeatures;
 // AARCH32-NOT: module 'TargetFeatures' requires
 // AARCH64-NOT: module 'TargetFeatures' requires
 // X86_32-NOT: module 'TargetFeatures' requires
 // X86_64-NOT: module 'TargetFeatures' requires
+// RISCV32-NOT: module 'TargetFeatures' requires
+// RISCV64-NOT: module 'TargetFeatures' requires
 @import TargetFeatures.arm;
 // AARCH32-NOT: module 'TargetFeatures.arm' requires
 // AARCH64-NOT: module 'TargetFeatures.arm' requires
 // X86_32: module 'TargetFeatures.arm' requires feature 'arm'
 // X86_64: module 'TargetFeatures.arm' requires feature 'arm'
+// RISCV32: module 'TargetFeatures.arm' requires
+// RISCV64: module 'TargetFeatures.arm' requires
 @import TargetFeatures.arm.aarch32;
 // AARCH32-NOT: module 'TargetFeatures.arm.aarch32' requires
 // AARCH64: module 'TargetFeatures.arm.aarch32' requires feature 'aarch32'
 // X86_32: module 'TargetFeatures.arm.aarch32' requires feature 
 // X86_64: module 'TargetFeatures.arm.aarch32' requires feature
+// RISCV32: module 'TargetFeatures.arm.aarch32' requires feature
+// RISCV64: module 'TargetFeatures.arm.aarch32' requires feature
 #endif
 
 @import TargetFeatures.arm.aarch64;
 // AARCH32: module 'TargetFeatures.arm.aarch64' requires feature 'aarch64'
 // AARCH64-NOT: module 'TargetFeatures.arm.aarch64' requires
 // X86_32: module 'TargetFeatures.arm.aarch64' requires feature 
 // X86_64: module 'TargetFeatures.arm.aarch64' requires feature
+// RISCV32: module 'TargetFeatures.arm.aarch64' requires feature
+// RISCV64: module 'TargetFeatures.arm.aarch64' requires feature
 
 #ifndef SANITY_CHECK
 @import TargetFeatures.x86;
 // AARCH32:  module 'TargetFeatures.x86' requires feature 'x86'
 // AARCH64:  module 'TargetFeatures.x86' requires feature 'x86'
 // X86_32-NOT: module 'TargetFeatures.x86' requires
 // X86_64-NOT: module 'TargetFeatures.x86' requires
+// RISCV32:  module 'TargetFeatures.x86' requires feature 'x86'
+// RISCV64:  module 'TargetFeatures.x86' requires feature 'x86'
 @import TargetFeatures.x86.x86_32;
 // AARCH32:  module 'TargetFeatures.x86.x86_32' requires feature
 // AARCH64:  module 'TargetFeatures.x86.x86_32' requires feature
 // X86_32-NOT: module 'TargetFeatures.x86.x86_32' requires
 // X86_64: module 'TargetFeatures.x86.x86_32' requires feature 'x86_32'
+// RISCV32:  module 'TargetFeatures.x86.x86_32' requires feature
+// RISCV64:  module 'TargetFeatures.x86.x86_32' requires feature
 @import TargetFeatures.x86.x86_64;
 // AARCH32:  module 'TargetFeatures.x86.x86_64' requires feature
 // AARCH64:  module 'TargetFeatures.x86.x86_64' requires feature
 // X86_32: module 'TargetFeatures.x86.x86_64' requires feature 'x86_64'
 // X86_64-NOT: module 'TargetFeatures.x86.x86_64' requires
+// RISCV32:  module 'TargetFeatures.x86.x86_64' requires feature
+// RISCV64:  module 'TargetFeatures.x86.x86_64' requires feature
+@import TargetFeatures.riscv;
+// AARCH32:  module 'TargetFeatures.riscv' requires feature
+// AARCH64:  module 'TargetFeatures.riscv' requires feature
+// X86_32: module 'TargetFeatures.riscv' requires feature
+// X86_64: module 'TargetFeatures.riscv' requires feature
+// RISCV32-NOT: module 'TargetFeatures.riscv' requires feature
+// RISCV64-NOT: module 'TargetFeatures.riscv' requires feature
+@import TargetFeatures.riscv.riscv32;
+// AARCH32:  module 'TargetFeatures.riscv.riscv32' requires feature
+// AARCH64:  module 'TargetFeatures.riscv.riscv32' requires feature
+// X86_32: module 'TargetFeatures.riscv.riscv32' requires feature
+// X86_64: module 'TargetFeatures.riscv.riscv32' 

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Hi Eli:

Thanks your advise, I've checked those marco are match with GCC :)


Repository:
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https://reviews.llvm.org/D44727



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[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 140046.
kito-cheng retitled this revision from "[RISCV] Implement getTargetDefines, 
handleTargetFeatures and hasFeature for RISCVTargetInfo" to "[RISCV] Extend 
getTargetDefines for RISCVTargetInfo".
kito-cheng edited the summary of this revision.
kito-cheng added a comment.

Changes:

- Define __riscv_atomic, __riscv_flen, __riscv_fdiv and __riscv_fsqr, and add 
test for those marco.
- Handle riscv, riscv32 and riscv64 in RISCVTargetInfo::hasFeature.
- Fix several coding style issue.
- Breaking the long lines in test case.
- Add comment for RISCVTargetInfo::hasFeature.


Repository:
  rC Clang

https://reviews.llvm.org/D44727

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/Preprocessor/riscv-target-features.c

Index: test/Preprocessor/riscv-target-features.c
===
--- /dev/null
+++ test/Preprocessor/riscv-target-features.c
@@ -0,0 +1,49 @@
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -o - | FileCheck %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -o - | FileCheck %s
+
+// CHECK-NOT: __riscv_div
+// CHECK-NOT: __riscv_mul
+// CHECK-NOT: __riscv_muldiv
+// CHECK-NOT: __riscv_compressed
+// CHECK-NOT: __riscv_flen
+// CHECK-NOT: __riscv_fdiv
+// CHECK-NOT: __riscv_fsqrt
+// CHECK-NOT: __riscv_atomic
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
+// CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_mul 1
+// CHECK-M-EXT: __riscv_muldiv 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __riscv_atomic 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __riscv_fdiv 1
+// CHECK-F-EXT: __riscv_flen 32
+// CHECK-F-EXT: __riscv_fsqrt 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ifd -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __riscv_fdiv 1
+// CHECK-D-EXT: __riscv_flen 64
+// CHECK-D-EXT: __riscv_fsqrt 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_compressed 1
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -26,10 +26,16 @@
 class RISCVTargetInfo : public TargetInfo {
 protected:
   std::string ABI;
+  bool HasM;
+  bool HasA;
+  bool HasF;
+  bool HasD;
+  bool HasC;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
-  : TargetInfo(Triple) {
+  : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
+HasD(false), HasC(false) {
 TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
@@ -59,6 +65,11 @@
  TargetInfo::ConstraintInfo ) const override {
 return false;
   }
+
+  bool hasFeature(StringRef Feature) const override;
+
+  bool handleTargetFeatures(std::vector ,
+DiagnosticsEngine ) override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -49,4 +49,60 @@
   // TODO: modify when more code models and ABIs are supported.
   Builder.defineMacro("__riscv_cmodel_medlow");
   Builder.defineMacro("__riscv_float_abi_soft");
+
+  if (HasM) {
+Builder.defineMacro("__riscv_mul");
+Builder.defineMacro("__riscv_div");
+Builder.defineMacro("__riscv_muldiv");
+  }
+
+  if (HasC)
+Builder.defineMacro("__riscv_compressed");
+
+  if (HasD)
+Builder.defineMacro("__riscv_flen", "64");
+  else if (HasF)
+Builder.defineMacro("__riscv_flen", "32");
+
+  if (HasF || HasD) {
+Builder.defineMacro("__riscv_fdiv");
+Builder.defineMacro("__riscv_fsqrt");
+  }
+
+  if (HasA)
+

[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked 4 inline comments as done.
kito-cheng added a comment.

Hi Alex:

Thanks for your input, check for repeated letter was missed in my last patch :)




Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:34
+
+// The canonical order specified in ISA manual.
+StringRef StdExts = "mafdc";

asb wrote:
> I'd reference Table 22.1 in RISC-V User-Level ISA V2.2 for anyone who wants 
> to verify this.
Done.



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:37-38
+
+bool hasF = false, hasD = false;
+char baseline = MArch[4];
+

asb wrote:
> Should be HasF, HasD, and Baseline to conform to standard LLVM naming 
> conventions.
Fixed.



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:65
+for (char c : Exts) {
+  // Check march is satisfied the canonical order.
+  while (StdExtsItr != StdExts.end() && *StdExtsItr != c)

asb wrote:
> I'd phrase this as "Check ISA extensions are specified in the canonical 
> order."
Done.



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:99
+
+// Dependency check
+if (hasD && !hasF)

asb wrote:
> I'd be tempted to give a bit more explanation a bit more "It's illegal to 
> specify the 'd' (double-precision floating point) extension without also 
> specifying the 'f' (single precision floating-point) extension".
Done.


Repository:
  rC Clang

https://reviews.llvm.org/D44189



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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 139256.
kito-cheng added a comment.

Update revision according Alex's review.

Changes:

- Add testcase for uppercase of -march string.
- Add testcase for repeated letter in -march.
- Add more comment.
- Add several TODO item for diagnostic message improvement.
- Fix coding style issue.


Repository:
  rC Clang

https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,89 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ima -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ic -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ia -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32g -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32gc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64im -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ima -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ic -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ia -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64g -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64gc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// CHECK-NOT: error: invalid arch name '
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// 

[PATCH] D44727: [RISCV] Implement getTargetDefines, handleTargetFeatures and hasFeature for RISCVTargetInfo

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: cfe-commits, shiva0217, niosHD, sabuasal, 
jordy.potman.lists, simoncook, johnrusso, rbar.
kito-cheng added a dependency: D44189: [RISCV] Verify the input value of 
-march=.

This patch implement getTargetDefines, handleTargetFeatures and hasFeature. and 
define corresponding marco for those features.


Repository:
  rC Clang

https://reviews.llvm.org/D44727

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/Preprocessor/riscv-target-features.c

Index: test/Preprocessor/riscv-target-features.c
===
--- /dev/null
+++ test/Preprocessor/riscv-target-features.c
@@ -0,0 +1,17 @@
+// RUN: %clang -target riscv32-unknown-linux-gnu -x c -E -dM %s -o - | FileCheck %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -x c -E -dM %s -o - | FileCheck %s
+
+// CHECK-NOT: __riscv_div
+// CHECK-NOT: __riscv_mul
+// CHECK-NOT: __riscv_muldiv
+// CHECK-NOT: __riscv_compressed
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-M-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64im -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-M-EXT %s
+// CHECK-M-EXT: __riscv_div 1
+// CHECK-M-EXT: __riscv_mul 1
+// CHECK-M-EXT: __riscv_muldiv 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32ic -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ic -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-C-EXT %s
+// CHECK-C-EXT: __riscv_compressed 1
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -26,10 +26,16 @@
 class RISCVTargetInfo : public TargetInfo {
 protected:
   std::string ABI;
+  bool HasM;
+  bool HasA;
+  bool HasF;
+  bool HasD;
+  bool HasC;
 
 public:
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
-  : TargetInfo(Triple) {
+  : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
+HasD(false), HasC(false) {
 TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
@@ -59,6 +65,11 @@
  TargetInfo::ConstraintInfo ) const override {
 return false;
   }
+
+  bool hasFeature(StringRef Feature) const override;
+
+  bool handleTargetFeatures(std::vector ,
+DiagnosticsEngine ) override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -49,4 +49,49 @@
   // TODO: modify when more code models and ABIs are supported.
   Builder.defineMacro("__riscv_cmodel_medlow");
   Builder.defineMacro("__riscv_float_abi_soft");
+
+  if (HasM) {
+Builder.defineMacro("__riscv_mul");
+Builder.defineMacro("__riscv_div");
+Builder.defineMacro("__riscv_muldiv");
+  }
+
+  if (HasC)
+Builder.defineMacro("__riscv_compressed");
+
+  // TODO: Define __riscv_flen, __riscv_fdiv and __riscv_fsqrt after
+  // F and D code gen upstream.
+
+  // TODO: Define __riscv_atomic after A code gen upstream.
+}
+
+bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
+  return llvm::StringSwitch(Feature)
+  .Case("m", HasM)
+  .Case("a", HasA)
+  .Case("f", HasF)
+  .Case("d", HasD)
+  .Case("c", HasC)
+  .Default(false);
+}
+
+/// handleTargetFeatures - Perform initialization based on the user
+/// configured set of features.
+bool RISCVTargetInfo::handleTargetFeatures(std::vector ,
+   DiagnosticsEngine ) {
+  for (const auto  : Features) {
+if (Feature == "+m") {
+  HasM = true;
+} else if (Feature == "+a") {
+  HasA = true;
+} else if (Feature == "+f") {
+  HasF = true;
+} else if (Feature == "+d") {
+  HasD = true;
+} else if (Feature == "+c") {
+  HasC = true;
+}
+  }
+
+  return true;
 }
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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 137970.
kito-cheng added a comment.

Add test cases for the correct inputs.


https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,77 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ima -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ic -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ia -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32g -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32gc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64im -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ima -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ic -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ia -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iaf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafd -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iac -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafc -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64iafdc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64g -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64gc -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// CHECK-NOT: error: invalid arch name '
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
+// RV32IMADF: error: invalid arch name 'rv32imadf'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### 

[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 137687.
kito-cheng added a comment.

This version only update variable name which changed in last version by 
accident.


https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,29 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
+// RV32IMADF: error: invalid arch name 'rv32imadf'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64 %s
+// RV64: error: invalid arch name 'rv64'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64M %s
+// RV64M: error: invalid arch name 'rv64m'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64ID %s
+// RV64ID: error: invalid arch name 'rv64id'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
+// RV64L: error: invalid arch name 'rv64l'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
+// RV64IMADF: error: invalid arch name 'rv64imadf'
Index: lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- lib/Driver/ToolChains/Arch/RISCV.cpp
+++ lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -24,32 +24,81 @@
std::vector ) {
   if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
 StringRef MArch = A->getValue();
-// TODO: handle rv64
-std::pair MArchSplit = StringRef(MArch).split("rv32");
-if (!MArchSplit.second.size())
+if (!(MArch.startswith("rv32") || MArch.startswith("rv64")) ||
+(MArch.size() < 5)) {
+  // ISA string must begin with rv32 or rv64.
+  D.Diag(diag::err_drv_invalid_arch_name) << MArch;
   return;
+}
+
+// The canonical order specified in ISA manual.
+StringRef StdExts = "mafdc";
+
+bool hasF = false, hasD = false;
+char baseline = MArch[4];
+
+// TODO: Add 'e' once backend supported.
+switch (baseline) {
+default:
+  // First letter should be 'e', 'i' or 'g'.
+  D.Diag(diag::err_drv_invalid_arch_name) << MArch;
+  return;
+case 'i':
+  break;
+case 'g':
+  // g = imafd
+  StdExts = StdExts.drop_front(4);
+  Features.push_back("+m");
+  Features.push_back("+a");
+  Features.push_back("+f");
+  Features.push_back("+d");
+  hasF = true;
+  hasD = true;
+  break;
+}
 
-for (char c : MArchSplit.second) {
+auto StdExtsItr = StdExts.begin();
+// Skip rvxxx
+StringRef Exts = MArch.substr(5);
+
+for (char c : Exts) {
+  // Check march is satisfied the canonical order.
+  while (StdExtsItr != StdExts.end() && *StdExtsItr != c)
+ ++StdExtsItr;
+
+  if (StdExtsItr == StdExts.end()) {
+D.Diag(diag::err_drv_invalid_arch_name) << MArch;
+return;
+  }
+
+  // The order is OK, then push it into features.
   switch (c) {
-  case 'i':
-break;
+  default:
+D.Diag(diag::err_drv_invalid_arch_name) << MArch;
+return;
   case 'm':
 Features.push_back("+m");
 break;
   case 'a':
 Features.push_back("+a");
 break;
   case 'f':
 Features.push_back("+f");
+hasF = true;
 break;
   case 'd':
 Features.push_back("+d");
+hasD = true;
 break;
   case 'c':
 Features.push_back("+c");
 break;
   }
 }
+
+// Dependency check
+if (hasD && !hasF)
+  D.Diag(diag::err_drv_invalid_arch_name) << MArch;
   }
 }
 
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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng marked 2 inline comments as done.
kito-cheng added inline comments.



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:48
+  break;
+default:
+  // First letter should be 'i' or 'g'.

apazos wrote:
> In the switch cases move default to first position.
Done :)



Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:60
   case 'm':
 Features.push_back("+m");
 break;

apazos wrote:
> So the subsequent features can appear in any order?
Yeah, here is a canonical order specified in ISA manual, I've check the order 
now.


Repository:
  rC Clang

https://reviews.llvm.org/D44189



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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng updated this revision to Diff 137547.

Repository:
  rC Clang

https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,29 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
+// RV32IMADF: error: invalid arch name 'rv32imadf'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64 %s
+// RV64: error: invalid arch name 'rv64'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64M %s
+// RV64M: error: invalid arch name 'rv64m'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64ID %s
+// RV64ID: error: invalid arch name 'rv64id'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
+// RV64L: error: invalid arch name 'rv64l'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imadf -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
+// RV64IMADF: error: invalid arch name 'rv64imadf'
Index: lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- lib/Driver/ToolChains/Arch/RISCV.cpp
+++ lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -23,33 +23,82 @@
 void riscv::getRISCVTargetFeatures(const Driver , const ArgList ,
std::vector ) {
   if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
-StringRef MArch = A->getValue();
-// TODO: handle rv64
-std::pair MArchSplit = StringRef(MArch).split("rv32");
-if (!MArchSplit.second.size())
+StringRef March = A->getValue();
+if (!(March.startswith("rv32") || March.startswith("rv64")) ||
+(March.size() < 5)) {
+  // ISA string must begin with rv32 or rv64.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   return;
+}
+
+// The canonical order specified in ISA manual.
+StringRef StdExts = "mafdc";
+
+bool hasF = false, hasD = false;
+char baseline = March[4];
+
+// TODO: Handle 'e' once backend supported.
+switch (baseline) {
+default:
+  // First letter should be 'e', 'i' or 'g'.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
+  return;
+case 'i':
+  break;
+case 'g':
+  // g = imafd
+  StdExts = StdExts.drop_front(4);
+  Features.push_back("+m");
+  Features.push_back("+a");
+  Features.push_back("+f");
+  Features.push_back("+d");
+  hasF = true;
+  hasD = true;
+  break;
+}
 
-for (char c : MArchSplit.second) {
+auto StdExtsItr = StdExts.begin();
+// Skip rvxxx
+StringRef Exts = March.substr(5);
+
+for (char c : Exts) {
+  // Check march is satisfied the canonical order.
+  while (StdExtsItr != StdExts.end() && *StdExtsItr != c)
+ ++StdExtsItr;
+
+  if (StdExtsItr == StdExts.end()) {
+D.Diag(diag::err_drv_invalid_arch_name) << March;
+return;
+  }
+
+  // The order is OK, then push it into features.
   switch (c) {
-  case 'i':
-break;
+  default:
+D.Diag(diag::err_drv_invalid_arch_name) << March;
+return;
   case 'm':
 Features.push_back("+m");
 break;
   case 'a':
 Features.push_back("+a");
 break;
   case 'f':
 Features.push_back("+f");
+hasF = true;
 break;
   case 'd':
 Features.push_back("+d");
+hasD = true;
 break;
   case 'c':
 Features.push_back("+c");
 break;
   }
 }
+
+// Dependency check
+if (hasD && !hasF)
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   }
 }
 
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[PATCH] D44189: [RISCV] Verify the input value of -march=

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: cfe-commits, shiva0217, niosHD, sabuasal, 
jordy.potman.lists, simoncook, johnrusso, rbar.

This patch doing more check and verify the -march= string and will issue and 
error if it's a invalid combination.


Repository:
  rC Clang

https://reviews.llvm.org/D44189

Files:
  lib/Driver/ToolChains/Arch/RISCV.cpp
  test/Driver/riscv-arch.c

Index: test/Driver/riscv-arch.c
===
--- /dev/null
+++ test/Driver/riscv-arch.c
@@ -0,0 +1,23 @@
+// RUN: %clang -target riscv32-unknown-elf -march=rv32 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32 %s
+// RV32: error: invalid arch name 'rv32'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32M %s
+// RV32M: error: invalid arch name 'rv32m'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ID %s
+// RV32ID: error: invalid arch name 'rv32id'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
+// RV32L: error: invalid arch name 'rv32l'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64 -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64 %s
+// RV64: error: invalid arch name 'rv64'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64m -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64M %s
+// RV64M: error: invalid arch name 'rv64m'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64id -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64ID %s
+// RV64ID: error: invalid arch name 'rv64id'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64l -### %s -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
+// RV64L: error: invalid arch name 'rv64l'
Index: lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- lib/Driver/ToolChains/Arch/RISCV.cpp
+++ lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -23,33 +23,65 @@
 void riscv::getRISCVTargetFeatures(const Driver , const ArgList ,
std::vector ) {
   if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
-StringRef MArch = A->getValue();
-// TODO: handle rv64
-std::pair MArchSplit = StringRef(MArch).split("rv32");
-if (!MArchSplit.second.size())
+StringRef March = A->getValue();
+if (!(March.startswith("rv32") || March.startswith("rv64")) ||
+(March.size() < 5)) {
+  // ISA string must begin with rv32 or rv64.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   return;
+}
+
+bool hasF = false, hasD = false;
+char baseline = March[4];
+
+switch (baseline) {
+case 'i':
+  break;
+case 'g':
+  Features.push_back("+m");
+  Features.push_back("+a");
+  Features.push_back("+f");
+  Features.push_back("+d");
+  hasF = true;
+  hasD = true;
+  break;
+default:
+  // First letter should be 'i' or 'g'.
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
+  break;
+}
 
-for (char c : MArchSplit.second) {
+// Skip rvxxx
+StringRef Exts = March.substr(5);
+
+for (char c : Exts) {
   switch (c) {
-  case 'i':
-break;
   case 'm':
 Features.push_back("+m");
 break;
   case 'a':
 Features.push_back("+a");
 break;
   case 'f':
 Features.push_back("+f");
+hasF = true;
 break;
   case 'd':
 Features.push_back("+d");
+hasD = true;
 break;
   case 'c':
 Features.push_back("+c");
 break;
+  default:
+D.Diag(diag::err_drv_invalid_arch_name) << March;
+break;
   }
 }
+
+// Dependency check
+if (hasD && !hasF)
+  D.Diag(diag::err_drv_invalid_arch_name) << March;
   }
 }
 
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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: lib/Basic/Targets/RISCV.h:85
+  bool hasInt128Type(const LangOptions ) const override {
+return Opts.UseInt128;
+  }

efriedma wrote:
> Maybe make this a cross-platform flag, rather than riscv-specific?
+1, then we can make all other 32 bits target to able easier support float128 
too :)


Repository:
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https://reviews.llvm.org/D43105



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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Hi Eli:

> but you want to make int128_t opt-in to avoid the possibility of someone 
> getting a link error trying to link code built with clang against libgcc.a?

Yes, that's the problem we want to avoid, and we actually get the problem if we 
built libc (newlib) with clang/llvm and used by GCC.


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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Hi Eli:

We need that because compiler-rt implement 128 bits soft floating point with 
int128_t, and RISC-V need that but RV32 doesn't support int128_t, we know it's 
can be just return true to support that. but we don't want to bring any ABI 
contemptible issue between GCC and Clang/LLVM. Here is another direction is 
make GCC support int128_t for RV32, but it's hard to support that in GCC for 
all 32 bits target[1].

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=60846


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