r355605 - [analyzer] handle modification of vars inside an expr with comma operator
Author: petarj
Date: Thu Mar 7 07:50:52 2019
New Revision: 355605
URL: http://llvm.org/viewvc/llvm-project?rev=355605=rev
Log:
[analyzer] handle modification of vars inside an expr with comma operator
We should track mutation of a variable within a comma operator expression.
Current code in ExprMutationAnalyzer does not handle it.
This will handle cases like:
(a, b) ++ < == b is modified
(a, b) = c < == b is modifed
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D58894
Modified:
cfe/trunk/include/clang/AST/Expr.h
cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp
cfe/trunk/unittests/Analysis/ExprMutationAnalyzerTest.cpp
Modified: cfe/trunk/include/clang/AST/Expr.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/AST/Expr.h?rev=355605=355604=355605=diff
==
--- cfe/trunk/include/clang/AST/Expr.h (original)
+++ cfe/trunk/include/clang/AST/Expr.h Thu Mar 7 07:50:52 2019
@@ -3403,6 +3403,9 @@ public:
static bool isComparisonOp(Opcode Opc) { return Opc >= BO_Cmp && Opc<=BO_NE;
}
bool isComparisonOp() const { return isComparisonOp(getOpcode()); }
+ static bool isCommaOp(Opcode Opc) { return Opc == BO_Comma; }
+ bool isCommaOp() const { return isCommaOp(getOpcode()); }
+
static Opcode negateComparisonOp(Opcode Opc) {
switch (Opc) {
default:
Modified: cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp?rev=355605=355604=355605=diff
==
--- cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp (original)
+++ cfe/trunk/lib/Analysis/ExprMutationAnalyzer.cpp Thu Mar 7 07:50:52 2019
@@ -24,6 +24,18 @@ AST_MATCHER_P(CXXForRangeStmt, hasRangeS
return InnerMatcher.matches(*Range, Finder, Builder);
}
+AST_MATCHER_P(Expr, maybeEvalCommaExpr,
+ ast_matchers::internal::Matcher, InnerMatcher) {
+ const Expr* Result =
+ while (const auto *BOComma =
+ dyn_cast_or_null(Result->IgnoreParens())) {
+if (!BOComma->isCommaOp())
+ break;
+Result = BOComma->getRHS();
+ }
+ return InnerMatcher.matches(*Result, Finder, Builder);
+}
+
const ast_matchers::internal::VariadicDynCastAllOfMatcher
cxxTypeidExpr;
@@ -193,24 +205,28 @@ const Stmt *ExprMutationAnalyzer::findDe
const Stmt *ExprMutationAnalyzer::findDirectMutation(const Expr *Exp) {
// LHS of any assignment operators.
const auto AsAssignmentLhs =
- binaryOperator(isAssignmentOperator(), hasLHS(equalsNode(Exp)));
+ binaryOperator(isAssignmentOperator(),
+ hasLHS(maybeEvalCommaExpr(equalsNode(Exp;
// Operand of increment/decrement operators.
const auto AsIncDecOperand =
unaryOperator(anyOf(hasOperatorName("++"), hasOperatorName("--")),
-hasUnaryOperand(equalsNode(Exp)));
+hasUnaryOperand(maybeEvalCommaExpr(equalsNode(Exp;
// Invoking non-const member function.
// A member function is assumed to be non-const when it is unresolved.
const auto NonConstMethod = cxxMethodDecl(unless(isConst()));
const auto AsNonConstThis =
- expr(anyOf(cxxMemberCallExpr(callee(NonConstMethod),
on(equalsNode(Exp))),
+ expr(anyOf(cxxMemberCallExpr(callee(NonConstMethod),
+ on(maybeEvalCommaExpr(equalsNode(Exp,
cxxOperatorCallExpr(callee(NonConstMethod),
- hasArgument(0, equalsNode(Exp))),
+ hasArgument(0,
+
maybeEvalCommaExpr(equalsNode(Exp,
callExpr(callee(expr(anyOf(
-
unresolvedMemberExpr(hasObjectExpression(equalsNode(Exp))),
+ unresolvedMemberExpr(
+
hasObjectExpression(maybeEvalCommaExpr(equalsNode(Exp,
cxxDependentScopeMemberExpr(
- hasObjectExpression(equalsNode(Exp);
+
hasObjectExpression(maybeEvalCommaExpr(equalsNode(Exp));
// Taking address of 'Exp'.
// We're assuming 'Exp' is mutated as soon as its address is taken, though in
@@ -220,10 +236,11 @@ const Stmt *ExprMutationAnalyzer::findDi
unaryOperator(hasOperatorName("&"),
// A NoOp implicit cast is adding const.
unless(hasParent(implicitCastExpr(hasCastKind(CK_NoOp,
-hasUnaryOperand(equalsNode(Exp)));
+hasUnaryOperand(maybeEvalCommaExpr(equalsNode(Exp;
const auto AsPointerFromArrayDecay =
castExpr(hasCastKind(CK_ArrayToPointerDecay),
- unless(hasParent(arraySubscriptExpr())), has(equalsNode(Exp)));
+ unless(hasParent(arraySubscriptExpr())),
+
r311669 - [mips] Introducing option -mabs=[legacy/2008]
Author: petarj
Date: Thu Aug 24 09:06:30 2017
New Revision: 311669
URL: http://llvm.org/viewvc/llvm-project?rev=311669=rev
Log:
[mips] Introducing option -mabs=[legacy/2008]
In patch r205628 using abs.[ds] instruction is forced, as they should behave
in accordance with flags Has2008 and ABS2008. Unfortunately for revisions
prior mips32r6 and mips64r6, abs.[ds] is not generating correct result when
working with NaNs. To generate a sequence which always produce a correct
result but also to allow user more control on how his code is compiled,
option -mabs is added where user can choose legacy or 2008.
By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6
use abs2008 mode by default.
Patch by Aleksandar Beserminji
Differential Revision: https://reviews.llvm.org/D35982
Added:
cfe/trunk/test/Driver/mips-mabs-warning.c
Modified:
cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
cfe/trunk/include/clang/Basic/DiagnosticGroups.td
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/Mips.cpp
cfe/trunk/lib/Basic/Targets/Mips.h
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/trunk/test/Driver/mips-features.c
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td?rev=311669=311668=311669=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td Thu Aug 24 09:06:30
2017
@@ -285,6 +285,12 @@ def warn_target_unsupported_nan2008 : Wa
def warn_target_unsupported_nanlegacy : Warning<
"ignoring '-mnan=legacy' option because the '%0' architecture does not
support it">,
InGroup;
+def warn_target_unsupported_abslegacy : Warning<
+ "ignoring '-mabs=legacy' option because the '%0' architecture does not
support it">,
+ InGroup;
+def warn_target_unsupported_abs2008 : Warning<
+ "ignoring '-mabs=2008' option because the '%0' architecture does not support
it">,
+ InGroup;
def warn_target_unsupported_compact_branches : Warning<
"ignoring '-mcompact-branches=' option because the '%0' architecture does
not"
" support it">, InGroup;
Modified: cfe/trunk/include/clang/Basic/DiagnosticGroups.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticGroups.td?rev=311669=311668=311669=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticGroups.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticGroups.td Thu Aug 24 09:06:30 2017
@@ -61,6 +61,7 @@ def FloatConversion :
def DoublePromotion : DiagGroup<"double-promotion">;
def EnumTooLarge : DiagGroup<"enum-too-large">;
def UnsupportedNan : DiagGroup<"unsupported-nan">;
+def UnsupportedAbs : DiagGroup<"unsupported-abs">;
def UnsupportedCB : DiagGroup<"unsupported-cb">;
def UnsupportedGPOpt : DiagGroup<"unsupported-gpopt">;
def NonLiteralNullConversion : DiagGroup<"non-literal-null-conversion">;
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=311669=311668=311669=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Thu Aug 24 09:06:30 2017
@@ -2066,6 +2066,7 @@ def mno_embedded_data : Flag<["-"], "mno
HelpText<"Do not place constants in the .rodata section instead of the "
".sdata if they meet the -G threshold (MIPS)">;
def mnan_EQ : Joined<["-"], "mnan=">, Group;
+def mabs_EQ : Joined<["-"], "mabs=">, Group;
def mabicalls : Flag<["-"], "mabicalls">, Group,
HelpText<"Enable SVR4-style position-independent code (Mips only)">;
def mno_abicalls : Flag<["-"], "mno-abicalls">, Group,
Modified: cfe/trunk/lib/Basic/Targets/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.cpp?rev=311669=311668=311669=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.cpp Thu Aug 24 09:06:30 2017
@@ -149,6 +149,9 @@ void MipsTargetInfo::getTargetDefines(co
if (IsNan2008)
Builder.defineMacro("__mips_nan2008", Twine(1));
+ if (IsAbs2008)
+Builder.defineMacro("__mips_abs2008", Twine(1));
+
switch (DspRev) {
default:
break;
Modified: cfe/trunk/lib/Basic/Targets/Mips.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.h?rev=311669=311668=311669=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.h (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.h Thu Aug 24 09:06:30 2017
@@ -46,6 +46,7 @@ class
r311454 - [mips] Rename getSupportedNanEncoding() to getIEEE754Standard()
Author: petarj
Date: Tue Aug 22 06:35:27 2017
New Revision: 311454
URL: http://llvm.org/viewvc/llvm-project?rev=311454=rev
Log:
[mips] Rename getSupportedNanEncoding() to getIEEE754Standard()
Rename the function getSupportedNanEncoding() to getIEEE754Standard(), since
this function will be used for non-nan related features.
Patch by Aleksandar Beserminji.
Differential Revision: https://reviews.llvm.org/D36824
Modified:
cfe/trunk/lib/Basic/Targets/Mips.h
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h
Modified: cfe/trunk/lib/Basic/Targets/Mips.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.h?rev=311454=311453=311454=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.h (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.h Tue Aug 22 06:35:27 2017
@@ -77,7 +77,7 @@ public:
Triple.getOS() == llvm::Triple::OpenBSD;
}
- bool isNaN2008Default() const {
+ bool isIEEE754_2008Default() const {
return CPU == "mips32r6" || CPU == "mips64r6";
}
@@ -299,7 +299,7 @@ public:
DiagnosticsEngine ) override {
IsMips16 = false;
IsMicromips = false;
-IsNan2008 = isNaN2008Default();
+IsNan2008 = isIEEE754_2008Default();
IsSingleFloat = false;
FloatABI = HardFloat;
DspRev = NoDSP;
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp?rev=311454=311453=311454=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp Tue Aug 22 06:35:27 2017
@@ -265,14 +265,14 @@ void mips::getMIPSTargetFeatures(const D
if (Arg *A = Args.getLastArg(options::OPT_mnan_EQ)) {
StringRef Val = StringRef(A->getValue());
if (Val == "2008") {
- if (mips::getSupportedNanEncoding(CPUName) & mips::Nan2008)
+ if (mips::getIEEE754Standard(CPUName) & mips::Std2008)
Features.push_back("+nan2008");
else {
Features.push_back("-nan2008");
D.Diag(diag::warn_target_unsupported_nan2008) << CPUName;
}
} else if (Val == "legacy") {
- if (mips::getSupportedNanEncoding(CPUName) & mips::NanLegacy)
+ if (mips::getIEEE754Standard(CPUName) & mips::Legacy)
Features.push_back("-nan2008");
else {
Features.push_back("+nan2008");
@@ -323,27 +323,28 @@ void mips::getMIPSTargetFeatures(const D
AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt,
"mt");
}
-mips::NanEncoding mips::getSupportedNanEncoding(StringRef ) {
- // Strictly speaking, mips32r2 and mips64r2 are NanLegacy-only since Nan2008
- // was first introduced in Release 3. However, other compilers have
- // traditionally allowed it for Release 2 so we should do the same.
- return (NanEncoding)llvm::StringSwitch(CPU)
- .Case("mips1", NanLegacy)
- .Case("mips2", NanLegacy)
- .Case("mips3", NanLegacy)
- .Case("mips4", NanLegacy)
- .Case("mips5", NanLegacy)
- .Case("mips32", NanLegacy)
- .Case("mips32r2", NanLegacy | Nan2008)
- .Case("mips32r3", NanLegacy | Nan2008)
- .Case("mips32r5", NanLegacy | Nan2008)
- .Case("mips32r6", Nan2008)
- .Case("mips64", NanLegacy)
- .Case("mips64r2", NanLegacy | Nan2008)
- .Case("mips64r3", NanLegacy | Nan2008)
- .Case("mips64r5", NanLegacy | Nan2008)
- .Case("mips64r6", Nan2008)
- .Default(NanLegacy);
+mips::IEEE754Standard mips::getIEEE754Standard(StringRef ) {
+ // Strictly speaking, mips32r2 and mips64r2 do not conform to the
+ // IEEE754-2008 standard. Support for this standard was first introduced
+ // in Release 3. However, other compilers have traditionally allowed it
+ // for Release 2 so we should do the same.
+ return (IEEE754Standard)llvm::StringSwitch(CPU)
+ .Case("mips1", Legacy)
+ .Case("mips2", Legacy)
+ .Case("mips3", Legacy)
+ .Case("mips4", Legacy)
+ .Case("mips5", Legacy)
+ .Case("mips32", Legacy)
+ .Case("mips32r2", Legacy | Std2008)
+ .Case("mips32r3", Legacy | Std2008)
+ .Case("mips32r5", Legacy | Std2008)
+ .Case("mips32r6", Std2008)
+ .Case("mips64", Legacy)
+ .Case("mips64r2", Legacy | Std2008)
+ .Case("mips64r3", Legacy | Std2008)
+ .Case("mips64r5", Legacy | Std2008)
+ .Case("mips64r6", Std2008)
+ .Default(Std2008);
}
bool mips::hasCompactBranches(StringRef ) {
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h?rev=311454=311453=311454=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.h (original)
+++
r306280 - [mips] Enable IAS by default for Android 64-bit MIPS target (N64)
Author: petarj Date: Mon Jun 26 02:58:01 2017 New Revision: 306280 URL: http://llvm.org/viewvc/llvm-project?rev=306280=rev Log: [mips] Enable IAS by default for Android 64-bit MIPS target (N64) IAS is already used for MIPS64 in majority of Android projects. Android MIPS64 uses N64 ABI. Set IAS as a default now. Differential Revision: https://reviews.llvm.org/D34514 Modified: cfe/trunk/lib/Driver/ToolChains/Gnu.cpp Modified: cfe/trunk/lib/Driver/ToolChains/Gnu.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Gnu.cpp?rev=306280=306279=306280=diff == --- cfe/trunk/lib/Driver/ToolChains/Gnu.cpp (original) +++ cfe/trunk/lib/Driver/ToolChains/Gnu.cpp Mon Jun 26 02:58:01 2017 @@ -2338,9 +2338,11 @@ bool Generic_GCC::IsIntegratedAssemblerD return true; case llvm::Triple::mips64: case llvm::Triple::mips64el: -// Enabled for Debian mips64/mips64el only. Other targets are unable to -// distinguish N32 from N64. -if (getTriple().getEnvironment() == llvm::Triple::GNUABI64) +// Enabled for Debian and Android mips64/mipsel, as they can precisely +// identify the ABI in use (Debian) or only use N64 for MIPS64 (Android). +// Other targets are unable to distinguish N32 from N64. +if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 || +getTriple().isAndroid()) return true; return false; default: ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
RE: r304935 - Revert r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
I reverted the patch too quickly and have not noticed the file was not
actually deleted. I am reapplying the patch with minor modifications now,
hopefully no issues this time.
Thanks.
Regards,
Petar
From: Simon Dardis
Sent: Wednesday, June 07, 2017 10:36 PM
To: Evgenii Stepanov; Petar Jovanovic
Cc: cfe-commits
Subject: RE: r304935 - Revert r304929 [mips] Add runtime options to
enable/disable madd/sub.fmt
Appears to be fixed, r304936. I'll keep an eye on the buildbots.
Thanks,
Simon
From: cfe-commits [cfe-commits-boun...@lists.llvm.org] on behalf of Evgenii
Stepanov via cfe-commits [cfe-commits@lists.llvm.org]
Sent: 07 June 2017 20:53
To: Petar Jovanovic
Cc: cfe-commits
Subject: Re: r304935 - Revert r304929 [mips] Add runtime options to
enable/disable madd/sub.fmt
You've left an empty file in test/CodeGen/mips-madd4.c
On Wed, Jun 7, 2017 at 11:57 AM, Petar Jovanovic via cfe-commits
<cfe-commits@lists.llvm.org> wrote:
> Author: petarj
> Date: Wed Jun 7 13:57:56 2017
> New Revision: 304935
>
> URL: http://llvm.org/viewvc/llvm-project?rev=304935=rev
> Log:
> Revert r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
>
> Revert r304929 since the test broke buildbots.
>
> Original commit:
>
> [mips] Add runtime options to enable/disable madd.fmt and msub.fmt
>
> Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable
> generation of madd.fmt and similar instructions respectively, as per GCC.
>
> Patch by Stefan Maksimovic.
>
> Modified:
> cfe/trunk/include/clang/Driver/Options.td
> cfe/trunk/lib/Basic/Targets.cpp
> cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
> cfe/trunk/test/CodeGen/mips-madd4.c
> cfe/trunk/test/Preprocessor/init.c
>
> Modified: cfe/trunk/include/clang/Driver/Options.td
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=304935=304934=304935=diff
> ==
> --- cfe/trunk/include/clang/Driver/Options.td (original)
> +++ cfe/trunk/include/clang/Driver/Options.td Wed Jun 7 13:57:56 2017
> @@ -2001,10 +2001,6 @@ def mdspr2 : Flag<["-"], "mdspr2">, Grou
> def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
> def msingle_float : Flag<["-"], "msingle-float">, Group;
> def mdouble_float : Flag<["-"], "mdouble-float">, Group;
> -def mmadd4 : Flag<["-"], "mmadd4">, Group,
> - HelpText<"Enable the generation of 4-operand madd.s, madd.d and related
> instructions.">;
> -def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
> - HelpText<"Disable the generation of 4-operand madd.s, madd.d and related
> instructions.">;
> def mmsa : Flag<["-"], "mmsa">, Group,
>HelpText<"Enable MSA ASE (MIPS only)">;
> def mno_msa : Flag<["-"], "mno-msa">, Group,
>
> Modified: cfe/trunk/lib/Basic/Targets.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304935=304934=304935=diff
> ==
> --- cfe/trunk/lib/Basic/Targets.cpp (original)
> +++ cfe/trunk/lib/Basic/Targets.cpp Wed Jun 7 13:57:56 2017
> @@ -7737,7 +7737,6 @@ class MipsTargetInfo : public TargetInfo
> NoDSP, DSP1, DSP2
>} DspRev;
>bool HasMSA;
> - bool DisableMadd4;
>
> protected:
>bool HasFP64;
> @@ -7748,7 +7747,7 @@ public:
>: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
> IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
> CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
> -HasMSA(false), DisableMadd4(false), HasFP64(false) {
> +HasMSA(false), HasFP64(false) {
> TheCXXABI.set(TargetCXXABI::GenericMIPS);
>
> setABI((getTriple().getArch() == llvm::Triple::mips ||
> @@ -7994,9 +7993,6 @@ public:
> if (HasMSA)
>Builder.defineMacro("__mips_msa", Twine(1));
>
> -if (DisableMadd4)
> - Builder.defineMacro("__mips_no_madd4", Twine(1));
> -
> Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
> Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
> Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
> @@ -8159,8 +8155,6 @@ public:
> DspRev = std::max(DspRev, DSP2);
>else if (Feature == "+msa")
> HasMSA = true;
> - else if (Feature == &qu
r304953 - Reapply r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
Author: petarj
Date: Wed Jun 7 18:51:52 2017
New Revision: 304953
URL: http://llvm.org/viewvc/llvm-project?rev=304953=rev
Log:
Reapply r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
The test in r304929 broke multiple buildbots as it expected mips target to
be registered and available (which is not necessarily true). Updating the
test with this condition.
Original commit:
[mips] Add runtime options to enable/disable madd.fmt and msub.fmt
Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable
generation of madd.fmt and similar instructions respectively, as per GCC.
Patch by Stefan Maksimovic.
Added:
cfe/trunk/test/CodeGen/mips-madd4.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=304953=304952=304953=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Jun 7 18:51:52 2017
@@ -2001,6 +2001,10 @@ def mdspr2 : Flag<["-"], "mdspr2">, Grou
def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
def msingle_float : Flag<["-"], "msingle-float">, Group;
def mdouble_float : Flag<["-"], "mdouble-float">, Group;
+def mmadd4 : Flag<["-"], "mmadd4">, Group,
+ HelpText<"Enable the generation of 4-operand madd.s, madd.d and related
instructions.">;
+def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
+ HelpText<"Disable the generation of 4-operand madd.s, madd.d and related
instructions.">;
def mmsa : Flag<["-"], "mmsa">, Group,
HelpText<"Enable MSA ASE (MIPS only)">;
def mno_msa : Flag<["-"], "mno-msa">, Group,
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304953=304952=304953=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Wed Jun 7 18:51:52 2017
@@ -7737,6 +7737,7 @@ class MipsTargetInfo : public TargetInfo
NoDSP, DSP1, DSP2
} DspRev;
bool HasMSA;
+ bool DisableMadd4;
protected:
bool HasFP64;
@@ -7747,7 +7748,7 @@ public:
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-HasMSA(false), HasFP64(false) {
+HasMSA(false), DisableMadd4(false), HasFP64(false) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI((getTriple().getArch() == llvm::Triple::mips ||
@@ -7993,6 +7994,9 @@ public:
if (HasMSA)
Builder.defineMacro("__mips_msa", Twine(1));
+if (DisableMadd4)
+ Builder.defineMacro("__mips_no_madd4", Twine(1));
+
Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
@@ -8155,6 +8159,8 @@ public:
DspRev = std::max(DspRev, DSP2);
else if (Feature == "+msa")
HasMSA = true;
+ else if (Feature == "+nomadd4")
+DisableMadd4 = true;
else if (Feature == "+fp64")
HasFP64 = true;
else if (Feature == "-fp64")
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp?rev=304953=304952=304953=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp Wed Jun 7 18:51:52 2017
@@ -298,6 +298,13 @@ void mips::getMIPSTargetFeatures(const D
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
+
+ if (Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
+if (A->getOption().matches(options::OPT_mmadd4))
+ Features.push_back("-nomadd4");
+else
+ Features.push_back("+nomadd4");
+ }
}
mips::NanEncoding mips::getSupportedNanEncoding(StringRef ) {
Added: cfe/trunk/test/CodeGen/mips-madd4.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-madd4.c?rev=304953=auto
==
--- cfe/trunk/test/CodeGen/mips-madd4.c (added)
+++ cfe/trunk/test/CodeGen/mips-madd4.c Wed Jun 7 18:51:52 2017
@@ -0,0 +1,87 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4%s -o -| FileCheck
%s -check-prefix=MADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck
%s -check-prefix=NOMADD4
+// RUN:
r304935 - Revert r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
Author: petarj
Date: Wed Jun 7 13:57:56 2017
New Revision: 304935
URL: http://llvm.org/viewvc/llvm-project?rev=304935=rev
Log:
Revert r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
Revert r304929 since the test broke buildbots.
Original commit:
[mips] Add runtime options to enable/disable madd.fmt and msub.fmt
Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable
generation of madd.fmt and similar instructions respectively, as per GCC.
Patch by Stefan Maksimovic.
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/trunk/test/CodeGen/mips-madd4.c
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=304935=304934=304935=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Jun 7 13:57:56 2017
@@ -2001,10 +2001,6 @@ def mdspr2 : Flag<["-"], "mdspr2">, Grou
def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
def msingle_float : Flag<["-"], "msingle-float">, Group;
def mdouble_float : Flag<["-"], "mdouble-float">, Group;
-def mmadd4 : Flag<["-"], "mmadd4">, Group,
- HelpText<"Enable the generation of 4-operand madd.s, madd.d and related
instructions.">;
-def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
- HelpText<"Disable the generation of 4-operand madd.s, madd.d and related
instructions.">;
def mmsa : Flag<["-"], "mmsa">, Group,
HelpText<"Enable MSA ASE (MIPS only)">;
def mno_msa : Flag<["-"], "mno-msa">, Group,
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304935=304934=304935=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Wed Jun 7 13:57:56 2017
@@ -7737,7 +7737,6 @@ class MipsTargetInfo : public TargetInfo
NoDSP, DSP1, DSP2
} DspRev;
bool HasMSA;
- bool DisableMadd4;
protected:
bool HasFP64;
@@ -7748,7 +7747,7 @@ public:
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-HasMSA(false), DisableMadd4(false), HasFP64(false) {
+HasMSA(false), HasFP64(false) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI((getTriple().getArch() == llvm::Triple::mips ||
@@ -7994,9 +7993,6 @@ public:
if (HasMSA)
Builder.defineMacro("__mips_msa", Twine(1));
-if (DisableMadd4)
- Builder.defineMacro("__mips_no_madd4", Twine(1));
-
Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
@@ -8159,8 +8155,6 @@ public:
DspRev = std::max(DspRev, DSP2);
else if (Feature == "+msa")
HasMSA = true;
- else if (Feature == "+nomadd4")
-DisableMadd4 = true;
else if (Feature == "+fp64")
HasFP64 = true;
else if (Feature == "-fp64")
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp?rev=304935=304934=304935=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp Wed Jun 7 13:57:56 2017
@@ -298,13 +298,6 @@ void mips::getMIPSTargetFeatures(const D
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
-
- if (Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
-if (A->getOption().matches(options::OPT_mmadd4))
- Features.push_back("-nomadd4");
-else
- Features.push_back("+nomadd4");
- }
}
mips::NanEncoding mips::getSupportedNanEncoding(StringRef ) {
Modified: cfe/trunk/test/CodeGen/mips-madd4.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-madd4.c?rev=304935=304934=304935=diff
==
--- cfe/trunk/test/CodeGen/mips-madd4.c (original)
+++ cfe/trunk/test/CodeGen/mips-madd4.c Wed Jun 7 13:57:56 2017
@@ -1,86 +0,0 @@
-// RUN: %clang --target=mips64-unknown-linux -S -mmadd4%s -o -| FileCheck
%s -check-prefix=MADD4
-// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck
%s -check-prefix=NOMADD4
-// RUN: %clang --target=mips64-unknown-linux -S -mmadd4-fno-honor-nans %s
-o -| FileCheck %s -check-prefix=MADD4-NONAN
-// RUN: %clang
r304929 - [mips] Add runtime options to enable/disable madd.fmt and msub.fmt
Author: petarj
Date: Wed Jun 7 12:17:57 2017
New Revision: 304929
URL: http://llvm.org/viewvc/llvm-project?rev=304929=rev
Log:
[mips] Add runtime options to enable/disable madd.fmt and msub.fmt
Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable
generation of madd.fmt and similar instructions respectively, as per GCC.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D33401
Added:
cfe/trunk/test/CodeGen/mips-madd4.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=304929=304928=304929=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Jun 7 12:17:57 2017
@@ -2001,6 +2001,10 @@ def mdspr2 : Flag<["-"], "mdspr2">, Grou
def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
def msingle_float : Flag<["-"], "msingle-float">, Group;
def mdouble_float : Flag<["-"], "mdouble-float">, Group;
+def mmadd4 : Flag<["-"], "mmadd4">, Group,
+ HelpText<"Enable the generation of 4-operand madd.s, madd.d and related
instructions.">;
+def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
+ HelpText<"Disable the generation of 4-operand madd.s, madd.d and related
instructions.">;
def mmsa : Flag<["-"], "mmsa">, Group,
HelpText<"Enable MSA ASE (MIPS only)">;
def mno_msa : Flag<["-"], "mno-msa">, Group,
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304929=304928=304929=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Wed Jun 7 12:17:57 2017
@@ -7737,6 +7737,7 @@ class MipsTargetInfo : public TargetInfo
NoDSP, DSP1, DSP2
} DspRev;
bool HasMSA;
+ bool DisableMadd4;
protected:
bool HasFP64;
@@ -7747,7 +7748,7 @@ public:
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-HasMSA(false), HasFP64(false) {
+HasMSA(false), DisableMadd4(false), HasFP64(false) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI((getTriple().getArch() == llvm::Triple::mips ||
@@ -7993,6 +7994,9 @@ public:
if (HasMSA)
Builder.defineMacro("__mips_msa", Twine(1));
+if (DisableMadd4)
+ Builder.defineMacro("__mips_no_madd4", Twine(1));
+
Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
@@ -8155,6 +8159,8 @@ public:
DspRev = std::max(DspRev, DSP2);
else if (Feature == "+msa")
HasMSA = true;
+ else if (Feature == "+nomadd4")
+DisableMadd4 = true;
else if (Feature == "+fp64")
HasFP64 = true;
else if (Feature == "-fp64")
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp?rev=304929=304928=304929=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp Wed Jun 7 12:17:57 2017
@@ -298,6 +298,13 @@ void mips::getMIPSTargetFeatures(const D
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
+
+ if (Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
+if (A->getOption().matches(options::OPT_mmadd4))
+ Features.push_back("-nomadd4");
+else
+ Features.push_back("+nomadd4");
+ }
}
mips::NanEncoding mips::getSupportedNanEncoding(StringRef ) {
Added: cfe/trunk/test/CodeGen/mips-madd4.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-madd4.c?rev=304929=auto
==
--- cfe/trunk/test/CodeGen/mips-madd4.c (added)
+++ cfe/trunk/test/CodeGen/mips-madd4.c Wed Jun 7 12:17:57 2017
@@ -0,0 +1,86 @@
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4%s -o -| FileCheck
%s -check-prefix=MADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck
%s -check-prefix=NOMADD4
+// RUN: %clang --target=mips64-unknown-linux -S -mmadd4-fno-honor-nans %s
-o -| FileCheck %s -check-prefix=MADD4-NONAN
+// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 -fno-honor-nans %s
-o -| FileCheck %s -check-prefix=NOMADD4-NONAN
+
+float madd_s
r302670 - Reland: [mips] Impose a threshold for coercion of aggregates
Author: petarj
Date: Wed May 10 09:28:18 2017
New Revision: 302670
URL: http://llvm.org/viewvc/llvm-project?rev=302670=rev
Log:
Reland: [mips] Impose a threshold for coercion of aggregates
Modified MipsABIInfo::classifyArgumentType so that it now coerces
aggregate structures only if the size of said aggregate is less than
16/64 bytes, depending on the ABI.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D32900
with minor changes (use regexp instead of the hardcoded values) to the test.
Added:
cfe/trunk/test/CodeGen/mips-aggregate-arg.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=302670=302669=302670=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Wed May 10 09:28:18 2017
@@ -6693,6 +6693,14 @@ MipsABIInfo::classifyArgumentType(QualTy
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) >
CharUnits::fromQuantity(Threshold))
+ return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 >
Align);
+
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
Added: cfe/trunk/test/CodeGen/mips-aggregate-arg.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-aggregate-arg.c?rev=302670=auto
==
--- cfe/trunk/test/CodeGen/mips-aggregate-arg.c (added)
+++ cfe/trunk/test/CodeGen/mips-aggregate-arg.c Wed May 10 09:28:18 2017
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s |
FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+ char t1[10];
+};
+
+struct t2 {
+ char t2[20];
+};
+
+struct t3 {
+ char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32: call void @f1(i32 inreg %{{[0-9]+}}, i32 inreg %{{[0-9]+}}, i16 inreg
%{{[0-9]+}})
+// O32: call void @f2(%struct.t2* byval align 4 %{{.*}})
+// O32: call void @f3(%struct.t3* byval align 4 %{{.*}})
+
+// N32-N64: call void @f1(i64 inreg %{{[0-9]+}}, i16 inreg %{{[0-9]+}})
+// N32-N64: call void @f2(i64 inreg %{{[0-9]+}}, i64 inreg %{{[0-9]+}}, i32
inreg %{{[0-9]+}})
+// N32-N64: call void @f3(%struct.t3* byval align 8 %{{.*}})
+
+ f1(g1);
+ f2(g2);
+ f3(g3);
+}
+
___
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RE: r302547 - [mips] Impose a threshold for coercion of aggregates
Reverted in r302555. From: hwennb...@google.com [hwennb...@google.com] on behalf of Hans Wennborg [h...@chromium.org] Sent: Tuesday, May 09, 2017 7:18 PM To: Petar Jovanovic Cc: cfe-commits Subject: Re: r302547 - [mips] Impose a threshold for coercion of aggregates On Tue, May 9, 2017 at 9:24 AM, Petar Jovanovic via cfe-commits <cfe-commits@lists.llvm.org> wrote: > Author: petarj > Date: Tue May 9 11:24:03 2017 > New Revision: 302547 > > URL: http://llvm.org/viewvc/llvm-project?rev=302547=rev > Log: > [mips] Impose a threshold for coercion of aggregates > > Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate > structures only if the size of said aggregate is less than 16/64 bytes, > depending on the ABI. > > Patch by Stefan Maksimovic. > > Differential Revision: https://reviews.llvm.org/D32900 > > Added: > cfe/trunk/test/CodeGen/mips-aggregate-arg.c > Modified: > cfe/trunk/lib/CodeGen/TargetInfo.cpp Looks like a test is failing due to this: http://bb.pgr.jp/builders/test-clang-x86_64-linux-R/builds/1932/steps/test_clang/logs/Clang%20%3A%3A%20CodeGen__mips-aggregate-arg.c ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r302555 - Revert r302547 ([mips] Impose a threshold for coercion of aggregates)
Author: petarj
Date: Tue May 9 12:20:06 2017
New Revision: 302555
URL: http://llvm.org/viewvc/llvm-project?rev=302555=rev
Log:
Revert r302547 ([mips] Impose a threshold for coercion of aggregates)
Reverting
Modified MipsABIInfo::classifyArgumentType so that it now coerces
aggregate structures only if the size of said aggregate is less than 16/64
bytes, depending on the ABI.
as it broke clang-with-lto-ubuntu builder.
Removed:
cfe/trunk/test/CodeGen/mips-aggregate-arg.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=302555=302554=302555=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Tue May 9 12:20:06 2017
@@ -6695,14 +6695,6 @@ MipsABIInfo::classifyArgumentType(QualTy
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
-// Use indirect if the aggregate cannot fit into registers for
-// passing arguments according to the ABI
-unsigned Threshold = IsO32 ? 16 : 64;
-
-if(getContext().getTypeSizeInChars(Ty) >
CharUnits::fromQuantity(Threshold))
- return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
- getContext().getTypeAlign(Ty) / 8 >
Align);
-
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
Removed: cfe/trunk/test/CodeGen/mips-aggregate-arg.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-aggregate-arg.c?rev=302554=auto
==
--- cfe/trunk/test/CodeGen/mips-aggregate-arg.c (original)
+++ cfe/trunk/test/CodeGen/mips-aggregate-arg.c (removed)
@@ -1,38 +0,0 @@
-// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s |
FileCheck -check-prefix=O32 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n64 | FileCheck -check-prefix=N32-N64 %s
-
-struct t1 {
- char t1[10];
-};
-
-struct t2 {
- char t2[20];
-};
-
-struct t3 {
- char t3[65];
-};
-
-extern struct t1 g1;
-extern struct t2 g2;
-extern struct t3 g3;
-extern void f1(struct t1);
-extern void f2(struct t2);
-extern void f3(struct t3);
-
-void f() {
-
-// O32: call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
-// O32: call void @f2(%struct.t2* byval align 4 %tmp)
-// O32: call void @f3(%struct.t3* byval align 4 %tmp1)
-
-// N32-N64: call void @f1(i64 inreg %3, i16 inreg %5)
-// N32-N64: call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
-// N32-N64: call void @f3(%struct.t3* byval align 8 %tmp)
-
- f1(g1);
- f2(g2);
- f3(g3);
-}
-
___
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r302547 - [mips] Impose a threshold for coercion of aggregates
Author: petarj
Date: Tue May 9 11:24:03 2017
New Revision: 302547
URL: http://llvm.org/viewvc/llvm-project?rev=302547=rev
Log:
[mips] Impose a threshold for coercion of aggregates
Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate
structures only if the size of said aggregate is less than 16/64 bytes,
depending on the ABI.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D32900
Added:
cfe/trunk/test/CodeGen/mips-aggregate-arg.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=302547=302546=302547=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Tue May 9 11:24:03 2017
@@ -6695,6 +6695,14 @@ MipsABIInfo::classifyArgumentType(QualTy
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
+// Use indirect if the aggregate cannot fit into registers for
+// passing arguments according to the ABI
+unsigned Threshold = IsO32 ? 16 : 64;
+
+if(getContext().getTypeSizeInChars(Ty) >
CharUnits::fromQuantity(Threshold))
+ return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
+ getContext().getTypeAlign(Ty) / 8 >
Align);
+
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
Added: cfe/trunk/test/CodeGen/mips-aggregate-arg.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-aggregate-arg.c?rev=302547=auto
==
--- cfe/trunk/test/CodeGen/mips-aggregate-arg.c (added)
+++ cfe/trunk/test/CodeGen/mips-aggregate-arg.c Tue May 9 11:24:03 2017
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s |
FileCheck -check-prefix=O32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n64 | FileCheck -check-prefix=N32-N64 %s
+
+struct t1 {
+ char t1[10];
+};
+
+struct t2 {
+ char t2[20];
+};
+
+struct t3 {
+ char t3[65];
+};
+
+extern struct t1 g1;
+extern struct t2 g2;
+extern struct t3 g3;
+extern void f1(struct t1);
+extern void f2(struct t2);
+extern void f3(struct t3);
+
+void f() {
+
+// O32: call void @f1(i32 inreg %3, i32 inreg %5, i16 inreg %7)
+// O32: call void @f2(%struct.t2* byval align 4 %tmp)
+// O32: call void @f3(%struct.t3* byval align 4 %tmp1)
+
+// N32-N64: call void @f1(i64 inreg %3, i16 inreg %5)
+// N32-N64: call void @f2(i64 inreg %9, i64 inreg %11, i32 inreg %13)
+// N32-N64: call void @f3(%struct.t3* byval align 8 %tmp)
+
+ f1(g1);
+ f2(g2);
+ f3(g3);
+}
+
___
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r299229 - [mips][msa] Range adjustment for ldi_b builtin function operand
Author: petarj
Date: Fri Mar 31 11:16:43 2017
New Revision: 299229
URL: http://llvm.org/viewvc/llvm-project?rev=299229=rev
Log:
[mips][msa] Range adjustment for ldi_b builtin function operand
Reasoning behind this change was allowing the function to accept all values
from range [-128, 255] since all of them can be encoded in an 8bit wide
value.
This differs from the prior state where only range [-128, 127] was accepted,
where values were assumed to be signed, whereas now the actual
interpretation of the immediate is deferred to the consumer as required.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D31082
Modified:
cfe/trunk/lib/Sema/SemaChecking.cpp
cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
cfe/trunk/test/CodeGen/builtins-mips-msa.c
Modified: cfe/trunk/lib/Sema/SemaChecking.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaChecking.cpp?rev=299229=299228=299229=diff
==
--- cfe/trunk/lib/Sema/SemaChecking.cpp (original)
+++ cfe/trunk/lib/Sema/SemaChecking.cpp Fri Mar 31 11:16:43 2017
@@ -1640,7 +1640,7 @@ bool Sema::CheckMipsBuiltinFunctionCall(
case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
// Memory offsets and immediate loads.
// These intrinsics take a signed 10 bit immediate.
- case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;
+ case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
case Mips::BI__builtin_msa_ldi_h:
case Mips::BI__builtin_msa_ldi_w:
case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
Modified: cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-mips-msa-error.c?rev=299229=299228=299229=diff
==
--- cfe/trunk/test/CodeGen/builtins-mips-msa-error.c (original)
+++ cfe/trunk/test/CodeGen/builtins-mips-msa-error.c Fri Mar 31 11:16:43 2017
@@ -119,7 +119,7 @@ void test(void) {
v4i32_r = __msa_ld_w(_a, 512); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(_a, 512); // expected-error
{{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(512);// expected-error
{{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(256);// expected-error
{{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(512);// expected-error
{{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(512);// expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(512);// expected-error
{{argument should be a value from -512 to 511}}
@@ -310,7 +310,7 @@ void test(void) {
v4i32_r = __msa_ld_w(_a, -513); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(_a, -513); // expected-error
{{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(-513); // expected-error
{{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(-129); // expected-error
{{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(-513); // expected-error
{{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(-513); // expected-error
{{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(-513); // expected-error
{{argument should be a value from -512 to 511}}
Modified: cfe/trunk/test/CodeGen/builtins-mips-msa.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-mips-msa.c?rev=299229=299228=299229=diff
==
--- cfe/trunk/test/CodeGen/builtins-mips-msa.c (original)
+++ cfe/trunk/test/CodeGen/builtins-mips-msa.c Fri Mar 31 11:16:43 2017
@@ -526,6 +526,8 @@ void test(void) {
v2i64_r = __msa_ld_d(_a, 96); // CHECK: call <2 x i64>
@llvm.mips.ld.d(
v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(255); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
v8i16_r = __msa_ldi_h(3); // CHECK: call <8 x i16> @llvm.mips.ldi.h(
v4i32_r = __msa_ldi_w(3); // CHECK: call <4 x i32> @llvm.mips.ldi.w(
v2i64_r = __msa_ldi_d(3); // CHECK: call <2 x i64> @llvm.mips.ldi.d(
___
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r297485 - [mips][msa] Remove range checks for non-immediate sld.[bhwd] instructions
Author: petarj
Date: Fri Mar 10 11:51:01 2017
New Revision: 297485
URL: http://llvm.org/viewvc/llvm-project?rev=297485=rev
Log:
[mips][msa] Remove range checks for non-immediate sld.[bhwd] instructions
Removes immediate range checks for these instructions, since they have GPR
rt as their input operand.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D30693
Modified:
cfe/trunk/lib/Sema/SemaChecking.cpp
cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
cfe/trunk/test/CodeGen/builtins-mips-msa.c
Modified: cfe/trunk/lib/Sema/SemaChecking.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaChecking.cpp?rev=297485=297484=297485=diff
==
--- cfe/trunk/lib/Sema/SemaChecking.cpp (original)
+++ cfe/trunk/lib/Sema/SemaChecking.cpp Fri Mar 10 11:51:01 2017
@@ -1619,28 +1619,24 @@ bool Sema::CheckMipsBuiltinFunctionCall(
case Mips::BI__builtin_msa_copy_u_b:
case Mips::BI__builtin_msa_insve_b:
case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;
- case Mips::BI__builtin_msa_sld_b:
case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;
// These intrinsics take an unsigned 3 bit immediate.
case Mips::BI__builtin_msa_copy_s_h:
case Mips::BI__builtin_msa_copy_u_h:
case Mips::BI__builtin_msa_insve_h:
case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;
- case Mips::BI__builtin_msa_sld_h:
case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;
// These intrinsics take an unsigned 2 bit immediate.
case Mips::BI__builtin_msa_copy_s_w:
case Mips::BI__builtin_msa_copy_u_w:
case Mips::BI__builtin_msa_insve_w:
case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;
- case Mips::BI__builtin_msa_sld_w:
case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;
// These intrinsics take an unsigned 1 bit immediate.
case Mips::BI__builtin_msa_copy_s_d:
case Mips::BI__builtin_msa_copy_u_d:
case Mips::BI__builtin_msa_insve_d:
case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break;
- case Mips::BI__builtin_msa_sld_d:
case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
// Memory offsets and immediate loads.
// These intrinsics take a signed 10 bit immediate.
Modified: cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-mips-msa-error.c?rev=297485=297484=297485=diff
==
--- cfe/trunk/test/CodeGen/builtins-mips-msa-error.c (original)
+++ cfe/trunk/test/CodeGen/builtins-mips-msa-error.c Fri Mar 10 11:51:01 2017
@@ -162,11 +162,6 @@ void test(void) {
v8i16_r = __msa_shf_h(v8i16_a, 256); // CHECK: warning:
argument should be a value from 0 to 255}}
v4i32_r = __msa_shf_w(v4i32_a, 256); // CHECK: warning:
argument should be a value from 0 to 255}}
- v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16); // expected-error
{{argument should be a value from 0 to 15}}
- v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8); // expected-error
{{argument should be a value from 0 to 7}}
- v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4); // expected-error
{{argument should be a value from 0 to 3}}
- v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2); // expected-error
{{argument should be a value from 0 to 1}}
-
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 16); // expected-error
{{argument should be a value from 0 to 15}}
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 8); // expected-error
{{argument should be a value from 0 to 7}}
v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 4); // expected-error
{{argument should be a value from 0 to 3}}
@@ -358,11 +353,6 @@ void test(void) {
v8i16_r = __msa_shf_h(v8i16_a, -1);// CHECK: warning:
argument should be a value from 0 to 255}}
v4i32_r = __msa_shf_w(v4i32_a, -1);// CHECK: warning:
argument should be a value from 0 to 255}}
- v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, -17); // expected-error
{{argument should be a value from 0 to 15}}
- v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, -8); // expected-error
{{argument should be a value from 0 to 7}}
- v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, -4); // expected-error
{{argument should be a value from 0 to 3}}
- v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, -2); // expected-error
{{argument should be a value from 0 to 1}}
-
v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, -17); // expected-error
{{argument should be a value from 0 to 15}}
v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, -8); // expected-error
{{argument should be a value from 0 to 7}}
v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, -4); // expected-error
{{argument should be a value from 0 to 3}}
Modified: cfe/trunk/test/CodeGen/builtins-mips-msa.c
URL:
Re: [PATCH] D20345: [Mips] Finetuning MIPS32 Android default variants
This revision was automatically updated to reflect the committed changes.
Closed by commit rL269914: [Mips] Finetuning MIPS32 Android default variants
(authored by petarj).
Changed prior to commit:
http://reviews.llvm.org/D20345?vs=57543=57603#toc
Repository:
rL LLVM
http://reviews.llvm.org/D20345
Files:
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/lib/Driver/Tools.h
cfe/trunk/test/Driver/clang-translation.c
Index: cfe/trunk/test/Driver/clang-translation.c
===
--- cfe/trunk/test/Driver/clang-translation.c
+++ cfe/trunk/test/Driver/clang-translation.c
@@ -246,8 +246,19 @@
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
// MIPSEL-ANDROID: "-target-cpu" "mips32"
+// MIPSEL-ANDROID: "-target-feature" "+fpxx"
+// MIPSEL-ANDROID: "-target-feature" "+nooddspreg"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
+// RUN: %clang -target mipsel-linux-android -### -S %s -mcpu=mips32r6 2>&1 | \
+// RUN: FileCheck -check-prefix=MIPSEL-ANDROID-R6 %s
+// MIPSEL-ANDROID-R6: clang
+// MIPSEL-ANDROID-R6: "-cc1"
+// MIPSEL-ANDROID-R6: "-target-cpu" "mips32r6"
+// MIPSEL-ANDROID-R6: "-target-feature" "+fp64"
+// MIPSEL-ANDROID-R6: "-target-feature" "+nooddspreg"
+// MIPSEL-ANDROID-R6: "-mfloat-abi" "hard"
+
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
// RUN: FileCheck -check-prefix=MIPS64 %s
// MIPS64: clang
Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -1359,8 +1359,9 @@
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
- // Add the last -mfp32/-mfpxx/-mfp64 or if none are given and the ABI is O32
- // pass -mfpxx
+ // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
+ // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
+ // nooddspreg.
if (Arg *A = Args.getLastArg(options::OPT_mfp32, options::OPT_mfpxx,
options::OPT_mfp64)) {
if (A->getOption().matches(options::OPT_mfp32))
@@ -1373,6 +1374,9 @@
} else if (mips::shouldUseFPXX(Args, Triple, CPUName, ABIName, FloatABI)) {
Features.push_back(Args.MakeArgString("+fpxx"));
Features.push_back(Args.MakeArgString("+nooddspreg"));
+ } else if (mips::isFP64ADefault(Triple, CPUName)) {
+Features.push_back(Args.MakeArgString("+fp64"));
+Features.push_back(Args.MakeArgString("+nooddspreg"));
}
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
@@ -7039,10 +7043,21 @@
return false;
}
+bool mips::isFP64ADefault(const llvm::Triple , StringRef CPUName) {
+ if (!Triple.isAndroid())
+return false;
+
+ // Android MIPS32R6 defaults to FP64A.
+ return llvm::StringSwitch(CPUName)
+ .Case("mips32r6", true)
+ .Default(false);
+}
+
bool mips::isFPXXDefault(const llvm::Triple , StringRef CPUName,
StringRef ABIName, mips::FloatABI FloatABI) {
if (Triple.getVendor() != llvm::Triple::ImaginationTechnologies &&
- Triple.getVendor() != llvm::Triple::MipsTechnologies)
+ Triple.getVendor() != llvm::Triple::MipsTechnologies &&
+ !Triple.isAndroid())
return false;
if (ABIName != "32")
Index: cfe/trunk/lib/Driver/Tools.h
===
--- cfe/trunk/lib/Driver/Tools.h
+++ cfe/trunk/lib/Driver/Tools.h
@@ -299,6 +299,7 @@
bool hasMipsAbiArg(const llvm::opt::ArgList , const char *Value);
bool isUCLibc(const llvm::opt::ArgList );
bool isNaN2008(const llvm::opt::ArgList , const llvm::Triple );
+bool isFP64ADefault(const llvm::Triple , StringRef CPUName);
bool isFPXXDefault(const llvm::Triple , StringRef CPUName,
StringRef ABIName, mips::FloatABI FloatABI);
bool shouldUseFPXX(const llvm::opt::ArgList , const llvm::Triple ,
Index: cfe/trunk/test/Driver/clang-translation.c
===
--- cfe/trunk/test/Driver/clang-translation.c
+++ cfe/trunk/test/Driver/clang-translation.c
@@ -246,8 +246,19 @@
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
// MIPSEL-ANDROID: "-target-cpu" "mips32"
+// MIPSEL-ANDROID: "-target-feature" "+fpxx"
+// MIPSEL-ANDROID: "-target-feature" "+nooddspreg"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
+// RUN: %clang -target mipsel-linux-android -### -S %s -mcpu=mips32r6 2>&1 | \
+// RUN: FileCheck -check-prefix=MIPSEL-ANDROID-R6 %s
+// MIPSEL-ANDROID-R6: clang
+// MIPSEL-ANDROID-R6: "-cc1"
+// MIPSEL-ANDROID-R6: "-target-cpu" "mips32r6"
+// MIPSEL-ANDROID-R6: "-target-feature" "+fp64"
+// MIPSEL-ANDROID-R6: "-target-feature" "+nooddspreg"
+// MIPSEL-ANDROID-R6: "-mfloat-abi" "hard"
+
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
// RUN: FileCheck -check-prefix=MIPS64 %s
// MIPS64: clang
Index: cfe/trunk/lib/Driver/Tools.cpp
r269914 - [Mips] Finetuning MIPS32 Android default variants
Author: petarj
Date: Wed May 18 07:46:06 2016
New Revision: 269914
URL: http://llvm.org/viewvc/llvm-project?rev=269914=rev
Log:
[Mips] Finetuning MIPS32 Android default variants
MIPS32 Android defaults to FPXX ("-fpxx").
MIPS32R6 Android defaults to FP64A ("-mfp64 -mno-odd-spreg").
Differential Revision: http://reviews.llvm.org/D20345
Modified:
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/lib/Driver/Tools.h
cfe/trunk/test/Driver/clang-translation.c
Modified: cfe/trunk/lib/Driver/Tools.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=269914=269913=269914=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Wed May 18 07:46:06 2016
@@ -1359,8 +1359,9 @@ static void getMIPSTargetFeatures(const
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
- // Add the last -mfp32/-mfpxx/-mfp64 or if none are given and the ABI is O32
- // pass -mfpxx
+ // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
+ // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
+ // nooddspreg.
if (Arg *A = Args.getLastArg(options::OPT_mfp32, options::OPT_mfpxx,
options::OPT_mfp64)) {
if (A->getOption().matches(options::OPT_mfp32))
@@ -1373,6 +1374,9 @@ static void getMIPSTargetFeatures(const
} else if (mips::shouldUseFPXX(Args, Triple, CPUName, ABIName, FloatABI)) {
Features.push_back(Args.MakeArgString("+fpxx"));
Features.push_back(Args.MakeArgString("+nooddspreg"));
+ } else if (mips::isFP64ADefault(Triple, CPUName)) {
+Features.push_back(Args.MakeArgString("+fp64"));
+Features.push_back(Args.MakeArgString("+nooddspreg"));
}
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
@@ -7039,10 +7043,21 @@ bool mips::isNaN2008(const ArgList
return false;
}
+bool mips::isFP64ADefault(const llvm::Triple , StringRef CPUName) {
+ if (!Triple.isAndroid())
+return false;
+
+ // Android MIPS32R6 defaults to FP64A.
+ return llvm::StringSwitch(CPUName)
+ .Case("mips32r6", true)
+ .Default(false);
+}
+
bool mips::isFPXXDefault(const llvm::Triple , StringRef CPUName,
StringRef ABIName, mips::FloatABI FloatABI) {
if (Triple.getVendor() != llvm::Triple::ImaginationTechnologies &&
- Triple.getVendor() != llvm::Triple::MipsTechnologies)
+ Triple.getVendor() != llvm::Triple::MipsTechnologies &&
+ !Triple.isAndroid())
return false;
if (ABIName != "32")
Modified: cfe/trunk/lib/Driver/Tools.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.h?rev=269914=269913=269914=diff
==
--- cfe/trunk/lib/Driver/Tools.h (original)
+++ cfe/trunk/lib/Driver/Tools.h Wed May 18 07:46:06 2016
@@ -299,6 +299,7 @@ std::string getMipsABILibSuffix(const ll
bool hasMipsAbiArg(const llvm::opt::ArgList , const char *Value);
bool isUCLibc(const llvm::opt::ArgList );
bool isNaN2008(const llvm::opt::ArgList , const llvm::Triple );
+bool isFP64ADefault(const llvm::Triple , StringRef CPUName);
bool isFPXXDefault(const llvm::Triple , StringRef CPUName,
StringRef ABIName, mips::FloatABI FloatABI);
bool shouldUseFPXX(const llvm::opt::ArgList , const llvm::Triple ,
Modified: cfe/trunk/test/Driver/clang-translation.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/clang-translation.c?rev=269914=269913=269914=diff
==
--- cfe/trunk/test/Driver/clang-translation.c (original)
+++ cfe/trunk/test/Driver/clang-translation.c Wed May 18 07:46:06 2016
@@ -246,8 +246,19 @@
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
// MIPSEL-ANDROID: "-target-cpu" "mips32"
+// MIPSEL-ANDROID: "-target-feature" "+fpxx"
+// MIPSEL-ANDROID: "-target-feature" "+nooddspreg"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
+// RUN: %clang -target mipsel-linux-android -### -S %s -mcpu=mips32r6 2>&1 | \
+// RUN: FileCheck -check-prefix=MIPSEL-ANDROID-R6 %s
+// MIPSEL-ANDROID-R6: clang
+// MIPSEL-ANDROID-R6: "-cc1"
+// MIPSEL-ANDROID-R6: "-target-cpu" "mips32r6"
+// MIPSEL-ANDROID-R6: "-target-feature" "+fp64"
+// MIPSEL-ANDROID-R6: "-target-feature" "+nooddspreg"
+// MIPSEL-ANDROID-R6: "-mfloat-abi" "hard"
+
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
// RUN: FileCheck -check-prefix=MIPS64 %s
// MIPS64: clang
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[PATCH] D20345: [Mips] Finetuning MIPS32 Android default variants
petarj created this revision.
petarj added a reviewer: atanasyan.
petarj added a subscriber: cfe-commits.
Herald added subscribers: srhines, danalbert, tberghammer.
MIPS32 Android defaults to FPXX ("-fpxx").
MIPS32R6 Android defaults to FP64A ("-mfp64 -mno-odd-spreg").
http://reviews.llvm.org/D20345
Files:
lib/Driver/Tools.cpp
lib/Driver/Tools.h
test/Driver/clang-translation.c
Index: test/Driver/clang-translation.c
===
--- test/Driver/clang-translation.c
+++ test/Driver/clang-translation.c
@@ -246,8 +246,19 @@
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
// MIPSEL-ANDROID: "-target-cpu" "mips32"
+// MIPSEL-ANDROID: "-target-feature" "+fpxx"
+// MIPSEL-ANDROID: "-target-feature" "+nooddspreg"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
+// RUN: %clang -target mipsel-linux-android -### -S %s -mcpu=mips32r6 2>&1 | \
+// RUN: FileCheck -check-prefix=MIPSEL-ANDROID-R6 %s
+// MIPSEL-ANDROID-R6: clang
+// MIPSEL-ANDROID-R6: "-cc1"
+// MIPSEL-ANDROID-R6: "-target-cpu" "mips32r6"
+// MIPSEL-ANDROID-R6: "-target-feature" "+fp64"
+// MIPSEL-ANDROID-R6: "-target-feature" "+nooddspreg"
+// MIPSEL-ANDROID-R6: "-mfloat-abi" "hard"
+
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
// RUN: FileCheck -check-prefix=MIPS64 %s
// MIPS64: clang
Index: lib/Driver/Tools.h
===
--- lib/Driver/Tools.h
+++ lib/Driver/Tools.h
@@ -299,6 +299,7 @@
bool hasMipsAbiArg(const llvm::opt::ArgList , const char *Value);
bool isUCLibc(const llvm::opt::ArgList );
bool isNaN2008(const llvm::opt::ArgList , const llvm::Triple );
+bool isFP64ADefault(const llvm::Triple , StringRef CPUName);
bool isFPXXDefault(const llvm::Triple , StringRef CPUName,
StringRef ABIName, mips::FloatABI FloatABI);
bool shouldUseFPXX(const llvm::opt::ArgList , const llvm::Triple ,
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -1359,8 +1359,9 @@
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
- // Add the last -mfp32/-mfpxx/-mfp64 or if none are given and the ABI is O32
- // pass -mfpxx
+ // Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
+ // pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
+ // nooddspreg.
if (Arg *A = Args.getLastArg(options::OPT_mfp32, options::OPT_mfpxx,
options::OPT_mfp64)) {
if (A->getOption().matches(options::OPT_mfp32))
@@ -1373,6 +1374,9 @@
} else if (mips::shouldUseFPXX(Args, Triple, CPUName, ABIName, FloatABI)) {
Features.push_back(Args.MakeArgString("+fpxx"));
Features.push_back(Args.MakeArgString("+nooddspreg"));
+ } else if (mips::isFP64ADefault(Triple, CPUName)) {
+Features.push_back(Args.MakeArgString("+fp64"));
+Features.push_back(Args.MakeArgString("+nooddspreg"));
}
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
@@ -7030,10 +7034,21 @@
return false;
}
+bool mips::isFP64ADefault(const llvm::Triple , StringRef CPUName) {
+ if (!Triple.isAndroid())
+return false;
+
+ // Android MIPS32R6 defaults to FP64A.
+ return llvm::StringSwitch(CPUName)
+ .Case("mips32r6", true)
+ .Default(false);
+}
+
bool mips::isFPXXDefault(const llvm::Triple , StringRef CPUName,
StringRef ABIName, mips::FloatABI FloatABI) {
if (Triple.getVendor() != llvm::Triple::ImaginationTechnologies &&
- Triple.getVendor() != llvm::Triple::MipsTechnologies)
+ Triple.getVendor() != llvm::Triple::MipsTechnologies &&
+ !Triple.isAndroid())
return false;
if (ABIName != "32")
Index: test/Driver/clang-translation.c
===
--- test/Driver/clang-translation.c
+++ test/Driver/clang-translation.c
@@ -246,8 +246,19 @@
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
// MIPSEL-ANDROID: "-target-cpu" "mips32"
+// MIPSEL-ANDROID: "-target-feature" "+fpxx"
+// MIPSEL-ANDROID: "-target-feature" "+nooddspreg"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
+// RUN: %clang -target mipsel-linux-android -### -S %s -mcpu=mips32r6 2>&1 | \
+// RUN: FileCheck -check-prefix=MIPSEL-ANDROID-R6 %s
+// MIPSEL-ANDROID-R6: clang
+// MIPSEL-ANDROID-R6: "-cc1"
+// MIPSEL-ANDROID-R6: "-target-cpu" "mips32r6"
+// MIPSEL-ANDROID-R6: "-target-feature" "+fp64"
+// MIPSEL-ANDROID-R6: "-target-feature" "+nooddspreg"
+// MIPSEL-ANDROID-R6: "-mfloat-abi" "hard"
+
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
// RUN: FileCheck -check-prefix=MIPS64 %s
// MIPS64: clang
Index: lib/Driver/Tools.h
===
--- lib/Driver/Tools.h
+++ lib/Driver/Tools.h
@@ -299,6 +299,7 @@
bool hasMipsAbiArg(const llvm::opt::ArgList , const char *Value);
r269754 - [Mips] Set mips32 as default CPU for MIPS32 Android
Author: petarj
Date: Tue May 17 05:46:10 2016
New Revision: 269754
URL: http://llvm.org/viewvc/llvm-project?rev=269754=rev
Log:
[Mips] Set mips32 as default CPU for MIPS32 Android
Change default CPU for MIPS32 Android. Now it is mips32 (rev1).
Differential Revision: http://reviews.llvm.org/D20313
Modified:
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Driver/clang-translation.c
Modified: cfe/trunk/lib/Driver/Tools.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=269754=269753=269754=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Tue May 17 05:46:10 2016
@@ -1183,8 +1183,10 @@ void mips::getMipsCPUAndABI(const ArgLis
}
// MIPS64r6 is the default for Android MIPS64 (mips64el-linux-android).
- if (Triple.isAndroid())
+ if (Triple.isAndroid()) {
+DefMips32CPU = "mips32";
DefMips64CPU = "mips64r6";
+ }
// MIPS3 is the default for mips64*-unknown-openbsd.
if (Triple.getOS() == llvm::Triple::OpenBSD)
Modified: cfe/trunk/test/Driver/clang-translation.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/clang-translation.c?rev=269754=269753=269754=diff
==
--- cfe/trunk/test/Driver/clang-translation.c (original)
+++ cfe/trunk/test/Driver/clang-translation.c Tue May 17 05:46:10 2016
@@ -245,7 +245,7 @@
// RUN: FileCheck -check-prefix=MIPSEL-ANDROID %s
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
-// MIPSEL-ANDROID: "-target-cpu" "mips32r2"
+// MIPSEL-ANDROID: "-target-cpu" "mips32"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
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Re: [PATCH] D20313: [Mips] Set mips32 as default CPU for MIPS32 Android
This revision was automatically updated to reflect the committed changes.
Closed by commit rL269754: [Mips] Set mips32 as default CPU for MIPS32 Android
(authored by petarj).
Changed prior to commit:
http://reviews.llvm.org/D20313?vs=57423=57454#toc
Repository:
rL LLVM
http://reviews.llvm.org/D20313
Files:
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Driver/clang-translation.c
Index: cfe/trunk/test/Driver/clang-translation.c
===
--- cfe/trunk/test/Driver/clang-translation.c
+++ cfe/trunk/test/Driver/clang-translation.c
@@ -245,7 +245,7 @@
// RUN: FileCheck -check-prefix=MIPSEL-ANDROID %s
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
-// MIPSEL-ANDROID: "-target-cpu" "mips32r2"
+// MIPSEL-ANDROID: "-target-cpu" "mips32"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -1183,8 +1183,10 @@
}
// MIPS64r6 is the default for Android MIPS64 (mips64el-linux-android).
- if (Triple.isAndroid())
+ if (Triple.isAndroid()) {
+DefMips32CPU = "mips32";
DefMips64CPU = "mips64r6";
+ }
// MIPS3 is the default for mips64*-unknown-openbsd.
if (Triple.getOS() == llvm::Triple::OpenBSD)
Index: cfe/trunk/test/Driver/clang-translation.c
===
--- cfe/trunk/test/Driver/clang-translation.c
+++ cfe/trunk/test/Driver/clang-translation.c
@@ -245,7 +245,7 @@
// RUN: FileCheck -check-prefix=MIPSEL-ANDROID %s
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
-// MIPSEL-ANDROID: "-target-cpu" "mips32r2"
+// MIPSEL-ANDROID: "-target-cpu" "mips32"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -1183,8 +1183,10 @@
}
// MIPS64r6 is the default for Android MIPS64 (mips64el-linux-android).
- if (Triple.isAndroid())
+ if (Triple.isAndroid()) {
+DefMips32CPU = "mips32";
DefMips64CPU = "mips64r6";
+ }
// MIPS3 is the default for mips64*-unknown-openbsd.
if (Triple.getOS() == llvm::Triple::OpenBSD)
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[PATCH] D20313: [Mips] Set mips32 as default CPU for MIPS32 Android
petarj created this revision.
petarj added a reviewer: atanasyan.
petarj added a subscriber: cfe-commits.
Herald added subscribers: srhines, danalbert, tberghammer.
Change default CPU for MIPS32 Android. Now it is mips32 (rev1).
http://reviews.llvm.org/D20313
Files:
lib/Driver/Tools.cpp
test/Driver/clang-translation.c
Index: test/Driver/clang-translation.c
===
--- test/Driver/clang-translation.c
+++ test/Driver/clang-translation.c
@@ -245,7 +245,7 @@
// RUN: FileCheck -check-prefix=MIPSEL-ANDROID %s
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
-// MIPSEL-ANDROID: "-target-cpu" "mips32r2"
+// MIPSEL-ANDROID: "-target-cpu" "mips32"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -1183,8 +1183,10 @@
}
// MIPS64r6 is the default for Android MIPS64 (mips64el-linux-android).
- if (Triple.isAndroid())
+ if (Triple.isAndroid()) {
+DefMips32CPU = "mips32";
DefMips64CPU = "mips64r6";
+ }
// MIPS3 is the default for mips64*-unknown-openbsd.
if (Triple.getOS() == llvm::Triple::OpenBSD)
Index: test/Driver/clang-translation.c
===
--- test/Driver/clang-translation.c
+++ test/Driver/clang-translation.c
@@ -245,7 +245,7 @@
// RUN: FileCheck -check-prefix=MIPSEL-ANDROID %s
// MIPSEL-ANDROID: clang
// MIPSEL-ANDROID: "-cc1"
-// MIPSEL-ANDROID: "-target-cpu" "mips32r2"
+// MIPSEL-ANDROID: "-target-cpu" "mips32"
// MIPSEL-ANDROID: "-mfloat-abi" "hard"
// RUN: %clang -target mips64-linux-gnu -### -S %s 2>&1 | \
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -1183,8 +1183,10 @@
}
// MIPS64r6 is the default for Android MIPS64 (mips64el-linux-android).
- if (Triple.isAndroid())
+ if (Triple.isAndroid()) {
+DefMips32CPU = "mips32";
DefMips64CPU = "mips64r6";
+ }
// MIPS3 is the default for mips64*-unknown-openbsd.
if (Triple.getOS() == llvm::Triple::OpenBSD)
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r255539 - [PowerPC] Fix test/CodeGen/ppc-sfvarargs
Author: petarj
Date: Mon Dec 14 14:30:02 2015
New Revision: 255539
URL: http://llvm.org/viewvc/llvm-project?rev=255539=rev
Log:
[PowerPC] Fix test/CodeGen/ppc-sfvarargs
The issue seems to be that .ll file may either use number of register
value or alias %numUsedRegs, so the check needs to cover both cases.
This will hopefully fix the last regression introduced by r255515.
Modified:
cfe/trunk/test/CodeGen/ppc-sfvarargs.c
Modified: cfe/trunk/test/CodeGen/ppc-sfvarargs.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ppc-sfvarargs.c?rev=255539=255538=255539=diff
==
--- cfe/trunk/test/CodeGen/ppc-sfvarargs.c (original)
+++ cfe/trunk/test/CodeGen/ppc-sfvarargs.c Mon Dec 14 14:30:02 2015
@@ -12,6 +12,6 @@ void foo() {
double a;
test("test",a);
}
-// CHECK: %{{[0-9]+}} = add i8 %{{[0-9]+}}, 1
+// CHECK: %{{[0-9]+}} = add i8 %{{[0-9]+|numUsedRegs}}, 1
// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2
// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4
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r255515 - [Power PC] add soft float support for ppc32
Author: petarj
Date: Mon Dec 14 11:51:50 2015
New Revision: 255515
URL: http://llvm.org/viewvc/llvm-project?rev=255515=rev
Log:
[Power PC] add soft float support for ppc32
This patch enables soft float support for ppc32 architecture and fixes
the ABI for variadic functions. This is the first in a set of patches
for soft float support in LLVM.
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D13351
Added:
cfe/trunk/test/CodeGen/ppc-sfvarargs.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/lib/Driver/Tools.h
cfe/trunk/test/Driver/ppc-features.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=255515=255514=255515=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Mon Dec 14 11:51:50 2015
@@ -3413,8 +3413,10 @@ Address WinX86_64ABIInfo::EmitVAArg(Code
namespace {
/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
+bool IsSoftFloatABI;
public:
- PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes ) : DefaultABIInfo(CGT) {}
+ PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes , bool SoftFloatABI)
+ : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
Address EmitVAArg(CodeGenFunction , Address VAListAddr,
QualType Ty) const override;
@@ -3422,8 +3424,8 @@ public:
class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
- PPC32TargetCodeGenInfo(CodeGenTypes )
- : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT)) {}
+ PPC32TargetCodeGenInfo(CodeGenTypes , bool SoftFloatABI)
+ : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
int getDwarfEHStackPointer(CodeGen::CodeGenModule ) const override {
// This is recovered from gcc output.
@@ -3455,6 +3457,7 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
bool isInt =
Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
+ bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
// All aggregates are passed indirectly? That doesn't seem consistent
// with the argument-lowering code.
@@ -3464,7 +3467,7 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
// The calling convention either uses 1-2 GPRs or 1 FPR.
Address NumRegsAddr = Address::invalid();
- if (isInt) {
+ if (isInt || IsSoftFloatABI) {
NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
} else {
NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
@@ -3473,7 +3476,7 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
// "Align" the register count when TY is i64.
- if (isI64) {
+ if (isI64 || (isF64 && IsSoftFloatABI)) {
NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
}
@@ -3502,14 +3505,14 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
assert(RegAddr.getElementType() == CGF.Int8Ty);
// Floating-point registers start after the general-purpose registers.
-if (!isInt) {
+if (!(isInt || IsSoftFloatABI)) {
RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
CharUnits::fromQuantity(32));
}
// Get the address of the saved value by scaling the number of
// registers we've used by the number of
-CharUnits RegSize = CharUnits::fromQuantity(isInt ? 4 : 8);
+CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4
: 8);
llvm::Value *RegOffset =
Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
@@ -3518,7 +3521,9 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
// Increase the used-register count.
-NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(isI64 ? 2 : 1));
+NumRegs =
+ Builder.CreateAdd(NumRegs,
+Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ?
2 : 1));
Builder.CreateStore(NumRegs, NumRegsAddr);
CGF.EmitBranch(Cont);
@@ -7471,7 +7476,8 @@ const TargetCodeGenInfo ::
}
case llvm::Triple::ppc:
-return *(TheTargetCodeGenInfo = new PPC32TargetCodeGenInfo(Types));
+return *(TheTargetCodeGenInfo =
+ new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI ==
"soft"));
case llvm::Triple::ppc64:
if (Triple.isOSBinFormatELF()) {
PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
Modified: cfe/trunk/lib/Driver/Tools.cpp
URL:
r255533 - [PowerPC] Fix make-check issues
Author: petarj
Date: Mon Dec 14 13:22:35 2015
New Revision: 255533
URL: http://llvm.org/viewvc/llvm-project?rev=255533=rev
Log:
[PowerPC] Fix make-check issues
Previous change r255515 introduced a couple of issues likely caused by
a different configure setup.
Modified:
cfe/trunk/test/CodeGen/ppc-sfvarargs.c
cfe/trunk/test/Driver/ppc-features.cpp
Modified: cfe/trunk/test/CodeGen/ppc-sfvarargs.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ppc-sfvarargs.c?rev=255533=255532=255533=diff
==
--- cfe/trunk/test/CodeGen/ppc-sfvarargs.c (original)
+++ cfe/trunk/test/CodeGen/ppc-sfvarargs.c Mon Dec 14 13:22:35 2015
@@ -12,6 +12,6 @@ void foo() {
double a;
test("test",a);
}
-// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1
+// CHECK: %{{[0-9]+}} = add i8 %{{[0-9]+}}, 1
// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2
-// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4
\ No newline at end of file
+// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4
Modified: cfe/trunk/test/Driver/ppc-features.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/ppc-features.cpp?rev=255533=255532=255533=diff
==
--- cfe/trunk/test/Driver/ppc-features.cpp (original)
+++ cfe/trunk/test/Driver/ppc-features.cpp Mon Dec 14 13:22:35 2015
@@ -38,23 +38,23 @@
// check -mfloat-abi=x option
// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=x -### -o %t.o
2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s
-// CHECK-ERRMSG: clang: error: invalid float ABI '-mfloat-abi=x'
+// CHECK-ERRMSG: error: invalid float ABI '-mfloat-abi=x'
// check -msoft-float option for ppc64
// RUN: %clang -target powerpc64-unknown-linux-gnu %s -msoft-float -### -o
%t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64 %s
-// CHECK-SOFTFLOAT64: clang: error: invalid float ABI 'soft float is not
supported for ppc64'
+// CHECK-SOFTFLOAT64: error: invalid float ABI 'soft float is not supported
for ppc64'
// check -mfloat-abi=soft option for ppc64
// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mfloat-abi=soft -### -o
%t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64 %s
-// CHECK-FLOATABISOFT64: clang: error: invalid float ABI 'soft float is not
supported for ppc64'
+// CHECK-FLOATABISOFT64: error: invalid float ABI 'soft float is not supported
for ppc64'
// check -msoft-float option for ppc64
// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -msoft-float -### -o
%t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64le %s
-// CHECK-SOFTFLOAT64le: clang: error: invalid float ABI 'soft float is not
supported for ppc64'
+// CHECK-SOFTFLOAT64le: error: invalid float ABI 'soft float is not supported
for ppc64'
// check -mfloat-abi=soft option for ppc64
// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -mfloat-abi=soft -###
-o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64le %s
-// CHECK-FLOATABISOFT64le: clang: error: invalid float ABI 'soft float is not
supported for ppc64'
+// CHECK-FLOATABISOFT64le: error: invalid float ABI 'soft float is not
supported for ppc64'
// CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le'
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D13351: [Power PC] add soft float support for ppc32
This revision was automatically updated to reflect the committed changes.
Closed by commit rL255515: [Power PC] add soft float support for ppc32
(authored by petarj).
Changed prior to commit:
http://reviews.llvm.org/D13351?vs=41736=42733#toc
Repository:
rL LLVM
http://reviews.llvm.org/D13351
Files:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/lib/Driver/Tools.h
cfe/trunk/test/CodeGen/ppc-sfvarargs.c
cfe/trunk/test/Driver/ppc-features.cpp
Index: cfe/trunk/test/Driver/ppc-features.cpp
===
--- cfe/trunk/test/Driver/ppc-features.cpp
+++ cfe/trunk/test/Driver/ppc-features.cpp
@@ -12,6 +12,50 @@
// RUN: not %clang -target mips64-linux-gnu -faltivec -fsyntax-only %s 2>&1 | FileCheck %s
// RUN: not %clang -target sparc-unknown-solaris -faltivec -fsyntax-only %s 2>&1 | FileCheck %s
+// check -msoft-float option for ppc32
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s
+// CHECK-SOFTFLOAT: "-target-feature" "+soft-float"
+
+// check -mfloat-abi=soft option for ppc32
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT %s
+// CHECK-FLOATABISOFT: "-target-feature" "+soft-float"
+
+// check -mhard-float option for ppc32
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDFLOAT %s
+// CHECK-HARDFLOAT-NOT: "-target-feature" "+soft-float"
+
+// check -mfloat-abi=hard option for ppc32
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=hard -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABIHARD %s
+// CHECK-FLOATABIHARD-NOT: "-target-feature" "+soft-float"
+
+// check combine -mhard-float -msoft-float option for ppc32
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -mhard-float -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-HARDSOFT %s
+// CHECK-HARDSOFT: "-target-feature" "+soft-float"
+
+// check combine -msoft-float -mhard-float option for ppc32
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -mhard-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTHARD %s
+// CHECK-SOFTHARD-NOT: "-target-feature" "+soft-float"
+
+// check -mfloat-abi=x option
+// RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=x -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s
+// CHECK-ERRMSG: clang: error: invalid float ABI '-mfloat-abi=x'
+
+// check -msoft-float option for ppc64
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64 %s
+// CHECK-SOFTFLOAT64: clang: error: invalid float ABI 'soft float is not supported for ppc64'
+
+// check -mfloat-abi=soft option for ppc64
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64 %s
+// CHECK-FLOATABISOFT64: clang: error: invalid float ABI 'soft float is not supported for ppc64'
+
+// check -msoft-float option for ppc64
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64le %s
+// CHECK-SOFTFLOAT64le: clang: error: invalid float ABI 'soft float is not supported for ppc64'
+
+// check -mfloat-abi=soft option for ppc64
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -mfloat-abi=soft -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-FLOATABISOFT64le %s
+// CHECK-FLOATABISOFT64le: clang: error: invalid float ABI 'soft float is not supported for ppc64'
+
// CHECK: invalid argument '-faltivec' only allowed with 'ppc/ppc64/ppc64le'
// Check that -fno-altivec and -mno-altivec correctly disable the altivec
Index: cfe/trunk/test/CodeGen/ppc-sfvarargs.c
===
--- cfe/trunk/test/CodeGen/ppc-sfvarargs.c
+++ cfe/trunk/test/CodeGen/ppc-sfvarargs.c
@@ -0,0 +1,17 @@
+// RUN: %clang -O0 --target=powerpc-unknown-linux-gnu -EB -msoft-float -S -emit-llvm %s -o - | FileCheck %s
+
+#include
+void test(char *fmt, ...) {
+ va_list ap;
+ va_start(ap, fmt);
+ va_arg(ap, double);
+ va_end(ap);
+}
+
+void foo() {
+ double a;
+ test("test",a);
+}
+// CHECK: %{{[0-9]+}} = add i8 %numUsedRegs, 1
+// CHECK: %{{[0-9]+}} = and i8 %{{[0-9]+}}, -2
+// CHECK: %{{[0-9]+}} = mul i8 %{{[0-9]+}}, 4
\ No newline at end of file
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -3413,17 +3413,19 @@
namespace {
/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
+bool IsSoftFloatABI;
public:
- PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes ) : DefaultABIInfo(CGT) {}
+
Re: [PATCH] D14871: [Power PC] fix calculating address of arguments on stack for variadic functions
This revision was automatically updated to reflect the committed changes.
Closed by commit rL254670: [PowerPC] Fix calculating address of arguments on
stack for variadic func (authored by petarj).
Changed prior to commit:
http://reviews.llvm.org/D14871?vs=41613=41826#toc
Repository:
rL LLVM
http://reviews.llvm.org/D14871
Files:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/ppc-varargs-struct.c
cfe/trunk/test/CodeGen/x86_64-arguments.c
Index: cfe/trunk/test/CodeGen/ppc-varargs-struct.c
===
--- cfe/trunk/test/CodeGen/ppc-varargs-struct.c
+++ cfe/trunk/test/CodeGen/ppc-varargs-struct.c
@@ -39,9 +39,13 @@
// CHECK-PPC:[[USING_OVERFLOW]]
// CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds %struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3
// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8** [[OVERFLOW_AREA_P]], align 4
-// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to %struct.x**
-// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* [[OVERFLOW_AREA]], i32 4
-// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA]], i8** [[OVERFLOW_AREA_P]]
+// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %argp.cur to i32
+// CHECK-PPC-NEXT: %{{[0-9]+}} = add i32 %{{[0-9]+}}, 7
+// CHECK-PPC-NEXT: %{{[0-9]+}} = and i32 %{{[0-9]+}}, -8
+// CHECK-PPC-NEXT: %argp.cur.aligned = inttoptr i32 %{{[0-9]+}} to i8*
+// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* %argp.cur.aligned to %struct.x**
+// CHECK-PPC-NEXT: [[NEW_OVERFLOW_AREA:%[0-9]+]] = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 4
+// CHECK-PPC-NEXT: store i8* [[NEW_OVERFLOW_AREA:%[0-9]+]], i8** [[OVERFLOW_AREA_P]], align 4
// CHECK-PPC-NEXT: br label %[[CONT]]
//
// CHECK-PPC:[[CONT]]
Index: cfe/trunk/test/CodeGen/x86_64-arguments.c
===
--- cfe/trunk/test/CodeGen/x86_64-arguments.c
+++ cfe/trunk/test/CodeGen/x86_64-arguments.c
@@ -336,7 +336,8 @@
// CHECK-LABEL: define i32 @f44
// CHECK: ptrtoint
-// CHECK-NEXT: and {{.*}}, -32
+// CHECK-NEXT: add i64 %{{[0-9]+}}, 31
+// CHECK-NEXT: and i64 %{{[0-9]+}}, -32
// CHECK-NEXT: inttoptr
typedef int T44 __attribute((vector_size(32)));
struct s44 { T44 x; int y; };
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -162,6 +162,23 @@
OS << ")\n";
}
+// Dynamically round a pointer up to a multiple of the given alignment.
+static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction ,
+ llvm::Value *Ptr,
+ CharUnits Align) {
+ llvm::Value *PtrAsInt = Ptr;
+ // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
+ PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
+ PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
+llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
+ PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
+ llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
+ PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
+Ptr->getType(),
+Ptr->getName() + ".aligned");
+ return PtrAsInt;
+}
+
/// Emit va_arg for a platform using the common void* representation,
/// where arguments are simply emitted in an array of slots on the stack.
///
@@ -193,17 +210,10 @@
// If the CC aligns values higher than the slot size, do so if needed.
Address Addr = Address::invalid();
if (AllowHigherAlign && DirectAlign > SlotSize) {
-llvm::Value *PtrAsInt = Ptr;
-PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
-PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
- llvm::ConstantInt::get(CGF.IntPtrTy, DirectAlign.getQuantity() - 1));
-PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
- llvm::ConstantInt::get(CGF.IntPtrTy, -DirectAlign.getQuantity()));
-Addr = Address(CGF.Builder.CreateIntToPtr(PtrAsInt, Ptr->getType(),
- "argp.cur.aligned"),
- DirectAlign);
+Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
+ DirectAlign);
} else {
-Addr = Address(Ptr, SlotSize);
+Addr = Address(Ptr, SlotSize);
}
// Advance the pointer past the argument, then store that back.
@@ -3072,19 +3082,10 @@
// byte boundary if alignment needed by type exceeds 8 byte boundary.
// It isn't stated explicitly in the standard, but in practice we use
// alignment greater than 16 where necessary.
- uint64_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity();
- if (Align > 8) {
-// overflow_arg_area =
r254670 - [PowerPC] Fix calculating address of arguments on stack for variadic func
Author: petarj
Date: Thu Dec 3 18:26:47 2015
New Revision: 254670
URL: http://llvm.org/viewvc/llvm-project?rev=254670=rev
Log:
[PowerPC] Fix calculating address of arguments on stack for variadic func
Fix calculating address of arguments larger than 32 bit on stack for
variadic functions (rounding up address to alignment) on ppc32 architecture.
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D14871
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/ppc-varargs-struct.c
cfe/trunk/test/CodeGen/x86_64-arguments.c
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=254670=254669=254670=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Thu Dec 3 18:26:47 2015
@@ -162,6 +162,23 @@ void ABIArgInfo::dump() const {
OS << ")\n";
}
+// Dynamically round a pointer up to a multiple of the given alignment.
+static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction ,
+ llvm::Value *Ptr,
+ CharUnits Align) {
+ llvm::Value *PtrAsInt = Ptr;
+ // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
+ PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
+ PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
+llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
+ PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
+ llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
+ PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
+Ptr->getType(),
+Ptr->getName() + ".aligned");
+ return PtrAsInt;
+}
+
/// Emit va_arg for a platform using the common void* representation,
/// where arguments are simply emitted in an array of slots on the stack.
///
@@ -193,17 +210,10 @@ static Address emitVoidPtrDirectVAArg(Co
// If the CC aligns values higher than the slot size, do so if needed.
Address Addr = Address::invalid();
if (AllowHigherAlign && DirectAlign > SlotSize) {
-llvm::Value *PtrAsInt = Ptr;
-PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
-PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
- llvm::ConstantInt::get(CGF.IntPtrTy, DirectAlign.getQuantity() - 1));
-PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
- llvm::ConstantInt::get(CGF.IntPtrTy, -DirectAlign.getQuantity()));
-Addr = Address(CGF.Builder.CreateIntToPtr(PtrAsInt, Ptr->getType(),
- "argp.cur.aligned"),
- DirectAlign);
+Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
+ DirectAlign);
} else {
-Addr = Address(Ptr, SlotSize);
+Addr = Address(Ptr, SlotSize);
}
// Advance the pointer past the argument, then store that back.
@@ -3072,19 +3082,10 @@ static Address EmitX86_64VAArgFromMemory
// byte boundary if alignment needed by type exceeds 8 byte boundary.
// It isn't stated explicitly in the standard, but in practice we use
// alignment greater than 16 where necessary.
- uint64_t Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity();
- if (Align > 8) {
-// overflow_arg_area = (overflow_arg_area + align - 1) & -align;
-llvm::Value *Offset =
- llvm::ConstantInt::get(CGF.Int64Ty, Align - 1);
-overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset);
-llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area,
-CGF.Int64Ty);
-llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align);
-overflow_arg_area =
- CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask),
- overflow_arg_area->getType(),
- "overflow_arg_area.align");
+ CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
+ if (Align > CharUnits::fromQuantity(8)) {
+overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
+ Align);
}
// AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
@@ -3106,7 +3107,7 @@ static Address EmitX86_64VAArgFromMemory
CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
// AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
- return Address(Res, CharUnits::fromQuantity(Align));
+ return Address(Res, Align);
}
Address X86_64ABIInfo::EmitVAArg(CodeGenFunction , Address VAListAddr,
@@ -3541,11 +3542,16 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
Address OverflowAreaAddr =
Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
-Address
Re: [PATCH] D14149: __builtin_signbit fix for ppcf128 type
This revision was automatically updated to reflect the committed changes.
Closed by commit rL252307: Fix __builtin_signbit for ppcf128 type (authored by
petarj).
Changed prior to commit:
http://reviews.llvm.org/D14149?vs=39513=39523#toc
Repository:
rL LLVM
http://reviews.llvm.org/D14149
Files:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/Analysis/builtin_signbit.cpp
Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -238,10 +238,20 @@
llvm::Type *IntTy = llvm::IntegerType::get(C, Width);
V = CGF.Builder.CreateBitCast(V, IntTy);
if (Ty->isPPC_FP128Ty()) {
-// The higher-order double comes first, and so we need to truncate the
-// pair to extract the overall sign. The order of the pair is the same
-// in both little- and big-Endian modes.
+// We want the sign bit of the higher-order double. The bitcast we just
+// did works as if the double-double was stored to memory and then
+// read as an i128. The "store" will put the higher-order double in the
+// lower address in both little- and big-Endian modes, but the "load"
+// will treat those bits as a different part of the i128: the low bits in
+// little-Endian, the high bits in big-Endian. Therefore, on big-Endian
+// we need to shift the high bits down to the low before truncating.
Width >>= 1;
+if (CGF.getTarget().isBigEndian()) {
+ Value *ShiftCst = llvm::ConstantInt::get(IntTy, Width);
+ V = CGF.Builder.CreateLShr(V, ShiftCst);
+}
+// We are truncating value in order to extract the higher-order
+// double, which we will be using to extract the sign from.
IntTy = llvm::IntegerType::get(C, Width);
V = CGF.Builder.CreateTrunc(V, IntTy);
}
Index: cfe/trunk/test/Analysis/builtin_signbit.cpp
===
--- cfe/trunk/test/Analysis/builtin_signbit.cpp
+++ cfe/trunk/test/Analysis/builtin_signbit.cpp
@@ -0,0 +1,43 @@
+// RUN: %clang -target powerpc-linux-gnu -emit-llvm -S -O0 %s -o - |
FileCheck %s --check-prefix=CHECK-BE --check-prefix=CHECK
+// RUN: %clang -target powerpc64-linux-gnu -emit-llvm -S -O0 %s -o - |
FileCheck %s --check-prefix=CHECK-BE --check-prefix=CHECK
+// RUN: %clang -target powerpc64le-linux-gnu -emit-llvm -S -O0 %s -o - |
FileCheck %s --check-prefix=CHECK-LE --check-prefix=CHECK
+
+bool b;
+double d = -1.0;
+long double ld = -1.0L;
+void test_signbit()
+{
+ b = __builtin_signbit(1.0L);
+ // CHECK: i128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+
+ b = __builtin_signbit(ld);
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+
+ b = __builtin_signbitf(1.0);
+ // CHECK: store i8 0
+
+ b = __builtin_signbitf(d);
+ // CHECK: bitcast
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE-NOT: lshr
+
+ b = __builtin_signbitl(1.0L);
+ // CHECK: i128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+
+ b = __builtin_signbitl(ld);
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+}
Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -238,10 +238,20 @@
llvm::Type *IntTy = llvm::IntegerType::get(C, Width);
V = CGF.Builder.CreateBitCast(V, IntTy);
if (Ty->isPPC_FP128Ty()) {
-// The higher-order double comes first, and so we need to truncate the
-// pair to extract the overall sign. The order of the pair is the same
-// in both little- and big-Endian modes.
+// We want the sign bit of the higher-order double. The bitcast we just
+// did works as if the double-double was stored to memory and then
+// read as an i128. The "store" will put the higher-order double in the
+// lower address in both little- and big-Endian modes, but the "load"
+// will treat those bits as a different part of the i128: the low bits in
+// little-Endian, the high bits in big-Endian. Therefore, on big-Endian
+// we need to shift the high bits down to the low before truncating.
Width >>= 1;
+if (CGF.getTarget().isBigEndian()) {
+ Value *ShiftCst = llvm::ConstantInt::get(IntTy, Width);
+ V = CGF.Builder.CreateLShr(V, ShiftCst);
+}
+// We are truncating value in order to extract the higher-order
+// double, which we will be using to extract the sign from.
IntTy = llvm::IntegerType::get(C, Width);
V = CGF.Builder.CreateTrunc(V, IntTy);
}
Index: cfe/trunk/test/Analysis/builtin_signbit.cpp
===
--- cfe/trunk/test/Analysis/builtin_signbit.cpp
+++ cfe/trunk/test/Analysis/builtin_signbit.cpp
@@ -0,0 +1,43 @@
+// RUN:
r252307 - Fix __builtin_signbit for ppcf128 type
Author: petarj
Date: Fri Nov 6 08:52:46 2015
New Revision: 252307
URL: http://llvm.org/viewvc/llvm-project?rev=252307=rev
Log:
Fix __builtin_signbit for ppcf128 type
Function__builtin_signbit returns wrong value for type ppcf128 on big endian
machines. This patch fixes how value is generated in that case.
Patch by Aleksandar Beserminji.
Differential Revision: http://reviews.llvm.org/D14149
Added:
cfe/trunk/test/Analysis/builtin_signbit.cpp
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=252307=252306=252307=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Fri Nov 6 08:52:46 2015
@@ -238,10 +238,20 @@ static Value *EmitSignBit(CodeGenFunctio
llvm::Type *IntTy = llvm::IntegerType::get(C, Width);
V = CGF.Builder.CreateBitCast(V, IntTy);
if (Ty->isPPC_FP128Ty()) {
-// The higher-order double comes first, and so we need to truncate the
-// pair to extract the overall sign. The order of the pair is the same
-// in both little- and big-Endian modes.
+// We want the sign bit of the higher-order double. The bitcast we just
+// did works as if the double-double was stored to memory and then
+// read as an i128. The "store" will put the higher-order double in the
+// lower address in both little- and big-Endian modes, but the "load"
+// will treat those bits as a different part of the i128: the low bits in
+// little-Endian, the high bits in big-Endian. Therefore, on big-Endian
+// we need to shift the high bits down to the low before truncating.
Width >>= 1;
+if (CGF.getTarget().isBigEndian()) {
+ Value *ShiftCst = llvm::ConstantInt::get(IntTy, Width);
+ V = CGF.Builder.CreateLShr(V, ShiftCst);
+}
+// We are truncating value in order to extract the higher-order
+// double, which we will be using to extract the sign from.
IntTy = llvm::IntegerType::get(C, Width);
V = CGF.Builder.CreateTrunc(V, IntTy);
}
Added: cfe/trunk/test/Analysis/builtin_signbit.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Analysis/builtin_signbit.cpp?rev=252307=auto
==
--- cfe/trunk/test/Analysis/builtin_signbit.cpp (added)
+++ cfe/trunk/test/Analysis/builtin_signbit.cpp Fri Nov 6 08:52:46 2015
@@ -0,0 +1,43 @@
+// RUN: %clang -target powerpc-linux-gnu -emit-llvm -S -O0 %s -o - |
FileCheck %s --check-prefix=CHECK-BE --check-prefix=CHECK
+// RUN: %clang -target powerpc64-linux-gnu -emit-llvm -S -O0 %s -o - |
FileCheck %s --check-prefix=CHECK-BE --check-prefix=CHECK
+// RUN: %clang -target powerpc64le-linux-gnu -emit-llvm -S -O0 %s -o - |
FileCheck %s --check-prefix=CHECK-LE --check-prefix=CHECK
+
+bool b;
+double d = -1.0;
+long double ld = -1.0L;
+void test_signbit()
+{
+ b = __builtin_signbit(1.0L);
+ // CHECK: i128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+
+ b = __builtin_signbit(ld);
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+
+ b = __builtin_signbitf(1.0);
+ // CHECK: store i8 0
+
+ b = __builtin_signbitf(d);
+ // CHECK: bitcast
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE-NOT: lshr
+
+ b = __builtin_signbitl(1.0L);
+ // CHECK: i128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+
+ b = __builtin_signbitl(ld);
+ // CHECK: bitcast
+ // CHECK: ppc_fp128
+ // CHECK-LE-NOT: lshr
+ // CHECK-BE: lshr
+}
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[PATCH] D11949: [MIPS] Use arch values for lock-free atomic operations
petarj created this revision.
petarj added a reviewer: dschuff.
petarj added a subscriber: cfe-commits.
Herald added subscribers: dschuff, jfb.
Let NaClMips32ELTargetInfo inherit arch values for maximum width lock-free
atomic operations.
http://reviews.llvm.org/D11949
Files:
lib/Basic/Targets.cpp
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6842,8 +6842,7 @@
class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
public:
NaClMips32ELTargetInfo(const llvm::Triple Triple) :
-Mips32ELTargetInfo(Triple) {
- MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0;
+Mips32ELTargetInfo(Triple) {
}
BuiltinVaListKind getBuiltinVaListKind() const override {
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6842,8 +6842,7 @@
class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
public:
NaClMips32ELTargetInfo(const llvm::Triple Triple) :
-Mips32ELTargetInfo(Triple) {
- MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0;
+Mips32ELTargetInfo(Triple) {
}
BuiltinVaListKind getBuiltinVaListKind() const override {
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