from:"Pete Couperus via Phabricator via cfe\-commits"

[PATCH] D43089: clang: Add ARCTargetInfo

2018-02-14 Thread Pete Couperus via Phabricator via cfe-commits

petecoup added a comment.

Hi Tatyana,

Thanks for taking a look here, and sorry for the delay.
I tried to follow the other target's usage patterns here.
I'm happy to update/change this...I'll add a couple of clang reviewers here to 
weigh in?


https://reviews.llvm.org/D43089



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[PATCH] D43089: clang: Add ARCTargetInfo

2018-02-09 Thread Pete Couperus via Phabricator via cfe-commits

petecoup added a comment.

Hi Tatyana,

Thanks for checking against lldb! I will try and find a couple of people who 
can review this as a clang change.

Pete


https://reviews.llvm.org/D43089



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[PATCH] D43089: clang: Add ARCTargetInfo

2018-02-09 Thread Pete Couperus via Phabricator via cfe-commits

petecoup updated this revision to Diff 133674.
petecoup added a comment.

Hello Eugene,

Thanks for taking a look.
Changed // End anonymous namespace. -> // namespace


https://reviews.llvm.org/D43089

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/ARC.cpp
  clang/lib/Basic/Targets/ARC.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arc-arguments.c
  clang/test/CodeGen/arc-struct-align.c
  clang/test/CodeGen/target-data.c

Index: clang/test/CodeGen/target-data.c
===
--- clang/test/CodeGen/target-data.c
+++ clang/test/CodeGen/target-data.c
@@ -159,6 +159,10 @@
 // RUN: %s | FileCheck %s -check-prefix=ARM-GNU
 // ARM-GNU: target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
 
+// RUN: %clang_cc1 -triple arc-unknown-unknown -o - -emit-llvm %s | \
+// RUN: FileCheck %s -check-prefix=ARC
+// ARC: target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-f32:32:32-i64:32-f64:32-a:0:32-n32"
+
 // RUN: %clang_cc1 -triple hexagon-unknown -o - -emit-llvm %s | \
 // RUN: FileCheck %s -check-prefix=HEXAGON
 // HEXAGON: target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
Index: clang/test/CodeGen/arc-struct-align.c
===
--- /dev/null
+++ clang/test/CodeGen/arc-struct-align.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN:   | FileCheck %s
+
+// 64-bit fields need only be 32-bit aligned for arc.
+
+typedef struct {
+  int aa;
+  double bb;
+} s1;
+
+// CHECK: define i32 @f1
+// CHECK: ret i32 12
+int f1() {
+  return sizeof(s1);
+}
+
+typedef struct {
+  int aa;
+  long long bb;
+} s2;
+// CHECK: define i32 @f2
+// CHECK: ret i32 12
+int f2() {
+  return sizeof(s2);
+}
+
Index: clang/test/CodeGen/arc-arguments.c
===
--- /dev/null
+++ clang/test/CodeGen/arc-arguments.c
@@ -0,0 +1,135 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN:   | FileCheck %s
+
+// Basic argument tests for ARC.
+
+// CHECK: define void @f0(i32 %i, i32 %j, i64 %k)
+void f0(int i, long j, long long k) {}
+
+typedef struct {
+  int aa;
+  int bb;
+} s1;
+// CHECK: define void @f1(i32 %i.coerce0, i32 %i.coerce1)
+void f1(s1 i) {}
+
+typedef struct {
+  char aa; char bb; char cc; char dd;
+} cs1;
+// CHECK: define void @cf1(i32 %i.coerce)
+void cf1(cs1 i) {}
+
+typedef struct {
+  int cc;
+} s2;
+// CHECK: define void @f2(%struct.s2* noalias sret %agg.result)
+s2 f2() {
+  s2 foo;
+  return foo;
+}
+
+typedef struct {
+  int cc;
+  int dd;
+} s3;
+// CHECK: define void @f3(%struct.s3* noalias sret %agg.result)
+s3 f3() {
+  s3 foo;
+  return foo;
+}
+
+// CHECK: define void @f4(i64 %i)
+void f4(long long i) {}
+
+// CHECK: define void @f5(i8 signext %a, i16 signext %b)
+void f5(signed char a, short b) {}
+
+// CHECK: define void @f6(i8 zeroext %a, i16 zeroext %b)
+void f6(unsigned char a, unsigned short b) {}
+
+enum my_enum {
+  ENUM1,
+  ENUM2,
+  ENUM3,
+};
+// Enums should be treated as the underlying i32.
+// CHECK: define void @f7(i32 %a)
+void f7(enum my_enum a) {}
+
+enum my_big_enum {
+  ENUM4 = 0x,
+};
+// Big enums should be treated as the underlying i64.
+// CHECK: define void @f8(i64 %a)
+void f8(enum my_big_enum a) {}
+
+union simple_union {
+  int a;
+  char b;
+};
+// Unions should be passed inreg.
+// CHECK: define void @f9(i32 %s.coerce)
+void f9(union simple_union s) {}
+
+typedef struct {
+  int b4 : 4;
+  int b3 : 3;
+  int b8 : 8;
+} bitfield1;
+// Bitfields should be passed inreg.
+// CHECK: define void @f10(i32 %bf1.coerce)
+void f10(bitfield1 bf1) {}
+
+// CHECK: define { float, float } @cplx1(float %r)
+_Complex float cplx1(float r) {
+  return r + 2.0fi;
+}
+
+// CHECK: define { double, double } @cplx2(double %r)
+_Complex double cplx2(double r) {
+  return r + 2.0i;
+}
+
+// CHECK: define { i32, i32 } @cplx3(i32 %r)
+_Complex int cplx3(int r) {
+  return r + 2i;
+}
+
+// CHECK: define { i64, i64 } @cplx4(i64 %r)
+_Complex long long cplx4(long long r) {
+  return r + 2i;
+}
+
+// CHECK: define { i8, i8 } @cplx6(i8 signext %r)
+_Complex signed char cplx6(signed char r) {
+  return r + 2i;
+}
+
+// CHECK: define { i16, i16 } @cplx7(i16 signext %r)
+_Complex short cplx7(short r) {
+  return r + 2i;
+}
+
+typedef struct {
+  int aa; int bb;
+} s8;
+
+typedef struct {
+  int aa; int bb; int cc; int dd;
+} s16;
+
+// Use 16-byte struct 2 times, gets 8 registers.
+void st2(s16 a, s16 b) {}
+// CHECK: define void @st2(i32 %a.coerce0, i32 %a.coerce1, i32 %a.coerce2, i32 %a.coerce3, i32 %b.coerce0, i32 %b.coerce1, i32 %b.coerce2, i32 %b.coerce3)
+
+// Use 8-byte struct 3 times, gets 8 registers, 1 byval struct argument.
+void st3(s16 a, s

[PATCH] D43089: clang: Add ARCTargetInfo

2018-02-08 Thread Pete Couperus via Phabricator via cfe-commits

petecoup created this revision.
petecoup added a reviewer: tatyana-krasnukha.
Herald added subscribers: hintonda, mgorny.

https://reviews.llvm.org/D43089

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/ARC.cpp
  clang/lib/Basic/Targets/ARC.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arc-arguments.c
  clang/test/CodeGen/arc-struct-align.c
  clang/test/CodeGen/target-data.c

Index: clang/test/CodeGen/target-data.c
===
--- clang/test/CodeGen/target-data.c
+++ clang/test/CodeGen/target-data.c
@@ -159,6 +159,10 @@
 // RUN: %s | FileCheck %s -check-prefix=ARM-GNU
 // ARM-GNU: target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
 
+// RUN: %clang_cc1 -triple arc-unknown-unknown -o - -emit-llvm %s | \
+// RUN: FileCheck %s -check-prefix=ARC
+// ARC: target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-f32:32:32-i64:32-f64:32-a:0:32-n32"
+
 // RUN: %clang_cc1 -triple hexagon-unknown -o - -emit-llvm %s | \
 // RUN: FileCheck %s -check-prefix=HEXAGON
 // HEXAGON: target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
Index: clang/test/CodeGen/arc-struct-align.c
===
--- /dev/null
+++ clang/test/CodeGen/arc-struct-align.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN:   | FileCheck %s
+
+// 64-bit fields need only be 32-bit aligned for arc.
+
+typedef struct {
+  int aa;
+  double bb;
+} s1;
+
+// CHECK: define i32 @f1
+// CHECK: ret i32 12
+int f1() {
+  return sizeof(s1);
+}
+
+typedef struct {
+  int aa;
+  long long bb;
+} s2;
+// CHECK: define i32 @f2
+// CHECK: ret i32 12
+int f2() {
+  return sizeof(s2);
+}
+
Index: clang/test/CodeGen/arc-arguments.c
===
--- /dev/null
+++ clang/test/CodeGen/arc-arguments.c
@@ -0,0 +1,135 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN:   | FileCheck %s
+
+// Basic argument tests for ARC.
+
+// CHECK: define void @f0(i32 %i, i32 %j, i64 %k)
+void f0(int i, long j, long long k) {}
+
+typedef struct {
+  int aa;
+  int bb;
+} s1;
+// CHECK: define void @f1(i32 %i.coerce0, i32 %i.coerce1)
+void f1(s1 i) {}
+
+typedef struct {
+  char aa; char bb; char cc; char dd;
+} cs1;
+// CHECK: define void @cf1(i32 %i.coerce)
+void cf1(cs1 i) {}
+
+typedef struct {
+  int cc;
+} s2;
+// CHECK: define void @f2(%struct.s2* noalias sret %agg.result)
+s2 f2() {
+  s2 foo;
+  return foo;
+}
+
+typedef struct {
+  int cc;
+  int dd;
+} s3;
+// CHECK: define void @f3(%struct.s3* noalias sret %agg.result)
+s3 f3() {
+  s3 foo;
+  return foo;
+}
+
+// CHECK: define void @f4(i64 %i)
+void f4(long long i) {}
+
+// CHECK: define void @f5(i8 signext %a, i16 signext %b)
+void f5(signed char a, short b) {}
+
+// CHECK: define void @f6(i8 zeroext %a, i16 zeroext %b)
+void f6(unsigned char a, unsigned short b) {}
+
+enum my_enum {
+  ENUM1,
+  ENUM2,
+  ENUM3,
+};
+// Enums should be treated as the underlying i32.
+// CHECK: define void @f7(i32 %a)
+void f7(enum my_enum a) {}
+
+enum my_big_enum {
+  ENUM4 = 0x,
+};
+// Big enums should be treated as the underlying i64.
+// CHECK: define void @f8(i64 %a)
+void f8(enum my_big_enum a) {}
+
+union simple_union {
+  int a;
+  char b;
+};
+// Unions should be passed inreg.
+// CHECK: define void @f9(i32 %s.coerce)
+void f9(union simple_union s) {}
+
+typedef struct {
+  int b4 : 4;
+  int b3 : 3;
+  int b8 : 8;
+} bitfield1;
+// Bitfields should be passed inreg.
+// CHECK: define void @f10(i32 %bf1.coerce)
+void f10(bitfield1 bf1) {}
+
+// CHECK: define { float, float } @cplx1(float %r)
+_Complex float cplx1(float r) {
+  return r + 2.0fi;
+}
+
+// CHECK: define { double, double } @cplx2(double %r)
+_Complex double cplx2(double r) {
+  return r + 2.0i;
+}
+
+// CHECK: define { i32, i32 } @cplx3(i32 %r)
+_Complex int cplx3(int r) {
+  return r + 2i;
+}
+
+// CHECK: define { i64, i64 } @cplx4(i64 %r)
+_Complex long long cplx4(long long r) {
+  return r + 2i;
+}
+
+// CHECK: define { i8, i8 } @cplx6(i8 signext %r)
+_Complex signed char cplx6(signed char r) {
+  return r + 2i;
+}
+
+// CHECK: define { i16, i16 } @cplx7(i16 signext %r)
+_Complex short cplx7(short r) {
+  return r + 2i;
+}
+
+typedef struct {
+  int aa; int bb;
+} s8;
+
+typedef struct {
+  int aa; int bb; int cc; int dd;
+} s16;
+
+// Use 16-byte struct 2 times, gets 8 registers.
+void st2(s16 a, s16 b) {}
+// CHECK: define void @st2(i32 %a.coerce0, i32 %a.coerce1, i32 %a.coerce2, i32 %a.coerce3, i32 %b.coerce0, i32 %b.coerce1, i32 %b.coerce2, i32 %b.coerce3)
+
+// Use 8-byte struct 3 times, gets 8 registers, 1 byval struct argument.
+void st3(s16 a, s16 b, s16 c) {}
+// CHECK: define void @st3(i3

[PATCH] D43089: clang: Add ARCTargetInfo

[PATCH] D43089: clang: Add ARCTargetInfo

[PATCH] D43089: clang: Add ARCTargetInfo

[PATCH] D43089: clang: Add ARCTargetInfo

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