[PATCH] D134821: [flang][driver] Allow main program to be in an archive

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

In D134821#4304690 , @awarzynski 
wrote:

> I've just reverted this patch - for context please see 
> https://reviews.llvm.org/D149429.
>
> @sunshaoce This was committed 
>  without 
> acknowledging @ekieri 's contribution, so didn't follow the official 
> guidelines: Attribution of Changes 
> . IMHO, we 
> should keep Emil as the author of this change (he has done the lion share of 
> this highly non-trivial work) and add you as a co-author 
> .
>  Unless @ekieri has some other preference :) (I am happy as long as we follow 
> the guidelines).
>
> Either way, thank you **both** for contributing! Now, lets try to figure out 
> what caused the issue with the bots.

Sorry for not following the official attribution guidelines. I agree with your 
suggestion to keep @ekieri as the main author. Thank you!


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[PATCH] D134821: [flang][driver] Allow main program to be in an archive

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG876df74dd471: [flang][driver] Allow main program to be in an 
archive (authored by sunshaoce).

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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  flang/docs/FlangDriver.md
  flang/test/CMakeLists.txt
  flang/test/Driver/link-c-main.c
  flang/test/Driver/link-f90-main.f90
  flang/test/Driver/linker-flags.f90

Index: flang/test/Driver/linker-flags.f90
===
--- flang/test/Driver/linker-flags.f90
+++ flang/test/Driver/linker-flags.f90
@@ -12,6 +12,14 @@
 !   Make sure they're not added.
 ! RUN: %flang -### -flang-experimental-exec -target aarch64-windows-msvc %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,MSVC --implicit-check-not libcmt --implicit-check-not oldnames
 
+! Check linker invocation to generate shared object (only GNU toolchain for now)
+! Output should not contain any undefined reference to _QQmain since it is not
+! considered a valid entry point for shared objects, which are usually specified
+! using the bind attribute.
+! RUN: %flang -### -flang-experimental-exec -shared -target x86_64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARED --implicit-check-not _QQmain
+! RUN: %flang -### -flang-experimental-exec -shared -target aarch64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARED --implicit-check-not _QQmain
+! RUN: %flang -### -flang-experimental-exec -shared -target riscv64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARED --implicit-check-not _QQmain
+
 ! Compiler invocation to generate the object file
 ! CHECK-LABEL: {{.*}} "-emit-obj"
 ! CHECK-SAME:  "-o" "[[object_file:.*\.o]]" {{.*}}Inputs/hello.f90
@@ -23,6 +31,7 @@
 !   executable and may find the GNU linker from MinGW or Cygwin.
 ! GNU-LABEL:  "{{.*}}ld{{(\.exe)?}}"
 ! GNU-SAME: "[[object_file]]"
+! GNU-SAME: --undefined=_QQmain
 ! GNU-SAME: -lFortran_main
 ! GNU-SAME: -lFortranRuntime
 ! GNU-SAME: -lFortranDecimal
@@ -50,3 +59,9 @@
 ! MSVC-SAME: FortranDecimal.lib
 ! MSVC-SAME: /subsystem:console
 ! MSVC-SAME: "[[object_file]]"
+
+! Linker invocation to generate a shared object
+! GNU-SHARED-LABEL:  "{{.*}}ld"
+! GNU-SHARED-SAME: "[[object_file]]"
+! GNU-SHARED-SAME: -lFortranRuntime
+! GNU-SHARED-SAME: -lFortranDecimal
Index: flang/test/Driver/link-f90-main.f90
===
--- /dev/null
+++ flang/test/Driver/link-f90-main.f90
@@ -0,0 +1,23 @@
+! Test that a fortran main program can be linked to an executable
+! by flang.
+!
+! For now, this test only covers the Gnu toolchain on linux.
+
+!REQUIRES: x86-registered-target || aarch64-registered-target || riscv64-registered-target
+!REQUIRES: system-linux
+
+! RUN: %flang_fc1 -emit-obj %s -o %t.o
+! RUN: %flang -target x86_64-unknown-linux-gnu %t.o -o %t.out -flang-experimental-exec
+! RUN: llvm-objdump --syms %t.out | FileCheck %s
+
+! Test that it also works if the program is bundled in an archive.
+
+! RUN: llvm-ar -r %t.a %t.o
+! RUN: %flang -target x86_64-unknown-linux-gnu %t.a -o %ta.out -flang-experimental-exec
+! RUN: llvm-objdump --syms %ta.out | FileCheck %s
+
+end program
+
+! CHECK-DAG: F .text {{[a-f0-9]+}} main
+! CHECK-DAG: F .text {{[a-f0-9]+}} _QQmain
+! CHECK-DAG: _FortranAProgramStart
Index: flang/test/Driver/link-c-main.c
===
--- /dev/null
+++ flang/test/Driver/link-c-main.c
@@ -0,0 +1,28 @@
+/*
+Test that an object file with a C main function can be linked to an executable
+by Flang.
+
+For now, this test only covers the Gnu toolchain on Linux.
+
+REQUIRES: x86-registered-target || aarch64-registered-target || riscv64-registered-target
+REQUIRES: system-linux, c-compiler
+
+RUN: %cc -c %s -o %t.o
+RUN: %flang -target x86_64-unknown-linux-gnu %t.o -o %t.out -flang-experimental-exec
+RUN: llvm-objdump --syms %t.out | FileCheck %s --implicit-check-not Fortran
+
+Test that it also works if the c-main is bundled in an archive.
+
+RUN: llvm-ar -r %t.a %t.o
+RUN: %flang -target x86_64-unknown-linux-gnu %t.a -o %ta.out -flang-experimental-exec
+RUN: llvm-objdump --syms %ta.out | FileCheck %s --implicit-check-not Fortran
+*/
+
+int main(void) {
+return 0;
+}
+
+/*
+CHECK-DAG: F .text {{[a-f0-9]+}} main
+CHECK-DAG: *UND* {{[a-f0-9]+}} _QQmain
+*/
Index: flang/test/CMakeLists.txt
===
--- flang/test/CMakeLists.txt
+++ flang/test/CMakeLists.txt
@@ -57,6 +57,7 @@
   fir-opt
   tco
   bbc
+  llvm-ar
   llvm-dis
   llvm-objdump
   llvm-readobj
Index: flang/docs/FlangDriver.md

[PATCH] D134821: [flang][driver] Allow main program to be in an archive

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sunshaoce added a comment.

Any further suggestions?


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[PATCH] D134821: [flang][driver] Allow main program to be in an archive

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sunshaoce updated this revision to Diff 516651.
sunshaoce added a comment.

Address @awarzynski's comments


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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  flang/docs/FlangDriver.md
  flang/test/CMakeLists.txt
  flang/test/Driver/link-c-main.c
  flang/test/Driver/link-f90-main.f90
  flang/test/Driver/linker-flags.f90

Index: flang/test/Driver/linker-flags.f90
===
--- flang/test/Driver/linker-flags.f90
+++ flang/test/Driver/linker-flags.f90
@@ -12,6 +12,14 @@
 !   Make sure they're not added.
 ! RUN: %flang -### -flang-experimental-exec -target aarch64-windows-msvc %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,MSVC --implicit-check-not libcmt --implicit-check-not oldnames
 
+! Check linker invocation to generate shared object (only GNU toolchain for now)
+! Output should not contain any undefined reference to _QQmain since it is not
+! considered a valid entry point for shared objects, which are usually specified
+! using the bind attribute.
+! RUN: %flang -### -flang-experimental-exec -shared -target x86_64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARED --implicit-check-not _QQmain
+! RUN: %flang -### -flang-experimental-exec -shared -target aarch64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARED --implicit-check-not _QQmain
+! RUN: %flang -### -flang-experimental-exec -shared -target riscv64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARED --implicit-check-not _QQmain
+
 ! Compiler invocation to generate the object file
 ! CHECK-LABEL: {{.*}} "-emit-obj"
 ! CHECK-SAME:  "-o" "[[object_file:.*\.o]]" {{.*}}Inputs/hello.f90
@@ -23,6 +31,7 @@
 !   executable and may find the GNU linker from MinGW or Cygwin.
 ! GNU-LABEL:  "{{.*}}ld{{(\.exe)?}}"
 ! GNU-SAME: "[[object_file]]"
+! GNU-SAME: --undefined=_QQmain
 ! GNU-SAME: -lFortran_main
 ! GNU-SAME: -lFortranRuntime
 ! GNU-SAME: -lFortranDecimal
@@ -50,3 +59,9 @@
 ! MSVC-SAME: FortranDecimal.lib
 ! MSVC-SAME: /subsystem:console
 ! MSVC-SAME: "[[object_file]]"
+
+! Linker invocation to generate a shared object
+! GNU-SHARED-LABEL:  "{{.*}}ld"
+! GNU-SHARED-SAME: "[[object_file]]"
+! GNU-SHARED-SAME: -lFortranRuntime
+! GNU-SHARED-SAME: -lFortranDecimal
Index: flang/test/Driver/link-f90-main.f90
===
--- /dev/null
+++ flang/test/Driver/link-f90-main.f90
@@ -0,0 +1,23 @@
+! Test that a fortran main program can be linked to an executable
+! by flang.
+!
+! For now, this test only covers the Gnu toolchain on linux.
+
+!REQUIRES: x86-registered-target || aarch64-registered-target || riscv64-registered-target
+!REQUIRES: system-linux
+
+! RUN: %flang_fc1 -emit-obj %s -o %t.o
+! RUN: %flang -target x86_64-unknown-linux-gnu %t.o -o %t.out -flang-experimental-exec
+! RUN: llvm-objdump --syms %t.out | FileCheck %s
+
+! Test that it also works if the program is bundled in an archive.
+
+! RUN: llvm-ar -r %t.a %t.o
+! RUN: %flang -target x86_64-unknown-linux-gnu %t.a -o %ta.out -flang-experimental-exec
+! RUN: llvm-objdump --syms %ta.out | FileCheck %s
+
+end program
+
+! CHECK-DAG: F .text {{[a-f0-9]+}} main
+! CHECK-DAG: F .text {{[a-f0-9]+}} _QQmain
+! CHECK-DAG: _FortranAProgramStart
Index: flang/test/Driver/link-c-main.c
===
--- /dev/null
+++ flang/test/Driver/link-c-main.c
@@ -0,0 +1,28 @@
+/*
+Test that an object file with a C main function can be linked to an executable
+by Flang.
+
+For now, this test only covers the Gnu toolchain on Linux.
+
+REQUIRES: x86-registered-target || aarch64-registered-target || riscv64-registered-target
+REQUIRES: system-linux, c-compiler
+
+RUN: %cc -c %s -o %t.o
+RUN: %flang -target x86_64-unknown-linux-gnu %t.o -o %t.out -flang-experimental-exec
+RUN: llvm-objdump --syms %t.out | FileCheck %s --implicit-check-not Fortran
+
+Test that it also works if the c-main is bundled in an archive.
+
+RUN: llvm-ar -r %t.a %t.o
+RUN: %flang -target x86_64-unknown-linux-gnu %t.a -o %ta.out -flang-experimental-exec
+RUN: llvm-objdump --syms %ta.out | FileCheck %s --implicit-check-not Fortran
+*/
+
+int main(void) {
+return 0;
+}
+
+/*
+CHECK-DAG: F .text {{[a-f0-9]+}} main
+CHECK-DAG: *UND* {{[a-f0-9]+}} _QQmain
+*/
Index: flang/test/CMakeLists.txt
===
--- flang/test/CMakeLists.txt
+++ flang/test/CMakeLists.txt
@@ -57,6 +57,7 @@
   fir-opt
   tco
   bbc
+  llvm-ar
   llvm-dis
   llvm-objdump
   llvm-readobj
Index: flang/docs/FlangDriver.md
===
--- flang/docs/FlangDriver.md
+++ flang/docs/FlangDriver.md
@@ -149,13 +149,6 @@
 +- 3: backend, {2}, assembler
 4: 

[PATCH] D134821: [flang][driver] Allow main program to be in an archive

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 516476.
sunshaoce added a comment.
This revision is now accepted and ready to land.
Herald added subscribers: pcwang-thead, s.egerton, simoncook, asb.

Address comments


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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  flang/docs/FlangDriver.md
  flang/test/CMakeLists.txt
  flang/test/Driver/link-c-main.c
  flang/test/Driver/link-f90-main.f90
  flang/test/Driver/linker-flags.f90

Index: flang/test/Driver/linker-flags.f90
===
--- flang/test/Driver/linker-flags.f90
+++ flang/test/Driver/linker-flags.f90
@@ -12,6 +12,11 @@
 !   Make sure they're not added.
 ! RUN: %flang -### -flang-experimental-exec -target aarch64-windows-msvc %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,MSVC --implicit-check-not libcmt --implicit-check-not oldnames
 
+! Check linker invocation to generate shared object (only GNU toolchain for now)
+! RUN: %flang -### -flang-experimental-exec -shared -target x86_64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARD --implicit-check-not _QQmain
+! RUN: %flang -### -flang-experimental-exec -shared -target aarch64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARD --implicit-check-not _QQmain
+! RUN: %flang -### -flang-experimental-exec -shared -target riscv64-linux-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,GNU-SHARD --implicit-check-not _QQmain
+
 ! Compiler invocation to generate the object file
 ! CHECK-LABEL: {{.*}} "-emit-obj"
 ! CHECK-SAME:  "-o" "[[object_file:.*\.o]]" {{.*}}Inputs/hello.f90
@@ -23,6 +28,7 @@
 !   executable and may find the GNU linker from MinGW or Cygwin.
 ! GNU-LABEL:  "{{.*}}ld{{(\.exe)?}}"
 ! GNU-SAME: "[[object_file]]"
+! GNU-SAME: --undefined=_QQmain
 ! GNU-SAME: -lFortran_main
 ! GNU-SAME: -lFortranRuntime
 ! GNU-SAME: -lFortranDecimal
@@ -50,3 +56,9 @@
 ! MSVC-SAME: FortranDecimal.lib
 ! MSVC-SAME: /subsystem:console
 ! MSVC-SAME: "[[object_file]]"
+
+! Linker invocation to generate a shared object
+! GNU-SHARD-LABEL:  "{{.*}}ld"
+! GNU-SHARD-SAME: "[[object_file]]"
+! GNU-SHARD-SAME: -lFortranRuntime
+! GNU-SHARD-SAME: -lFortranDecimal
Index: flang/test/Driver/link-f90-main.f90
===
--- /dev/null
+++ flang/test/Driver/link-f90-main.f90
@@ -0,0 +1,23 @@
+! Test that a fortran main program can be linked to an executable
+! by flang.
+!
+! For now, this test only covers the Gnu toolchain on linux.
+
+!REQUIRES: x86-registered-target || aarch64-registered-target || riscv64-registered-target
+!REQUIRES: system-linux
+
+! RUN: %flang_fc1 -emit-obj %s -o %t.o
+! RUN: %flang -target x86_64-unknown-linux-gnu %t.o -o %t.out -flang-experimental-exec
+! RUN: llvm-objdump --syms %t.out | FileCheck %s
+
+! Test that it also works if the program is bundled in an archive.
+
+! RUN: llvm-ar -r %t.a %t.o
+! RUN: %flang -target x86_64-unknown-linux-gnu %t.a -o %ta.out -flang-experimental-exec
+! RUN: llvm-objdump --syms %ta.out | FileCheck %s
+
+end program
+
+! CHECK-DAG: F .text {{[a-f0-9]+}} main
+! CHECK-DAG: F .text {{[a-f0-9]+}} _QQmain
+! CHECK-DAG: _FortranAProgramStart
Index: flang/test/Driver/link-c-main.c
===
--- /dev/null
+++ flang/test/Driver/link-c-main.c
@@ -0,0 +1,28 @@
+/*
+Test that an object file with a c main function can be linked to an executable
+by flang.
+
+For now, this test only covers the Gnu toolchain on linux.
+
+REQUIRES: x86-registered-target || aarch64-registered-target || riscv64-registered-target
+REQUIRES: system-linux, c-compiler
+
+RUN: %cc -c %s -o %t.o
+RUN: %flang -target x86_64-unknown-linux-gnu %t.o -o %t.out -flang-experimental-exec
+RUN: llvm-objdump --syms %t.out | FileCheck %s --implicit-check-not Fortran
+
+Test that it also works if the c-main is bundled in an archive.
+
+RUN: llvm-ar -r %t.a %t.o
+RUN: %flang -target x86_64-unknown-linux-gnu %t.a -o %ta.out -flang-experimental-exec
+RUN: llvm-objdump --syms %ta.out | FileCheck %s --implicit-check-not Fortran
+*/
+
+int main(void) {
+return 0;
+}
+
+/*
+CHECK-DAG: F .text {{[a-f0-9]+}} main
+CHECK-DAG: *UND* {{[a-f0-9]+}} _QQmain
+*/
Index: flang/test/CMakeLists.txt
===
--- flang/test/CMakeLists.txt
+++ flang/test/CMakeLists.txt
@@ -57,6 +57,7 @@
   fir-opt
   tco
   bbc
+  llvm-ar
   llvm-dis
   llvm-objdump
   llvm-readobj
Index: flang/docs/FlangDriver.md
===
--- flang/docs/FlangDriver.md
+++ flang/docs/FlangDriver.md
@@ -149,13 +149,6 @@
 +- 3: backend, {2}, assembler
 4: assembler, {3}, object
 ```
-Note that currently Flang does not support code-generation and 

[PATCH] D134821: [flang][driver] Allow main program to be in an archive

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sunshaoce added a comment.

I would like to help land this patch.


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce added a subscriber: DavidSpickett.
sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:1
+! Test -emit-obj (RISC-V 64)
+

mamrami wrote:
> sunshaoce wrote:
> > awarzynski wrote:
> > > mamrami wrote:
> > > > Hi :)
> > > > It seems like the test fails: 
> > > > https://buildkite.com/llvm-project/premerge-checks/builds/141302#0186e55e-199e-401d-ab9f-9f3d47ec87af
> > > > I see it in my non related patch https://reviews.llvm.org/D146132
> > > Sorry about that :(
> > > 
> > > ```
> > >  line 3: llvm-readelf: command not found
> > > ```
> > > 
> > > There are 3 options:
> > > * revert
> > > * add `llvm-readelf` here 
> > > https://github.com/llvm/llvm-project/blob/main/flang/test/CMakeLists.txt#L61
> > > * updated the test to use `llvm-objdump` instead
> > > 
> > > HTH.
> > Thanks! I've submitted in https://reviews.llvm.org/D146204.
> Hi again!
> The test passed after the fix but it fails again:
> https://buildkite.com/llvm-project/premerge-checks/builds/141905#0186fa14-2339-4c0c-9966-dea23592a86b
> 
I noticed this error before, but @DavidSpickett haven't fixed yet. I'll fix it 
now.
https://reviews.llvm.org/rG9f93b71f20ea


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:1
+! Test -emit-obj (RISC-V 64)
+

awarzynski wrote:
> mamrami wrote:
> > Hi :)
> > It seems like the test fails: 
> > https://buildkite.com/llvm-project/premerge-checks/builds/141302#0186e55e-199e-401d-ab9f-9f3d47ec87af
> > I see it in my non related patch https://reviews.llvm.org/D146132
> Sorry about that :(
> 
> ```
>  line 3: llvm-readelf: command not found
> ```
> 
> There are 3 options:
> * revert
> * add `llvm-readelf` here 
> https://github.com/llvm/llvm-project/blob/main/flang/test/CMakeLists.txt#L61
> * updated the test to use `llvm-objdump` instead
> 
> HTH.
Thanks! I've submitted in https://reviews.llvm.org/D146204.


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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This revision was automatically updated to reflect the committed changes.
sunshaoce marked an inline comment as done.
Closed by commit rG36278b735fa1: [Flang][RISCV] Emit target features for RISC-V 
(authored by sunshaoce).

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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features-invalid.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
 
 
 ! CHECK-A57: "-fc1" "-triple" "aarch64-unknown-linux-gnu"
@@ -52,5 +44,5 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
-! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
-! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
Index: flang/test/Driver/target-cpu-features-invalid.f90
===
--- /dev/null
+++ flang/test/Driver/target-cpu-features-invalid.f90
@@ -0,0 +1,13 @@
+! REQUIRES: aarch64-registered-target
+
+! Test that invalid cpu and features are ignored.
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+
+
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,17 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! 0x5 means set EF_RISCV_RVC (0x1) and EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -105,7 +105,7 @@
   default:
 break;
   case llvm::Triple::aarch64:
-[[fallthrough]];
+  case llvm::Triple::riscv64:
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu 

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 505363.
sunshaoce added a comment.

Address @MaskRay's comment


Repository:
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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features-invalid.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
 
 
 ! CHECK-A57: "-fc1" "-triple" "aarch64-unknown-linux-gnu"
@@ -52,5 +44,5 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
-! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
-! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
Index: flang/test/Driver/target-cpu-features-invalid.f90
===
--- /dev/null
+++ flang/test/Driver/target-cpu-features-invalid.f90
@@ -0,0 +1,13 @@
+! REQUIRES: aarch64-registered-target
+
+! Test that invalid cpu and features are ignored.
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
+! RUN:   -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+
+
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,17 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! 0x5 means set EF_RISCV_RVC (0x1) and EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -105,7 +105,7 @@
   default:
 break;
   case llvm::Triple::aarch64:
-[[fallthrough]];
+  case llvm::Triple::riscv64:
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce added a comment.

Any other opinions? If not, I will land it later.


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:7
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s

awarzynski wrote:
> jrtc27 wrote:
> > Why do we need to go to an object file??? That's terrible practice in Clang 
> > tests, and the same should be true of Flang. Test the IR, that is 
> > sufficient, and decouples you from the backend.
> > That's terrible practice in Clang tests, and the same should be true of 
> > Flang. Test the IR, that is sufficient, and decouples you from the backend.
> 
> I disagree. 
> 
> A compiler driver is responsible for creating a correct backend/LLVM 
> invocation. Is there some other way to verify that the backend invocation is 
> correct? (other then inspecting the generated machine code file).
> 
> I agree that it is desirable to avoid any architectural details leaking 
> outside of LLVM (into e.g. Clang and/or Flang), but IMHO it's very hard to 
> avoid in practice.
After my test, there is no difference between the LLVM IR generated before and 
after modification. These tests are also from or similar to those that already 
exist.

So I think we can land this patch first. Then fix these in a new patch.


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504756.
sunshaoce marked 2 inline comments as done.
sunshaoce added a comment.

Add `target-cpu-features-invalid.f90`


Repository:
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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features-invalid.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
-! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
 
 
 ! CHECK-A57: "-fc1" "-triple" "aarch64-unknown-linux-gnu"
@@ -52,5 +44,5 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
-! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
-! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
Index: flang/test/Driver/target-cpu-features-invalid.f90
===
--- /dev/null
+++ flang/test/Driver/target-cpu-features-invalid.f90
@@ -0,0 +1,13 @@
+! REQUIRES: aarch64-registered-target
+
+! Test that invalid cpu and features are ignored.
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
+! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
+
+! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
+! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s 
-check-prefix=CHECK-INVALID-FEATURE
+
+
+! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
+! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,17 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! 0x5 means set EF_RISCV_RVC (0x1) and EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,5 +1,3 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
-
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
 
@@ -22,14 +20,8 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
-
-! Test that invalid cpu and features are ignored.
-
-! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \
-! RUN: -o /dev/null -S %s 2>&1 | 

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce marked 5 inline comments as done.
sunshaoce added inline comments.



Comment at: flang/test/Driver/target-cpu-features.f90:33
 ! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
 
 ! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \

Without `REQUIRES` line, test will be failed here.

Due to this patch has little to do with CPU-feature, I think we can only add 
`code-gen-rv64.f90`. How about that?


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sunshaoce added inline comments.



Comment at: flang/test/Driver/code-gen-rv64.f90:12
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program

awarzynski wrote:
> awarzynski wrote:
> > For those of us less familiar with RISC-V - could you explain what's 
> > significant about this line? For example, [[ 
> > https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/flang/test/Driver/code-gen-aarch64.f90#L18
> >  | here ]] it is made clear that with the right triple used, one should see 
> > a `ret` instruction within the main function (`_QQmain`). In here, I just 
> > see a "magic" number :)
> Follow-up questions - what's "Flags" and why "0x5"? Is there any online 
> documentation that you can refer to here?
You can refer: 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0/riscv-abi.pdf
  `8.1. File Header` `e_flags` section


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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

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sunshaoce updated this revision to Diff 504695.
sunshaoce added a comment.

Add `REQUIRES` in tests


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Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,4 +1,4 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
+! REQUIRES: aarch64-registered-target, x86-registered-target, 
riscv-registered-target
 
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,16 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -1,4 +1,4 @@
-! REQUIRES: aarch64-registered-target, x86-registered-target
+! REQUIRES: aarch64-registered-target, x86-registered-target, riscv-registered-target
 
 ! Test that -mcpu/march are used and that the -target-cpu and -target-features
 ! are also added to the fc1 command.
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,16 @@
+! Test -emit-obj (RISC-V 64)
+
+! REQUIRES: riscv-registered-target
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang 

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504672.
sunshaoce marked an inline comment as done.
sunshaoce added a comment.

Address @awarzynski's comment. Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,14 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,14 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! If Flang failed to emit target-feature info, then Flags will be 0x0.
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, 

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504616.
sunshaoce added a comment.

Add test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/code-gen-rv64.f90
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,13 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,9 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +55,9 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: flang/test/Driver/code-gen-rv64.f90
===
--- /dev/null
+++ flang/test/Driver/code-gen-rv64.f90
@@ -0,0 +1,13 @@
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
+! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \
+! RUN:   -target-feature +d -target-feature +c -emit-obj %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! RUN: rm -f %t.o
+! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o
+! RUN: llvm-readelf -h %t.o | FileCheck %s
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -106,6 +106,8 @@
 break;
   case llvm::Triple::aarch64:
 [[fallthrough]];
+  case llvm::Triple::riscv64:
+[[fallthrough]];
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;
___
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[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504548.
sunshaoce added a comment.

Based on everyone's comments, I merged the test into `target-cpu-features.f90` 
and only kept the generic `-target-feature`. At the same time, I removed the 
`switch (TC.getArch())` and passed the test on x86 and RISC-V 64.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/target-cpu-features.f90


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,12 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv32-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV32
+
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +58,12 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" 
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" 
"-target-feature" "-fsgsbase"
 
+! CHECK-RV32: "-fc1" "-triple" "riscv32-unknown-linux-gnu"
+! CHECK-RV32-SAME: "-target-cpu" "generic-rv32" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c" "-target-feature" "-e"
+
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" 
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" 
"-target-feature" "+c" "-target-feature" "-e"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target 
(ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this 
target (ignoring feature)
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -101,15 +101,7 @@
   }
 
   // Add the target features.
-  switch (TC.getArch()) {
-  default:
-break;
-  case llvm::Triple::aarch64:
-[[fallthrough]];
-  case llvm::Triple::x86_64:
-getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
-break;
-  }
+  getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 
   // TODO: Add target specific flags, ABI, mtune option etc.
 }


Index: flang/test/Driver/target-cpu-features.f90
===
--- flang/test/Driver/target-cpu-features.f90
+++ flang/test/Driver/target-cpu-features.f90
@@ -22,6 +22,12 @@
 ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \
 ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H
 
+! RUN: %flang --target=riscv32-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV32
+
+! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
 
 ! Test that invalid cpu and features are ignored.
 
@@ -52,5 +58,12 @@
 ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu"
 ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase"
 
+! CHECK-RV32: "-fc1" "-triple" "riscv32-unknown-linux-gnu"
+! CHECK-RV32-SAME: "-target-cpu" "generic-rv32" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "-e"
+
+! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" "-target-feature" "-e"
+
+
 ! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor)
 ! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature)
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -101,15 +101,7 @@
   }
 
   // Add the target features.
-  switch (TC.getArch()) {
-  default:
-break;
-  case llvm::Triple::aarch64:
-[[fallthrough]];
-  case llvm::Triple::x86_64:
-getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
-break;
-  }
+  getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 
   // TODO: Add target specific flags, ABI, mtune option etc.
 }
___
cfe-commits mailing list

[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: awarzynski, klausler, clementval, sscalpone, 
craig.topper, jrtc27, kito-cheng.
Herald added subscribers: VincentWu, vkmr, evandro, luismarques, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rogfer01, shiva0217, 
simoncook, arichardson.
Herald added projects: Flang, All.
sunshaoce requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, jdoerfert, MaskRay.
Herald added a project: clang.

Fix the issue of .o file generated by `Flang` 
with `Flags` info is 0x0 under RISC-V.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145883

Files:
  clang/lib/Driver/ToolChains/Flang.cpp
  flang/test/Driver/target-features.f90


Index: flang/test/Driver/target-features.f90
===
--- /dev/null
+++ flang/test/Driver/target-features.f90
@@ -0,0 +1,4 @@
+! RUN: %flang --target=riscv64-linux-gnu --target=riscv64 -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
+! CHECK-RV64: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" 
"+c" "-target-feature" "-e" "-target-feature" "-f" "-target-feature" "-d" 
"-target-feature" "-h" "-target-feature" "-zihintpause" "-target-feature" 
"-zfhmin" "-target-feature" "-zfh" "-target-feature" "-zfinx" "-target-feature" 
"-zdinx" "-target-feature" "-zhinxmin" "-target-feature" "-zhinx" 
"-target-feature" "-zba" "-target-feature" "-zbb" "-target-feature" "-zbc" 
"-target-feature" "-zbs" "-target-feature" "-zbkb" "-target-feature" "-zbkc" 
"-target-feature" "-zbkx" "-target-feature" "-zknd" "-target-feature" "-zkne" 
"-target-feature" "-zknh" "-target-feature" "-zksed" "-target-feature" "-zksh" 
"-target-feature" "-zkr" "-target-feature" "-zkn" "-target-feature" "-zks" 
"-target-feature" "-zkt" "-target-feature" "-zk" "-target-feature" "-zmmul" 
"-target-feature" "-v" "-target-feature" "-zvl32b" "-target-feature" "-zvl64b" 
"-target-feature" "-zvl128b" "-target-feature" "-zvl256b" "-target-feature" 
"-zvl512b" "-target-feature" "-zvl1024b" "-target-feature" "-zvl2048b" 
"-target-feature" "-zvl4096b" "-target-feature" "-zvl8192b" "-target-feature" 
"-zvl16384b" "-target-feature" "-zvl32768b" "-target-feature" "-zvl65536b" 
"-target-feature" "-zve32x" "-target-feature" "-zve32f" "-target-feature" 
"-zve64x" "-target-feature" "-zve64f" "-target-feature" "-zve64d" 
"-target-feature" "-zicbom" "-target-feature" "-zicboz" "-target-feature" 
"-zicbop" "-target-feature" "-zicsr" "-target-feature" "-zifencei" 
"-target-feature" "-zawrs" "-target-feature" "-svnapot" "-target-feature" 
"-svpbmt" "-target-feature" "-svinval" "-target-feature" "-xtheadba" 
"-target-feature" "-xtheadbb" "-target-feature" "-xtheadbs" "-target-feature" 
"-xtheadcmo" "-target-feature" "-xtheadcondmov" "-target-feature" 
"-xtheadfmemidx" "-target-feature" "-xtheadmac" "-target-feature" 
"-xtheadmemidx" "-target-feature" "-xtheadmempair" "-target-feature" 
"-xtheadsync" "-target-feature" "-xtheadvdot" "-target-feature" 
"-xventanacondops" "-target-feature" "-experimental-zihintntl" 
"-target-feature" "-experimental-zca" "-target-feature" "-experimental-zcb" 
"-target-feature" "-experimental-zcd" "-target-feature" "-experimental-zcf" 
"-target-feature" "-experimental-zfa" "-target-feature" "-experimental-zvfh" 
"-target-feature" "-experimental-ztso" "-target-feature" "+relax" 
"-target-feature" "-save-restore"
Index: clang/lib/Driver/ToolChains/Flang.cpp
===
--- clang/lib/Driver/ToolChains/Flang.cpp
+++ clang/lib/Driver/ToolChains/Flang.cpp
@@ -109,6 +109,9 @@
   case llvm::Triple::x86_64:
 getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
 break;
+  case llvm::Triple::riscv64:
+getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false);
+break;
   }
 
   // TODO: Add target specific flags, ABI, mtune option etc.


Index: flang/test/Driver/target-features.f90
===
--- /dev/null
+++ flang/test/Driver/target-features.f90
@@ -0,0 +1,4 @@
+! RUN: %flang --target=riscv64-linux-gnu --target=riscv64 -c %s -### 2>&1 \
+! RUN: | FileCheck %s -check-prefix=CHECK-RV64
+
+! CHECK-RV64: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c" "-target-feature" "-e" "-target-feature" "-f" "-target-feature" "-d" "-target-feature" "-h" "-target-feature" "-zihintpause" "-target-feature" "-zfhmin" "-target-feature" "-zfh" "-target-feature" "-zfinx" "-target-feature" "-zdinx" "-target-feature" "-zhinxmin" "-target-feature" "-zhinx" "-target-feature" "-zba" "-target-feature" "-zbb" "-target-feature" "-zbc" "-target-feature" "-zbs" "-target-feature" "-zbkb" "-target-feature" "-zbkc" "-target-feature" "-zbkx" "-target-feature" "-zknd" "-target-feature" "-zkne" "-target-feature" "-zknh" "-target-feature" "-zksed" "-target-feature" "-zksh" "-target-feature" "-zkr" 

[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb1fdcd5fbc09: [Flang] Allow compile *.f03, *.f08 file 
(authored by sunshaoce).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504372.
sunshaoce added a comment.

Fix the issue of failing in the MSVC environment.


Repository:
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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce reopened this revision.
sunshaoce added a comment.
This revision is now accepted and ready to land.

Sorry! My previous tests were not comprehensive enough, which resulted in 
failures in the MSVC environment.


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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
sunshaoce marked an inline comment as done.
Closed by commit rG171794de533b: [Flang] Allow compile *.f03, *.f08 file 
(authored by sunshaoce).

Repository:
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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504363.
sunshaoce marked 2 inline comments as done.
sunshaoce added a comment.

Sorry, I just missed a comment.


Repository:
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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504362.
sunshaoce added a comment.

Address @awarzynski's comment


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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/supported-suffices/f03-suffix.f03
  flang/test/Driver/supported-suffices/f08-suffix.f08


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/supported-suffices/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/supported-suffices/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504360.
sunshaoce added a comment.

Remove -flang-experimental-exec


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Files:
  clang/lib/Driver/Types.cpp
  flang/test/Driver/f03-suffix.f03
  flang/test/Driver/f08-suffix.f08


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

Before

  $ /home/sunshaoce/dev/llvm-project/build/bin/flang-new 
/home/sunshaoce/dev/llvm-project/build/temp.f03 -flang-experimental-exec -o 
temp.out -###
  flang-new version 17.0.0 (https://github.com/llvm/llvm-project.git 
890e6c871d31dca9e461c01118cf25fb303b9cad)
  Target: x86_64-unknown-linux-gnu
  Thread model: posix
  InstalledDir: /home/sunshaoce/dev/llvm-project/build/bin
   "/usr/bin/ld" "-pie" "-z" "relro" "--hash-style=gnu" "--eh-frame-hdr" "-m" 
"elf_x86_64" "-dynamic-linker" "/lib64/ld-linux-x86-64.so.2" "-o" "temp.out" 
"/lib/x86_64-linux-gnu/Scrt1.o" "/lib/x86_64-linux-gnu/crti.o" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtbeginS.o" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9/../../../../lib64" "-L/lib/x86_64-linux-gnu" 
"-L/lib/../lib64" "-L/usr/lib/x86_64-linux-gnu" "-L/usr/lib/../lib64" "-L/lib" 
"-L/usr/lib" "/home/sunshaoce/dev/llvm-project/build/temp.f03" 
"-L/home/sunshaoce/dev/llvm-project/build/lib" "-lFortran_main" 
"-lFortranRuntime" "-lFortranDecimal" "-lm" "-lgcc" "--as-needed" "-lgcc_s" 
"--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtendS.o" "/lib/x86_64-linux-gnu/crtn.o"

after

  $ /home/sunshaoce/dev/llvm-project/build/bin/flang-new 
/home/sunshaoce/dev/llvm-project/build/temp.f03 -flang-experimental-exec -o 
temp.out -###
  flang-new version 17.0.0 (https://github.com/llvm/llvm-project.git 
890e6c871d31dca9e461c01118cf25fb303b9cad)
  Target: x86_64-unknown-linux-gnu
  Thread model: posix
  InstalledDir: /home/sunshaoce/dev/llvm-project/build/bin
   "/home/sunshaoce/dev/llvm-project/build/bin/flang-new" "-fc1" "-triple" 
"x86_64-unknown-linux-gnu" "-emit-obj" "-fcolor-diagnostics" 
"-mrelocation-model" "pic" "-pic-level" "2" "-pic-is-pie" "-target-cpu" 
"x86-64" "-o" "/tmp/temp-72c5c0.o" "-x" "f95-cpp-input" 
"/home/sunshaoce/dev/llvm-project/build/temp.f03"
   "/usr/bin/ld" "-pie" "-z" "relro" "--hash-style=gnu" "--eh-frame-hdr" "-m" 
"elf_x86_64" "-dynamic-linker" "/lib64/ld-linux-x86-64.so.2" "-o" "temp.out" 
"/lib/x86_64-linux-gnu/Scrt1.o" "/lib/x86_64-linux-gnu/crti.o" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtbeginS.o" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9" 
"-L/usr/lib/gcc/x86_64-linux-gnu/9/../../../../lib64" "-L/lib/x86_64-linux-gnu" 
"-L/lib/../lib64" "-L/usr/lib/x86_64-linux-gnu" "-L/usr/lib/../lib64" "-L/lib" 
"-L/usr/lib" "/tmp/temp-72c5c0.o" 
"-L/home/sunshaoce/dev/llvm-project/build/lib" "-lFortran_main" 
"-lFortranRuntime" "-lFortranDecimal" "-lm" "-lgcc" "--as-needed" "-lgcc_s" 
"--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" 
"/usr/lib/gcc/x86_64-linux-gnu/9/crtendS.o" "/lib/x86_64-linux-gnu/crtn.o"

So, I tested it by checking whether `flang` was called.


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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 504359.
sunshaoce added a comment.

Add tests


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Files:
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  flang/test/Driver/f03-suffix.f03
  flang/test/Driver/f08-suffix.f08


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: flang/test/Driver/f08-suffix.f08
===
--- /dev/null
+++ flang/test/Driver/f08-suffix.f08
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
Index: flang/test/Driver/f03-suffix.f03
===
--- /dev/null
+++ flang/test/Driver/f03-suffix.f03
@@ -0,0 +1,6 @@
+! RUN: %flang -### -flang-experimental-exec %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+! CHECK: "{{.*}}ld" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D145845: [Flang] Allow compile *.f03, *.f08 file

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: awarzynski, klausler, clementval, sscalpone.
Herald added a project: All.
sunshaoce requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Fix issue #61260


Repository:
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Files:
  clang/lib/Driver/Types.cpp


Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)


Index: clang/lib/Driver/Types.cpp
===
--- clang/lib/Driver/Types.cpp
+++ clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@
   .Case("cui", TY_PP_CUDA)
   .Case("cxx", TY_CXX)
   .Case("CXX", TY_CXX)
+  .Case("F03", TY_Fortran)
+  .Case("f03", TY_PP_Fortran)
+  .Case("F08", TY_Fortran)
+  .Case("f08", TY_PP_Fortran)
   .Case("F90", TY_Fortran)
   .Case("f90", TY_PP_Fortran)
   .Case("F95", TY_Fortran)
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[PATCH] D141698: doc: Rewrite opening paragraph of CFI Design Doc

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sunshaoce added a comment.

I tend to keep it as it is.


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[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce abandoned this revision.
sunshaoce added a comment.

A better implementation is in D143572 


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[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 495522.
sunshaoce added a comment.

Add a test


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Files:
  clang/include/clang/Driver/Options.h
  clang/include/clang/Driver/Options.td
  clang/include/clang/Driver/ToolChain.h
  clang/lib/Driver/ToolChain.cpp
  clang/lib/Driver/ToolChains/Flang.cpp
  clang/lib/Driver/ToolChains/Flang.h
  flang/test/Driver/asm-code-gen-x86.s
  flang/test/lit.cfg.py
  flang/tools/flang-driver/CMakeLists.txt
  flang/tools/flang-driver/driver.cpp
  flang/tools/flang-driver/fc1as_main.cpp

Index: flang/tools/flang-driver/fc1as_main.cpp
===
--- /dev/null
+++ flang/tools/flang-driver/fc1as_main.cpp
@@ -0,0 +1,672 @@
+//===-- fc1as_main.cpp - Flang Assembler  -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This is the entry point to the flang -fc1as functionality, which implements
+// the direct interface to the LLVM MC based assembler.
+//
+//===--===//
+
+#include "clang/Basic/Diagnostic.h"
+#include "clang/Basic/DiagnosticOptions.h"
+#include "clang/Driver/DriverDiagnostic.h"
+#include "clang/Driver/Options.h"
+#include "clang/Frontend/FrontendDiagnostic.h"
+#include "clang/Frontend/TextDiagnosticPrinter.h"
+#include "clang/Frontend/Utils.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCObjectFileInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCParser/MCAsmParser.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Option/Arg.h"
+#include "llvm/Option/ArgList.h"
+#include "llvm/Option/OptTable.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FileSystem.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/Path.h"
+#include "llvm/Support/Process.h"
+#include "llvm/Support/Signals.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/Timer.h"
+#include "llvm/Support/raw_ostream.h"
+#include 
+#include 
+#include 
+using namespace clang;
+using namespace clang::driver;
+using namespace clang::driver::options;
+using namespace llvm;
+using namespace llvm::opt;
+
+namespace {
+
+/// Helper class for representing a single invocation of the assembler.
+struct AssemblerInvocation {
+  /// @name Target Options
+  /// @{
+
+  /// The name of the target triple to assemble for.
+  std::string triple;
+
+  /// If given, the name of the target CPU to determine which instructions
+  /// are legal.
+  std::string cpu;
+
+  /// The list of target specific features to enable or disable -- this should
+  /// be a list of strings starting with '+' or '-'.
+  std::vector features;
+
+  /// The list of symbol definitions.
+  std::vector symbolDefs;
+
+  /// @}
+  /// @name Language Options
+  /// @{
+
+  std::vector includePaths;
+  unsigned noInitialTextSection : 1;
+  unsigned saveTemporaryLabels : 1;
+  unsigned genDwarfForAssembly : 1;
+  unsigned relaxElfRelocations : 1;
+  unsigned dwarf64 : 1;
+  unsigned dwarfVersion;
+  std::string dwarfDebugFlags;
+  std::string dwarfDebugProducer;
+  std::string debugCompilationDir;
+  std::map debugPrefixMap;
+  llvm::DebugCompressionType compressDebugSections =
+  llvm::DebugCompressionType::None;
+  std::string mainFileName;
+  std::string splitDwarfOutput;
+
+  /// @}
+  /// @name Frontend Options
+  /// @{
+
+  std::string inputFile;
+  std::vector llvmArgs;
+  std::string outputPath;
+  enum FileType {
+FT_Asm,  ///< Assembly (.s) output, transliterate mode.
+FT_Null, ///< No output, for timing purposes.
+FT_Obj   ///< Object file output.
+  };
+  FileType outputType;
+  unsigned showHelp : 1;
+  unsigned showVersion : 1;
+
+  /// @}
+  /// @name Transliterate Options
+  /// @{
+
+  unsigned outputAsmVariant;
+  unsigned showEncoding : 1;
+  unsigned showInst : 1;
+
+  /// @}
+  /// @name Assembler Options
+  /// @{
+
+  unsigned relaxAll : 1;
+  unsigned noExecStack : 1;
+  

[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

In D143478#4109412 , @clementval 
wrote:

> There should be some tests.

I'm not sure how to check the generated binaries, can you provide a test case 
for reference? Thanks!


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[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

In D143478#4109479 , @awarzynski 
wrote:

> Thanks for working on this! Before diving any deeper
>
> - Does LLVM Flang require `flang-new -fc1as`?
> - If yes, why can't Flang and Clang share it?
>
> For better visibility, I suggest raising these questions on Discourse 
> . As this could potentially affect both Flang 
> and Clang, could you post in one of the generic sections? Thanks!

Thanks! I opened a topic: 
https://discourse.llvm.org/t/rfc-flang-driver-try-to-support-flang-fc1as/68267


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[PATCH] D143478: [RFC][Flang][driver] Try to support `flang -fc1as`

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: rovka, kiranchandramohan, Leporacanthicus, 
awarzynski, sscalpone, liaolucy.
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Herald added a project: clang.

I'm trying to support `flang-new *.s`. Since I'm new to flang, I'm not sure if 
this is the right way to do it.


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Files:
  clang/include/clang/Driver/Options.h
  clang/include/clang/Driver/Options.td
  clang/include/clang/Driver/ToolChain.h
  clang/lib/Driver/ToolChain.cpp
  clang/lib/Driver/ToolChains/Flang.cpp
  clang/lib/Driver/ToolChains/Flang.h
  flang/tools/flang-driver/CMakeLists.txt
  flang/tools/flang-driver/driver.cpp
  flang/tools/flang-driver/fc1as_main.cpp

Index: flang/tools/flang-driver/fc1as_main.cpp
===
--- /dev/null
+++ flang/tools/flang-driver/fc1as_main.cpp
@@ -0,0 +1,672 @@
+//===-- fc1as_main.cpp - Flang Assembler  -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This is the entry point to the flang -fc1as functionality, which implements
+// the direct interface to the LLVM MC based assembler.
+//
+//===--===//
+
+#include "clang/Basic/Diagnostic.h"
+#include "clang/Basic/DiagnosticOptions.h"
+#include "clang/Driver/DriverDiagnostic.h"
+#include "clang/Driver/Options.h"
+#include "clang/Frontend/FrontendDiagnostic.h"
+#include "clang/Frontend/TextDiagnosticPrinter.h"
+#include "clang/Frontend/Utils.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCObjectFileInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCParser/MCAsmParser.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Option/Arg.h"
+#include "llvm/Option/ArgList.h"
+#include "llvm/Option/OptTable.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FileSystem.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/Path.h"
+#include "llvm/Support/Process.h"
+#include "llvm/Support/Signals.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/Timer.h"
+#include "llvm/Support/raw_ostream.h"
+#include 
+#include 
+#include 
+using namespace clang;
+using namespace clang::driver;
+using namespace clang::driver::options;
+using namespace llvm;
+using namespace llvm::opt;
+
+namespace {
+
+/// Helper class for representing a single invocation of the assembler.
+struct AssemblerInvocation {
+  /// @name Target Options
+  /// @{
+
+  /// The name of the target triple to assemble for.
+  std::string triple;
+
+  /// If given, the name of the target CPU to determine which instructions
+  /// are legal.
+  std::string cpu;
+
+  /// The list of target specific features to enable or disable -- this should
+  /// be a list of strings starting with '+' or '-'.
+  std::vector features;
+
+  /// The list of symbol definitions.
+  std::vector symbolDefs;
+
+  /// @}
+  /// @name Language Options
+  /// @{
+
+  std::vector includePaths;
+  unsigned noInitialTextSection : 1;
+  unsigned saveTemporaryLabels : 1;
+  unsigned genDwarfForAssembly : 1;
+  unsigned relaxElfRelocations : 1;
+  unsigned dwarf64 : 1;
+  unsigned dwarfVersion;
+  std::string dwarfDebugFlags;
+  std::string dwarfDebugProducer;
+  std::string debugCompilationDir;
+  std::map debugPrefixMap;
+  llvm::DebugCompressionType compressDebugSections =
+  llvm::DebugCompressionType::None;
+  std::string mainFileName;
+  std::string splitDwarfOutput;
+
+  /// @}
+  /// @name Frontend Options
+  /// @{
+
+  std::string inputFile;
+  std::vector llvmArgs;
+  std::string outputPath;
+  enum FileType {
+FT_Asm,  ///< Assembly (.s) output, transliterate mode.
+FT_Null, ///< No output, for timing purposes.
+FT_Obj   ///< Object file output.
+  };
+  FileType outputType;
+  unsigned showHelp : 1;
+  unsigned showVersion : 1;
+
+  /// @}
+  /// @name Transliterate Options
+  /// @{
+

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:599
+   Sched<[]>;
+def UKSTSA32 : RVPBinary<0b1110001, 0b011, "ukstsa32">,
+   Sched<[]>;

`0b011` should be `0b010`. 
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#847-ukstsa32-simd-32-bit-unsigned-saturating-straight-subtraction--addition


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[PATCH] D121670: [RISCV] Add zihintntl instructions

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7167a4207ee2: [RISCV] Add zihintntl instructions (authored 
by sunshaoce).

Repository:
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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/rv32zihintntl-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, gp
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: add zero, zero, tp
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, t0
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -8,6 +8,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
@@ -49,6 +50,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
@@ -91,6 +93,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -133,6 +136,7 @@
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasStdExtZihintpause = false;
+  bool HasStdExtZihintntl = false;
   bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
@@ -158,6 +159,7 @@
   bool hasStdExtC() const { return HasStdExtC; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
+  bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
   

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

In D95588#3641900 , @Jim wrote:

> In D95588#3622052 , @sunshaoce wrote:
>
>> Hello @Jim! We are developing the P extension, are you still maintaining 
>> this patch? Or would you mind co-development together?
>
> Yes, I am still on developing the P extension. But it seems spec has the 
> issue https://github.com/riscv/riscv-p-spec/issues/137 need to clarify.
> And some instruction (CLZ, FSR and FSRI) in Zbpbo only be aliased to B 
> extension on RV32. It is complicated if P extension are enabled on RV64.

Yes, this problem does exist. Thanks for your reply, looking forward to more 
cooperation!


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[PATCH] D128604: [RISCV] Support Zbpbo extension v0.9.11

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 443555.
sunshaoce added a comment.

Rebase


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck 

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.9.11

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 443552.
sunshaoce added a comment.

Rebase


Repository:
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Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -187,3 +187,15 @@
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32ip0p911"
+# CHECK: attribute  5, "rv32i2p0_p0p911_zbpbo0p911_zpn0p911_zpsfoperand0p911"
+
+.attribute arch, "rv32izbpbo0p911"
+# CHECK: attribute  5, "rv32i2p0_zbpbo0p911"
+
+.attribute arch, "rv32izpn0p911"
+# CHECK: attribute  5, "rv32i2p0_zpn0p911"
+
+.attribute arch, "rv32izpsfoperand0p911"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p911"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -109,6 +109,11 @@
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+
+{"p", RISCVExtensionVersion{0, 911}},
+{"zbpbo", RISCVExtensionVersion{0, 911}},
+{"zpn", RISCVExtensionVersion{0, 911}},
+{"zpsfoperand", RISCVExtensionVersion{0, 911}},
 };
 
 static bool stripExperimentalPrefix(StringRef ) {
@@ -598,8 +603,8 @@
 
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
-// Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+// Currently LLVM supports only "mafdcbpv".
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -773,6 +778,7 @@
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsP[] = {"zbpbo", "zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -787,6 +793,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
 {{"zfh"}, {ImpliedExtsZfh}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -42,6 +42,10 @@
 // CHECK-NOT: __riscv_zkr
 // CHECK-NOT: __riscv_zkt
 // CHECK-NOT: __riscv_zk
+// CHECK-NOT: __riscv_p
+// CHECK-NOT: __riscv_zbpbo
+// CHECK-NOT: __riscv_zpn
+// CHECK-NOT: __riscv_zpsfoperand
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 
@@ -224,6 +228,44 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 911000{{$}}
+// CHECK-P-EXT: __riscv_zbpbo 911000{{$}}
+// CHECK-P-EXT: __riscv_zpn 911000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// CHECK-ZBPBO-NOT: __riscv_p
+// CHECK-ZBPBO-EXT: __riscv_zbpbo 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu 

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441931.
sunshaoce added a comment.

Rebase on D99158 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo 

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.9.11

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441925.
sunshaoce added a comment.

Support for P extension version 0.9.11


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108189/new/

https://reviews.llvm.org/D108189

Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -187,3 +187,15 @@
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32ip0p911"
+# CHECK: attribute  5, "rv32i2p0_p0p911_zbpbo0p911_zpn0p911_zpsfoperand0p911"
+
+.attribute arch, "rv32izbpbo0p911"
+# CHECK: attribute  5, "rv32i2p0_zbpbo0p911"
+
+.attribute arch, "rv32izpn0p911"
+# CHECK: attribute  5, "rv32i2p0_zpn0p911"
+
+.attribute arch, "rv32izpsfoperand0p911"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p911"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -109,6 +109,11 @@
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+
+{"p", RISCVExtensionVersion{0, 911}},
+{"zbpbo", RISCVExtensionVersion{0, 911}},
+{"zpn", RISCVExtensionVersion{0, 911}},
+{"zpsfoperand", RISCVExtensionVersion{0, 911}},
 };
 
 static bool stripExperimentalPrefix(StringRef ) {
@@ -598,8 +603,8 @@
 
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
-// Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+// Currently LLVM supports only "mafdcbpv".
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -773,6 +778,7 @@
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsP[] = {"zbpbo", "zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -787,6 +793,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
 {{"zfh"}, {ImpliedExtsZfh}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -42,6 +42,10 @@
 // CHECK-NOT: __riscv_zkr
 // CHECK-NOT: __riscv_zkt
 // CHECK-NOT: __riscv_zk
+// CHECK-NOT: __riscv_p
+// CHECK-NOT: __riscv_zbpbo
+// CHECK-NOT: __riscv_zpn
+// CHECK-NOT: __riscv_zpsfoperand
 // CHECK-NOT: __riscv_zicbom
 // CHECK-NOT: __riscv_zicboz
 
@@ -224,6 +228,44 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 911000{{$}}
+// CHECK-P-EXT: __riscv_zbpbo 911000{{$}}
+// CHECK-P-EXT: __riscv_zpn 911000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izbpbo0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPBO-EXT %s
+// CHECK-ZBPBO-NOT: __riscv_p
+// CHECK-ZBPBO-EXT: __riscv_zbpbo 911000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p911 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 911000{{$}}
+
+// RUN: %clang -target 

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441872.
sunshaoce added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,26 

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added a comment.

Hello @Jim! We are developing the P extension, are you still maintaining this 
patch? Or would you mind co-development together?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

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[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 441052.
sunshaoce added a comment.

Add alias instructions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ 

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440714.
sunshaoce marked an inline comment as done.
sunshaoce added a comment.

Address @craig.topper's comment. Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440613.
sunshaoce added a comment.

Rebased on D128644 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s

[PATCH] D128604: [WIP][RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440324.
sunshaoce added a comment.
Herald added a subscriber: jdoerfert.

Fully supported Zbpbo v0.9.11


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo-intrinsics.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ 

[PATCH] D128604: [RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:352
 MinorStr = In.take_while(isDigit);
-In = In.substr(MajorStr.size() + 1);
+In = In.substr(MajorStr.size() + MinorStr.size() - 1);
 

Modifications here have been submitted separately in D128644.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D128604: [WIP][RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 440267.
sunshaoce added a comment.

Add more tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128604/new/

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+experimental-zbpbo \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r -M no-aliases --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump -d -r --mattr=+experimental-zbpbo - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
Index: llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc 

[PATCH] D128604: [WIP][RISCV] Support Zbpbo extension

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
sunshaoce added reviewers: asb, craig.topper, jrtc27, Jim, luismarques, 
kito-cheng, frasercrmck.
Herald added subscribers: VincentWu, luke957, StephenFan, vkmr, evandro, 
apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
sunshaoce requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128604

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv32-zbpbo.c
  clang/test/CodeGen/RISCV/rvp-intrinsics/riscv64-zbpbo.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rv32zbpbo.ll
  llvm/test/CodeGen/RISCV/rv64zbpbo.ll
  llvm/test/MC/RISCV/rv32zbpbo-valid.s
  llvm/test/MC/RISCV/rv64zbpbo-valid.s

Index: llvm/test/MC/RISCV/rv64zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zbpbo-valid.s
@@ -0,0 +1,35 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
+
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x6b]
+rev t0, t1
Index: llvm/test/MC/RISCV/rv32zbpbo-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zbpbo-valid.s
@@ -0,0 +1,43 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbpbo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbpbo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zbpbo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+pack t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: packu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48]
+packu t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
+
+# CHECK-ASM-AND-OBJ: fsri t0, t1, t2, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x3c]
+fsri t0, t1, t2, 0
+
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
+
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
+
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x69]
+rev t0, t1
Index: llvm/test/CodeGen/RISCV/rv64zbpbo.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbpbo.ll
@@ -0,0 +1,103 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbpbo -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBPBO
+
+define i64 @pack_i64(i64 %a, i64 %b) nounwind {
+; RV64I-LABEL: pack_i64:
+; RV64I:   # %bb.0:
+; RV64I-NEXT:slli a0, a0, 32
+; RV64I-NEXT:srli a0, a0, 32
+; RV64I-NEXT:slli a1, a1, 32
+; RV64I-NEXT:or a0, a1, a0
+; RV64I-NEXT:ret
+;
+; RV64ZBPBO-LABEL: pack_i64:
+; RV64ZBPBO:   # %bb.0:
+; RV64ZBPBO-NEXT:pack a0, a0, a1
+; RV64ZBPBO-NEXT:ret
+  %shl = and i64 %a, 4294967295
+  %shl1 = shl i64 %b, 32
+  %or = or i64 

[PATCH] D121670: [RISCV] Add zihintntl instructions

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 438563.
sunshaoce added a comment.
Herald added a subscriber: shiva0217.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121670/new/

https://reviews.llvm.org/D121670

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/rv32zihintntl-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, gp
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: add zero, zero, tp
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, t0
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
@@ -42,6 +43,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
@@ -79,6 +81,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -116,6 +119,7 @@
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasStdExtZihintpause = false;
+  bool HasStdExtZihintntl = false;
   bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
@@ -150,6 +151,7 @@
   bool hasStdExtC() const { return HasStdExtC; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
+  bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
   bool hasStdExtZba() const { return HasStdExtZba; }
   bool hasStdExtZbb() const { return 

[PATCH] D127589: [Driver][test] Make RISCV tests robust with PATH=

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe180cc5ff1a1: [Driver][test] Make RISCV tests robust with 
PATH= (authored by sunshaoce).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127589/new/

https://reviews.llvm.org/D127589

Files:
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 
-no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 \
@@ -60,7 +60,7 @@
 // CXX-RV64-BAREMETAL-LP64: "-lstdc++" "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -75,7 +75,7 @@
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "-lstdc++" "--start-group" "-lc" 
"-lgloss" "--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -mabi=lp64 \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -90,7 +90,7 @@
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64"
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64"
 
-// RUN: %clang -### %s -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -march=rv64imafd 
\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 -no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: 

[PATCH] D127684: [NFC] Use `https` instead of `http` in the `LLVM.org` URLs

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce abandoned this revision.
sunshaoce added a comment.

Thanks for comments!


Repository:
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[PATCH] D127684: [NFC] Use `https` instead of `http` in the urls

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https://reviews.llvm.org/D127684

Files:
  .github/PULL_REQUEST_TEMPLATE.md
  .github/workflows/repo-lockdown.yml
  .gitignore
  README.md
  bolt/docs/CMakeLists.txt
  bolt/docs/OptimizingClang.md
  bolt/docs/doxygen.cfg.in
  clang-tools-extra/.gitignore
  clang-tools-extra/README.txt
  clang-tools-extra/clang-doc/Representation.cpp
  clang-tools-extra/clang-doc/assets/clang-doc-default-stylesheet.css
  
clang-tools-extra/clang-include-fixer/find-all-symbols/tool/run-find-all-symbols.py
  clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.el
  clang-tools-extra/clang-include-fixer/tool/clang-include-fixer.py
  clang-tools-extra/clang-tidy/ClangTidy.cpp
  clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
  clang-tools-extra/clang-tidy/abseil/CleanupCtadCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationAdditionCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationComparisonCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationConversionCastCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationDivisionCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationFactoryFloatCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationFactoryScaleCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationSubtractionCheck.h
  clang-tools-extra/clang-tidy/abseil/DurationUnnecessaryConversionCheck.h
  clang-tools-extra/clang-tidy/abseil/FasterStrsplitDelimiterCheck.h
  clang-tools-extra/clang-tidy/abseil/NoInternalDependenciesCheck.h
  clang-tools-extra/clang-tidy/abseil/NoNamespaceCheck.h
  clang-tools-extra/clang-tidy/abseil/RedundantStrcatCallsCheck.h
  clang-tools-extra/clang-tidy/abseil/StrCatAppendCheck.h
  clang-tools-extra/clang-tidy/abseil/StringFindStrContainsCheck.h
  clang-tools-extra/clang-tidy/abseil/TimeComparisonCheck.h
  clang-tools-extra/clang-tidy/abseil/TimeSubtractionCheck.h
  clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h
  clang-tools-extra/clang-tidy/add_new_check.py
  clang-tools-extra/clang-tidy/altera/IdDependentBackwardBranchCheck.h
  clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.h
  clang-tools-extra/clang-tidy/altera/SingleWorkItemBarrierCheck.h
  clang-tools-extra/clang-tidy/altera/StructPackAlignCheck.h
  clang-tools-extra/clang-tidy/altera/UnrollLoopsCheck.h
  clang-tools-extra/clang-tidy/android/CloexecAccept4Check.h
  clang-tools-extra/clang-tidy/android/CloexecAcceptCheck.h
  clang-tools-extra/clang-tidy/android/CloexecCreatCheck.h
  

[PATCH] D127589: [RISCV] Compatible with more RISCV related ld in the test

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce updated this revision to Diff 436469.
sunshaoce added a comment.

Address @StephenFan's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127589/new/

https://reviews.llvm.org/D127589

Files:
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 
-no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 \
@@ -60,7 +60,7 @@
 // CXX-RV64-BAREMETAL-LP64: "-lstdc++" "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -75,7 +75,7 @@
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "-lstdc++" "--start-group" "-lc" 
"-lgloss" "--end-group" "-lgcc"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -mabi=lp64 \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -90,7 +90,7 @@
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64"
 // C-RV64-LINUX-MULTI-LP64: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64"
 
-// RUN: %clang -### %s -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv64-unknown-linux-gnu --rtlib=platform -march=rv64imafd 
\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
 // In the below tests, --rtlib=platform is used so that the driver ignores
 // the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 -no-pie \
@@ -30,7 +30,7 @@
 // C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform \
 // RUN:   --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
 // RUN:   --target=riscv64-unknown-elf 

[PATCH] D127589: [RISCV] Compatible with more RISCV related ld in the test

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce created this revision.
Herald added subscribers: VincentWu, luke957, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
sunshaoce requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

When `riscv64-unknown-linux-gnu-ld` is in the PATH, `clang -### -fuse-ld=ld 
--target=riscv64-unknown-linux-gnu` will use unknown-linux-gnu-ld first, which 
causes the error in the lit test.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127589

Files:
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -21,7 +21,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 
-no-pie \
 // RUN:   | FileCheck -check-prefix=C-RV64-BAREMETAL-LP64 %s
 
-// C-RV64-BAREMETAL-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// C-RV64-BAREMETAL-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // C-RV64-BAREMETAL-LP64: 
"--sysroot={{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf/lib{{/|}}crt0.o"
 // C-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
@@ -36,7 +36,7 @@
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV64-BAREMETAL-NOSYSROOT-LP64 %s
 
-// C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// C-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}riscv64-unknown-elf/lib{{/|}}crt0.o"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
 // C-RV64-BAREMETAL-NOSYSROOT-LP64: 
"-L{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1"
@@ -51,7 +51,7 @@
 // RUN:   | FileCheck -check-prefix=CXX-RV64-BAREMETAL-LP64 %s
 
 // CXX-RV64-BAREMETAL-LP64: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv64_tree/riscv64-unknown-elf/include/c++{{/|}}8.0.1"
-// CXX-RV64-BAREMETAL-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// CXX-RV64-BAREMETAL-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // CXX-RV64-BAREMETAL-LP64: 
"--sysroot={{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf/lib{{/|}}crt0.o"
 // CXX-RV64-BAREMETAL-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
@@ -67,7 +67,7 @@
 // RUN:   | FileCheck -check-prefix=CXX-RV64-BAREMETAL-NOSYSROOT-LP64 %s
 
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}riscv64-unknown-elf/include/c++{{/|}}8.0.1"
-// CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}bin{{/|}}riscv64-unknown-elf-ld"
+// CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "{{.*}}/riscv64-unknown-elf{{.*}}ld"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1/../../..{{/|}}..{{/|}}riscv64-unknown-elf/lib{{/|}}crt0.o"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtbegin.o"
 // CXX-RV64-BAREMETAL-NOSYSROOT-LP64: 
"-L{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1"
@@ -81,7 +81,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV64-LINUX-MULTI-LP64 %s
 
-// C-RV64-LINUX-MULTI-LP64: 
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../..{{/|}}..{{/|}}riscv64-unknown-linux-gnu/bin{{/|}}ld"
+// C-RV64-LINUX-MULTI-LP64: "{{.*}}/riscv64-unknown-linux-gnu{{.*}}ld"
 // C-RV64-LINUX-MULTI-LP64: 
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
 // C-RV64-LINUX-MULTI-LP64: "-m" "elf64lriscv"
 // C-RV64-LINUX-MULTI-LP64: "-dynamic-linker" "/lib/ld-linux-riscv64-lp64.so.1"
@@ -96,7 +96,7 @@
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 

[PATCH] D125157: [RISCV][NFC] Add more tests for clang driver.

[Shao-Ce SUN via Phabricator via cfe-commits]

sunshaoce added inline comments.



Comment at: clang/test/Driver/riscv-arch.c:583
+// RV32-ZHINX-BADVERS: unsupported version number 0.1 for extension 'zhinx'
\ No newline at end of file


Add a newline here.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D121670: [RISCV] Add zihintntl instructions

[Shao-Ce SUN via Phabricator via cfe-commits]

s updated this revision to Diff 415703.
s added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add preprocessor test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121670/new/

https://reviews.llvm.org/D121670

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/rv32zihintntl-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, gp
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: add zero, zero, tp
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: add zero, zero, t0
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s
@@ -42,6 +43,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s
@@ -79,6 +81,7 @@
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
+; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
@@ -116,6 +119,7 @@
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
+; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -66,6 +66,7 @@
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasStdExtZihintpause = false;
+  bool HasStdExtZihintntl = false;
   bool HasStdExtZba = false;
   bool HasStdExtZbb = false;
   bool HasStdExtZbc = false;
@@ -163,6 +164,7 @@
   bool hasStdExtC() const { return HasStdExtC; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
+  bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
   bool hasStdExtZba() const { return HasStdExtZba; }
   bool 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfa9c8bab0c7a: [RISCV] Support k-ext clang intrinsics 
(authored by achieveartificialintelligence).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 412698.
achieveartificialintelligence marked 7 inline comments as done.
achieveartificialintelligence added a comment.

Address @craig.topper's comments. Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0e38b295435b: [RISCV] add the MC layer support of Zfinx 
extension (authored by achieveartificialintelligence).
Herald added a project: All.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411959.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

Address @craig.topper's comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Are there any other errors now? @krasimir @nikic


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411734.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

Address @jrtc27's comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411719.
achieveartificialintelligence added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Can you help test if this patch works fine now? @krasimir


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

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[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411676.
achieveartificialintelligence added a comment.

Fix typo


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411675.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

Thanks for @craig.topper's detailed advice!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411379.
achieveartificialintelligence added a comment.

Ping & Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 411375.
achieveartificialintelligence added a comment.

Thanks for @craig.topper's patch!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/zfinx-types.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5

[PATCH] D117740: [NFC][clang] Simplify `isOneOf` function

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa8b4b9104c8f: [NFC][clang] Simplify `isOneOf` function 
(authored by achieveartificialintelligence).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117740/new/

https://reviews.llvm.org/D117740

Files:
  clang/include/clang/Lex/Token.h


Index: clang/include/clang/Lex/Token.h
===
--- clang/include/clang/Lex/Token.h
+++ clang/include/clang/Lex/Token.h
@@ -99,9 +99,8 @@
   bool isOneOf(tok::TokenKind K1, tok::TokenKind K2) const {
 return is(K1) || is(K2);
   }
-  template 
-  bool isOneOf(tok::TokenKind K1, tok::TokenKind K2, Ts... Ks) const {
-return is(K1) || isOneOf(K2, Ks...);
+  template  bool isOneOf(tok::TokenKind K1, Ts... Ks) const {
+return is(K1) || isOneOf(Ks...);
   }
 
   /// Return true if this is a raw identifier (when lexing


Index: clang/include/clang/Lex/Token.h
===
--- clang/include/clang/Lex/Token.h
+++ clang/include/clang/Lex/Token.h
@@ -99,9 +99,8 @@
   bool isOneOf(tok::TokenKind K1, tok::TokenKind K2) const {
 return is(K1) || is(K2);
   }
-  template 
-  bool isOneOf(tok::TokenKind K1, tok::TokenKind K2, Ts... Ks) const {
-return is(K1) || isOneOf(K2, Ks...);
+  template  bool isOneOf(tok::TokenKind K1, Ts... Ks) const {
+return is(K1) || isOneOf(Ks...);
   }
 
   /// Return true if this is a raw identifier (when lexing
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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D93298#3342452 , @krasimir wrote:

> @achieveartificialintelligence any progress with the problematic IR? Have you 
> been able to reproduce using nikic's reduced example?

Sorry, I don't have a solution right now.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D117740: [NFC][clang] Simplify `isOneOf` function

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

Ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 410444.
achieveartificialintelligence added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

@krasimir Since I don't have a rust environment, can you help me to test if 
D120130  works?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

Thanks all!


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
achieveartificialintelligence marked an inline comment as done.
Closed by commit rG7798ecca9c3d: [RISCV] add the MC layer support of Zfinx 
extension (authored by achieveartificialintelligence).

Changed prior to commit:
  https://reviews.llvm.org/D93298?vs=407482=409617#toc

Repository:
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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6

[PATCH] D119846: [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D119846#3325334 , @skan wrote:

> @achieveartificialintelligence  Please explain why a patch is reverted in the 
> commit message next time.

OK, thanks for your guidance!


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[PATCH] D119846: [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

[Shao-Ce SUN via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfe25c06cc5bd: [NFC][MC] remove unused argument 
`MCRegisterInfo` in `MCCodeEmitter` (authored by achieveartificialintelligence).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  bolt/include/bolt/Core/BinaryContext.h
  bolt/lib/Core/BinaryContext.cpp
  clang/tools/driver/cc1as_main.cpp
  llvm/include/llvm/MC/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/DWARFLinker/DWARFStreamer.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/LlvmState.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-ml/llvm-ml.cpp
  llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/MC/DwarfLineTableHeaders.cpp
  mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp

Index: mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
===
--- mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
+++ mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
@@ -377,7 +377,7 @@
   std::unique_ptr mcStreamer;
   std::unique_ptr mcii(target->createMCInstrInfo());
 
-  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, *mri, ctx);
+  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, ctx);
   llvm::MCAsmBackend *mab = target->createMCAsmBackend(*sti, *mri, mcOptions);
   mcStreamer.reset(target->createMCObjectStreamer(
   triple, ctx, std::unique_ptr(mab),
Index: llvm/unittests/MC/DwarfLineTableHeaders.cpp
===
--- llvm/unittests/MC/DwarfLineTableHeaders.cpp
+++ llvm/unittests/MC/DwarfLineTableHeaders.cpp
@@ -77,8 +77,7 @@
 Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
 Res.MII.reset(TheTarget->createMCInstrInfo());
-MCCodeEmitter *MCE =
-TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
 MCAsmBackend *MAB =
 TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
 std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
+++ llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
@@ -464,7 +464,7 @@
   TLOF->Initialize(*MC, *TM);
   MC->setObjectFileInfo(TLOF);
 
-  MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
+  MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
   if (!MCE)
 return make_error("no code emitter for target " + TripleName,
inconvertibleErrorCode());
Index: llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
+++ llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
@@ -106,7 +106,7 @@
   Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
   Res.MII.reset(TheTarget->createMCInstrInfo());
-  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
   MCAsmBackend *MAB =
   TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
   std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/tools/llvm-ml/llvm-ml.cpp
===
--- llvm/tools/llvm-ml/llvm-ml.cpp
+++ llvm/tools/llvm-ml/llvm-ml.cpp
@@ -377,7 +377,7 @@
 // Set up the AsmStreamer.
 std::unique_ptr CE;
 if (InputArgs.hasArg(OPT_show_encoding))
-  CE.reset(TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
+  CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
 
 std::unique_ptr MAB(
 TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
@@ -395,7 +395,7 @@
   OS = BOS.get();
 }
 
-MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
+MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
 Str.reset(TheTarget->createMCObjectStreamer(
 TheTriple, Ctx, std::unique_ptr(MAB),
Index: llvm/tools/llvm-mca/llvm-mca.cpp

[PATCH] D119846: [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: grosbach, Eugene.Zelenko, asb, 
jrtc27, craig.topper.
Herald added subscribers: ayermolo, sdasgup3, wenzhicui, wrengr, Chia-hungDuan, 
dcaballe, cota, teijeong, frasercrmck, rdzhabarov, tatianashp, msifontes, 
jurahul, Kayjukh, grosul1, Joonsoo, liufengdb, aartbik, mgester, arpith-jacob, 
csigg, antiagainst, shauheen, rriddle, mehdi_amini, luismarques, apazos, 
sameer.abuasal, pengfei, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, gbedwell, niosHD, sabuasal, 
simoncook, johnrusso, rbar, hiraditya.
Herald added a reviewer: andreadb.
Herald added a reviewer: bondhugula.
Herald added a reviewer: rafauler.
Herald added a reviewer: Amir.
Herald added a reviewer: maksfb.
achieveartificialintelligence requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, yota9, 
stephenneuendorffer, nicolasvasilache, MaskRay.
Herald added a reviewer: herhut.
Herald added projects: clang, MLIR, LLVM.

For ten years, it seems that `MCRegisterInfo` is not used by any target.


Repository:
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https://reviews.llvm.org/D119846

Files:
  bolt/include/bolt/Core/BinaryContext.h
  bolt/lib/Core/BinaryContext.cpp
  clang/tools/driver/cc1as_main.cpp
  llvm/include/llvm/MC/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/DWARFLinker/DWARFStreamer.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/LlvmState.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-ml/llvm-ml.cpp
  llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/MC/DwarfLineTableHeaders.cpp
  mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp

Index: mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
===
--- mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
+++ mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
@@ -376,7 +376,7 @@
   std::unique_ptr mcStreamer;
   std::unique_ptr mcii(target->createMCInstrInfo());
 
-  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, *mri, ctx);
+  llvm::MCCodeEmitter *ce = target->createMCCodeEmitter(*mcii, ctx);
   llvm::MCAsmBackend *mab = target->createMCAsmBackend(*sti, *mri, mcOptions);
   mcStreamer.reset(target->createMCObjectStreamer(
   triple, ctx, std::unique_ptr(mab),
Index: llvm/unittests/MC/DwarfLineTableHeaders.cpp
===
--- llvm/unittests/MC/DwarfLineTableHeaders.cpp
+++ llvm/unittests/MC/DwarfLineTableHeaders.cpp
@@ -77,8 +77,7 @@
 Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
 Res.MII.reset(TheTarget->createMCInstrInfo());
-MCCodeEmitter *MCE =
-TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
 MCAsmBackend *MAB =
 TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
 std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
+++ llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
@@ -464,7 +464,7 @@
   TLOF->Initialize(*MC, *TM);
   MC->setObjectFileInfo(TLOF);
 
-  MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
+  MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
   if (!MCE)
 return make_error("no code emitter for target " + TripleName,
inconvertibleErrorCode());
Index: llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
===
--- llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
+++ llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
@@ -106,7 +106,7 @@
   Res.Ctx->setObjectFileInfo(Res.MOFI.get());
 
   Res.MII.reset(TheTarget->createMCInstrInfo());
-  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *MRI, *Res.Ctx);
+  MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
   MCAsmBackend *MAB =
   TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
   std::unique_ptr OW = MAB->createObjectWriter(OS);
Index: llvm/tools/llvm-ml/llvm-ml.cpp
===
--- 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 408319.
achieveartificialintelligence marked 4 inline comments as done.
achieveartificialintelligence added a comment.

Address @craig.topper's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 408310.
achieveartificialintelligence added a comment.

Ping & Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557
+
+let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add

Jim wrote:
> Is register pair only on RV32 for used as f64?
Yes.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+X10_PD, X12_PD, X14_PD, X16_PD,

craig.topper wrote:
> Jim wrote:
> > Is XLenRI correct for GPRPF64? RV32 has size 32.
> I'm not sure the RegInfos are correct for the other classes either. The 
> RegInfos override the register size, the spill size, and spill alignment. I 
> think those should all be based on the FP type.
> 
> So I don't think any of these should have a RegInfos.
Without `RegInfo`, it would cause `spill size` to be changed for a large number 
of other tests.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 407482.
achieveartificialintelligence marked 2 inline comments as done.
achieveartificialintelligence added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 405997.
achieveartificialintelligence added a comment.

Amend tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,17 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zkt
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +354,58 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkt1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKT-EXT %s
+// CHECK-ZKT-EXT: __riscv_zkt
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,47 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: 

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 405989.
achieveartificialintelligence marked 3 inline comments as done.
achieveartificialintelligence added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,16 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +353,53 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,15 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: "-target-feature" "+zbkc"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkx1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added a comment.

In D93298#3296515 , @luismarques wrote:

> Assuming this will be merged soon, do you want to submit a backport request 
> for the 14.0 branch?

Yes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

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[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 405605.
achieveartificialintelligence added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112774/new/

https://reviews.llvm.org/D112774

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
  clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -31,6 +31,16 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_zbkc
+// CHECK-NOT: __riscv_zbkx
+// CHECK-NOT: __riscv_zbkb
+// CHECK-NOT: __riscv_zkne
+// CHECK-NOT: __riscv_zknd
+// CHECK-NOT: __riscv_zknh
+// CHECK-NOT: __riscv_zksh
+// CHECK-NOT: __riscv_zksed
+// CHECK-NOT: __riscv_zkr
+// CHECK-NOT: __riscv_zk
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -343,3 +353,53 @@
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 100{{$}}
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkc1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKC-EXT %s
+// CHECK-ZBKC-EXT: __riscv_zbkc
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkx1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKX-EXT %s
+// CHECK-ZBKX-EXT: __riscv_zbkx
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izbkb1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZBKB-EXT %s
+// CHECK-ZBKB-EXT: __riscv_zbkb
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknd1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKND-EXT %s
+// CHECK-ZKND-EXT: __riscv_zknd
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkne1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNE-EXT %s
+// CHECK-ZKNE-EXT: __riscv_zkne
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izknh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKNH-EXT %s
+// CHECK-ZKNH-EXT: __riscv_zknh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksh1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSH-EXT %s
+// CHECK-ZKSH-EXT: __riscv_zksh
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izksed1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKSED-EXT %s
+// CHECK-ZKSED-EXT: __riscv_zksed
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izkr1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZKR-EXT %s
+// CHECK-ZKR-EXT: __riscv_zkr
+
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izk1p0 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZK-EXT %s
+// CHECK-ZK-EXT: __riscv_zk
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -414,3 +414,15 @@
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv1p0_zvl32b1p0 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-GOODVERS %s
 // RV32-ZVL-GOODVERS: "-target-feature" "+zvl32b"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkc1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKC %s
+// RV32-ZBKC: "-target-feature" "+zbkc"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izbkx1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBKX %s
+// RV32-ZBKX: 

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence updated this revision to Diff 404910.
achieveartificialintelligence added a comment.

Separate the Zhinxmin and Zhinx extensions. Inspired by D118581 



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5

[PATCH] D117740: [NFC][clang] Simplify `isOneOf` function

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achieveartificialintelligence added a comment.

Ping


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[PATCH] D118578: [RISCV] Make Zfhmin in march imply F.

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achieveartificialintelligence accepted this revision.
achieveartificialintelligence added a comment.
This revision is now accepted and ready to land.

LGTM. I think this is indeed a better way to implement `Zfhmin`.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 402739.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.

@asb Thank you very much! Could you please take a look at what needs to be 
modified now?


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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn

[PATCH] D113237: [RISCV] Support I extension version 2.1

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achieveartificialintelligence added a comment.

> @achieveartificialintelligence Do you know what is the relation between your 
> patch and D115921 ?

This commit doesn't depend on D115921 , but 
if D115921  is merged, it's a good idea to 
build on it.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence updated this revision to Diff 401528.
achieveartificialintelligence added a comment.

Address @craig.topper's comments. Thanks!


Repository:
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Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32i-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-invalid.s
  llvm/test/MC/RISCV/rv32zdinx-valid.s
  llvm/test/MC/RISCV/rv32zfinx-invalid.s
  llvm/test/MC/RISCV/rv32zfinx-valid.s
  llvm/test/MC/RISCV/rv32zhinx-invalid.s
  llvm/test/MC/RISCV/rv32zhinx-valid.s
  llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv32zhinxmin-valid.s
  llvm/test/MC/RISCV/rv64zdinx-invalid.s
  llvm/test/MC/RISCV/rv64zdinx-valid.s
  llvm/test/MC/RISCV/rv64zfinx-invalid.s
  llvm/test/MC/RISCV/rv64zfinx-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinx-valid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-valid.s
  llvm/test/MC/RISCV/rvzdinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzfinx-aliases-valid.s
  llvm/test/MC/RISCV/rvzhinx-aliases-valid.s

Index: llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvzhinx-aliases-valid.s
@@ -0,0 +1,82 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx -riscv-no-aliases \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zhinx \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx -M no-aliases - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zhinx %s \
+# RUN: | llvm-objdump -d --mattr=+zhinx - \
+# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
+
+##===--===##
+## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
+##===--===##
+
+# CHECK-INST: fsgnjx.h s1, s2, s2
+# CHECK-ALIAS: fabs.h s1, s2
+fabs.h s1, s2
+# CHECK-INST: fsgnjn.h s2, s3, s3
+# CHECK-ALIAS: fneg.h s2, s3
+fneg.h s2, s3
+
+# CHECK-INST: flt.h tp, s6, s5
+# CHECK-ALIAS: flt.h tp, s6, s5
+fgt.h x4, s5, s6
+# CHECK-INST: fle.h t2, s1, s0
+# CHECK-ALIAS: fle.h t2, s1, s0
+fge.h x7, x8, x9
+
+##===--===##
+## Aliases which omit the rounding mode.
+##===--===##
+
+# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn
+# CHECK-ALIAS: fmadd.h a0, a1, a2, a3
+fmadd.h x10, x11, x12, x13
+# CHECK-INST: fmsub.h a4, a5, a6, a7, dyn
+# CHECK-ALIAS: fmsub.h a4, a5, a6, a7
+fmsub.h x14, x15, x16, x17
+# CHECK-INST: fnmsub.h s2, s3, s4, s5, dyn
+# CHECK-ALIAS: fnmsub.h s2, s3, s4, s5
+fnmsub.h x18, x19, x20, x21
+# CHECK-INST: fnmadd.h s6, s7, s8, s9, dyn
+# CHECK-ALIAS: fnmadd.h s6, s7, s8, s9
+fnmadd.h x22, x23, x24, x25
+# CHECK-INST: fadd.h s10, s11, t3, dyn
+# CHECK-ALIAS: fadd.h s10, s11, t3
+fadd.h x26, x27, x28
+# CHECK-INST: fsub.h t4, t5, t6, dyn
+# CHECK-ALIAS: fsub.h t4, t5, t6
+fsub.h x29, x30, x31
+# CHECK-INST: fmul.h s0, s1, s2, dyn
+# CHECK-ALIAS: fmul.h s0, s1, s2
+fmul.h s0, s1, s2
+# CHECK-INST: fdiv.h s3, s4, s5, dyn
+# CHECK-ALIAS: fdiv.h s3, s4, s5
+fdiv.h s3, s4, s5
+# CHECK-INST: fsqrt.h s6, s7, dyn
+# CHECK-ALIAS: fsqrt.h s6, s7
+fsqrt.h s6, s7
+# CHECK-INST: fcvt.w.h a0, s5, dyn
+# CHECK-ALIAS: fcvt.w.h a0, s5
+fcvt.w.h a0, s5
+# CHECK-INST: fcvt.wu.h a1, s6, dyn
+# CHECK-ALIAS: fcvt.wu.h a1, s6
+fcvt.wu.h a1, s6
+# CHECK-INST: fcvt.h.w t6, a4, dyn
+# CHECK-ALIAS: fcvt.h.w t6, a4
+fcvt.h.w t6, a4
+# CHECK-INST: fcvt.h.wu s0, a5, dyn
+# CHECK-ALIAS: fcvt.h.wu s0, a5
+fcvt.h.wu s0, a5
Index: llvm/test/MC/RISCV/rvzfinx-aliases-valid.s

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

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achieveartificialintelligence added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \
 ; RUN: -verify-machineinstrs < %s | FileCheck %s

Do we need `+f` here?


Repository:
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  https://reviews.llvm.org/D112408/new/

https://reviews.llvm.org/D112408

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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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achieveartificialintelligence added a comment.

Ping. Any other suggestions?


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[PATCH] D117740: [NFC][clang] Simplify `isOneOf` function

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achieveartificialintelligence created this revision.
achieveartificialintelligence added reviewers: alexfh, danielmarjamaki.
achieveartificialintelligence requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117740

Files:
  clang/include/clang/Lex/Token.h


Index: clang/include/clang/Lex/Token.h
===
--- clang/include/clang/Lex/Token.h
+++ clang/include/clang/Lex/Token.h
@@ -99,9 +99,8 @@
   bool isOneOf(tok::TokenKind K1, tok::TokenKind K2) const {
 return is(K1) || is(K2);
   }
-  template 
-  bool isOneOf(tok::TokenKind K1, tok::TokenKind K2, Ts... Ks) const {
-return is(K1) || isOneOf(K2, Ks...);
+  template  bool isOneOf(tok::TokenKind K1, Ts... Ks) const {
+return is(K1) || isOneOf(Ks...);
   }
 
   /// Return true if this is a raw identifier (when lexing


Index: clang/include/clang/Lex/Token.h
===
--- clang/include/clang/Lex/Token.h
+++ clang/include/clang/Lex/Token.h
@@ -99,9 +99,8 @@
   bool isOneOf(tok::TokenKind K1, tok::TokenKind K2) const {
 return is(K1) || is(K2);
   }
-  template 
-  bool isOneOf(tok::TokenKind K1, tok::TokenKind K2, Ts... Ks) const {
-return is(K1) || isOneOf(K2, Ks...);
+  template  bool isOneOf(tok::TokenKind K1, Ts... Ks) const {
+return is(K1) || isOneOf(Ks...);
   }
 
   /// Return true if this is a raw identifier (when lexing
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