[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce closed https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSscofpmf, +FeatureStdExtSstc, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, +FeatureStdExtZmmul, sunshaoce wrote: Addressed. Thanks! https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/8] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+FeatureStdExtI,
+FeatureStdExtM,
+
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSscofpmf, +FeatureStdExtSstc, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, +FeatureStdExtZmmul, sunshaoce wrote: Generated `"-target-feature" "-zmmul"` in `clang/test/Driver/riscv-cpus.c`. It seems that M imply Zmmul is not supported yet. https://github.com/llvm/llvm-project/pull/95070 https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+ NoSchedModel,
+ !listconcat(RVA22S64Features,
sunshaoce wrote:
This modification seems to cause the wrong information generated by
`build/include/llvm/TargetParser/RISCVTargetParserDef.inc`.
```c++
PROC(SIFIVE_X280, {"sifive-x280"},
{"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zifencei2p0_zfh1p0_zba1p0_zbb1p0_zvfh1p0_zvl512b1p0"},
0)
PROC(SPACEMIT_X60, {"spacemit-x60"},
{"rv0v1p0_zicond1p0_zmmul1p0_zfh1p0_zbc1p0_zbkc1p0_zvfh1p0_zvkt1p0_zvl256b1p0_sscofpmf1p0_sstc1p0_svnapot1p0"},
0)
PROC(SYNTACORE_SCR1_BASE, {"syntacore-scr1-base"},
{"rv32i2p1_c2p0_zicsr2p0_zifencei2p0"}, 0)
```
https://github.com/llvm/llvm-project/pull/94564
___
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[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
sunshaoce wrote: > Could you explain these numbers? It looks like data in some columns is > missing. I only ran the default `base metrics` once. The geometric mean of this `Estimated Base Ratio` column can be regarded as the comprehensive score for this item. [Q14. What is the difference between a "base" metric and a "peak" metric?](https://www.spec.org/cpu2006/docs/readme1st.html#Q14) https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
sunshaoce wrote: I've tested this patch with `spec 2006 int`. Everything seems to be running smoothly: ``` Estimated Estimated Base Base BasePeak Peak Peak Benchmarks Ref. Run Time Ratio Ref. Run Time Ratio -- -- - --- - - 400.perlbench9770 1899 5.14 * 401.bzip29650 3284 2.94 * 403.gcc 8050 1990 4.05 * 429.mcf 9120 5440 1.68 * 445.gobmk 10490 1805 5.81 * 456.hmmer9330 2585 3.61 * 458.sjeng 12100 2180 5.55 * 462.libquantum 20720990 20.9 * 464.h264ref 22130 3376 6.56 * 471.omnetpp 6250 3084 2.03 * 473.astar7020 2613 2.69 * 483.xalancbmk6900 1873 3.68 * ``` @preames Could we merge this patch? https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,21 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSscofpmf, +FeatureStdExtSstc, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, +FeatureStdExtZmmul, +FeatureStdExtZvfh, +FeatureStdExtZvfhmin, sunshaoce wrote: Addressed. Thanks! https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/7] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+FeatureStdExtI,
+FeatureStdExtM,
+
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
sunshaoce wrote: Added: - Sscofpmf - Sstc - Zvkt - TuneDLenFactor2 Removed: - Zvl32b - Zvl64b - Zvl128b https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/6] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+FeatureStdExtI,
+FeatureStdExtM,
+
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", + NoSchedModel, + !listconcat(RVA22S64Features, + [FeatureStdExtV, +FeatureStdExtSvnapot, +FeatureStdExtZbc, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZicond, sunshaoce wrote: Updated the description. https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
sunshaoce wrote: All done. Thanks! Is there anything else that needs to be modified? https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/5] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+FeatureStdExtI,
+FeatureStdExtM,
+
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/4] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+FeatureStdExtI,
+FeatureStdExtM,
+
[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
https://github.com/sunshaoce edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)
@@ -381,3 +381,14 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1", + NoSchedModel, sunshaoce wrote: Addressed. Thanks! https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/3] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+FeatureStdExtI,
+FeatureStdExtM,
+
[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion, TuneShiftedZExtWFusion]>; + +def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1", + NoSchedModel, + [Feature64Bit, +FeatureStdExtI, +FeatureStdExtM, +FeatureStdExtA, +FeatureStdExtF, +FeatureStdExtD, +FeatureStdExtC, +FeatureStdExtV, +FeatureStdExtZba, +FeatureStdExtZbb, +FeatureStdExtZbc, +FeatureStdExtZbs, +FeatureStdExtZbkb, +FeatureStdExtZbkc, +FeatureStdExtZfh, +FeatureStdExtZfhmin, +FeatureStdExtZicond, +FeatureStdExtZicsr, +FeatureStdExtZifencei, +FeatureStdExtZmmul, +FeatureStdExtZvfh, +FeatureStdExtZvfhmin, +FeatureStdExtZvl32b, +FeatureStdExtZvl64b, +FeatureStdExtZvl128b, +FeatureStdExtZvl256b]>; sunshaoce wrote: Addressed. Thanks! https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/94564
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+ NoSchedModel,
+ [Feature64Bit,
+FeatureStdExtI,
+FeatureStdExtM,
+
[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)
https://github.com/sunshaoce edited https://github.com/llvm/llvm-project/pull/94564 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)
https://github.com/sunshaoce created
https://github.com/llvm/llvm-project/pull/94564
Spacemit-k1 is a new 8-core CPU that supports RVV 1.0, and it is now integrated
into the BPi-F3 development board.
Through [ruapo](https://github.com/nihui/ruapu) detection, this is the march
information of Spacemit-K1:
```
i
m
a
f
d
c
v
zba
zbb
zbc
zbs
zbkb
zbkc
zfh
zfhmin
zicond
zicsr
zifencei
zmmul
zvfh
zvfhmin
zvl32b
zvl64b
zvl128b
zvl256b
```
BPi-F3 Datasheet: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet
Spacemit-K1 Datasheet:
https://developer.spacemit.com/#/documentation?token=DBd4wvqoqi2fiqkiERTcbEDknBh
>From 363e29385277c049bc91a86e76ff6f6ae70ceaa9 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Thu, 6 Jun 2024 12:05:33 +0800
Subject: [PATCH] [RISCV] Add processor definition for Spacemit-K1
---
clang/test/Driver/riscv-cpus.c| 12 ++
clang/test/Misc/target-invalid-cpu-note.c | 4 ++--
llvm/lib/Target/RISCV/RISCVProcessors.td | 29 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba3..32d7910ab4daa 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,18 @@
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature"
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-k1 | FileCheck
-check-prefix=MCPU-SPACEMIT-K1 %s
+// MCPU-SPACEMIT-K1: "-nostdsysteminc" "-target-cpu" "spacemit-k1"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+m" "-target-feature" "+a"
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+c" "-target-feature" "+v"
"-target-feature" "+zicond" "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zifencei" "-target-feature"
"+zmmul" "-target-feature" "+zfh"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zfhmin" "-target-feature" "+zba"
"-target-feature" "+zbb" "-target-feature" "+zbc"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zbkb" "-target-feature" "+zbkc"
"-target-feature" "+zbs" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zve32x" "-target-feature"
"+zve64d" "-target-feature" "+zve64f" "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvfh" "-target-feature"
"+zvfhmin"
+// MCPU-SPACEMIT-K1-SAME: "-target-feature" "+zvl128b" "-target-feature"
"+zvl256b" "-target-feature" "+zvl32b" "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-K1-SAME: "-target-abi" "lp64d"
+
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..04e92360fe665 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76,
sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu,
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64,
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54,
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-k1, veyron-v1,
xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..08602e9d06cc9 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -0,0 +1,142 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S -emit-llvm
-o - %s | FileCheck %s
+
+__attribute__((target_clones("default", "arch=rv64im"))) int foo1(void) {
+ return 1;
+}
+__attribute__((target_clones("default", "arch=+zbb"))) int foo2(void) { return
2; }
+__attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) {
return 3; }
+__attribute__((target_clones("default", "arch=rv64ima", "arch=+zbb,+v"))) int
+foo4(void) {
+ return 4;
+}
+__attribute__((target_clones("default"))) int foo5(void) { return 5; }
+
+int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
+
+//.
+// CHECK: @__riscv_hwprobe_args = internal global [2 x %riscv_hwprobe_pair]
[%riscv_hwprobe_pair { i64 3, i64 1 }, %riscv_hwprobe_pair { i64 4, i64 0 }]
+// CHECK: @__riscv_hwprobe_args.1 = internal global [2 x
%riscv_hwprobe_pair.0] [%riscv_hwprobe_pair.0 { i64 3, i64 1 },
%riscv_hwprobe_pair.0 { i64 4, i64 16 }]
+// CHECK: @__riscv_hwprobe_args.2 = internal global [2 x
%riscv_hwprobe_pair.1] [%riscv_hwprobe_pair.1 { i64 3, i64 1 },
%riscv_hwprobe_pair.1 { i64 4, i64 18 }]
+// CHECK: @__riscv_hwprobe_args.3 = internal global [2 x
%riscv_hwprobe_pair.2] [%riscv_hwprobe_pair.2 { i64 3, i64 1 },
%riscv_hwprobe_pair.2 { i64 4, i64 0 }]
+// CHECK: @__riscv_hwprobe_args.4 = internal global [2 x
%riscv_hwprobe_pair.3] [%riscv_hwprobe_pair.3 { i64 3, i64 1 },
%riscv_hwprobe_pair.3 { i64 4, i64 20 }]
+// CHECK: @foo1.ifunc = weak_odr alias i32 (), ptr @foo1
+// CHECK: @foo2.ifunc = weak_odr alias i32 (), ptr @foo2
+// CHECK: @foo3.ifunc = weak_odr alias i32 (), ptr @foo3
+// CHECK: @foo4.ifunc = weak_odr alias i32 (), ptr @foo4
+// CHECK: @foo5.ifunc = weak_odr alias i32 (), ptr @foo5
+// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
+// CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver
+// CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver
+// CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver
+// CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver
+//.
+// CHECK-LABEL: define dso_local signext i32 @foo1.default(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:ret i32 1
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr
@__riscv_hwprobe_args, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_return:
+// CHECK-NEXT:ret ptr @"foo1.arch=rv64im"
+// CHECK: resolver_else:
+// CHECK-NEXT:ret ptr @foo1.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo2.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:ret i32 2
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr
@__riscv_hwprobe_args.1, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_return:
+// CHECK-NEXT:ret ptr @"foo2.arch=+zbb"
+// CHECK: resolver_else:
+// CHECK-NEXT:ret ptr @foo2.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo3.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:ret i32 3
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr
@__riscv_hwprobe_args.2, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_return:
+// CHECK-NEXT:ret ptr @"foo3.arch=+zbb,+c"
+// CHECK: resolver_else:
+// CHECK-NEXT:ret ptr @foo3.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo4.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:ret i32 4
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr
@__riscv_hwprobe_args.3, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label
[[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_return:
+// CHECK-NEXT:ret ptr @"foo4.arch=rv64ima"
+// CHECK: resolver_else:
+// CHECK-NEXT:[[TMP1:%.*]] = call i1 @__riscv_ifunc_select(ptr
@__riscv_hwprobe_args.4, i32 2)
+// CHECK-NEXT:br i1 [[TMP1]], label [[RESOLVER_RETURN1:%.*]], label
[[RESOLVER_ELSE2:%.*]]
+// CHECK: resolver_return1:
+// CHECK-NEXT:ret ptr @"foo4.arch=+zbb,+v"
+// CHECK: resolver_else2:
+// CHECK-NEXT:ret ptr @foo4.default
+//
+//
+// CHECK-LABEL: define
[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)
sunshaoce wrote: > > > By the way, is there any plan to support `CFLUSH.I.L1` in the future? > > > > > > Flushing the instruction cache doesn't make sense given it can never be > > dirty. Invalidating/discarding does, but that's just what fence.i is doing? > > A cflush.i.l1 did appear in some SiFive manual at some point, but I don't > think any hardware implements it. Understood, thank you for the reply! https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)
sunshaoce wrote: By the way, is there any plan to support `CFLUSH.I.L1` in the future? https://github.com/llvm/llvm-project/pull/83896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
sunshaoce wrote:
I tried compiling it and then got two warnings.
```
llvm-project/clang/lib/CodeGen/CGDebugInfo.cpp:1408:11: warning: enumeration
value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
1408 | switch (CC) {
| ^~
1 warning generated.
[3629/3776] Building CXX object
tools/clang/tools/libclang/CMakeFiles/libclang.dir/CXType.cpp.o
llvm-project/clang/tools/libclang/CXType.cpp:662:13: warning: enumeration value
'CC_RISCVVectorCall' not handled in switch [-Wswitch]
662 | switch (FD->getCallConv()) {
| ^
1 warning generated.
```
https://github.com/llvm/llvm-project/pull/77560
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/sunshaoce closed https://github.com/llvm/llvm-project/pull/71140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/71140
>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/6] [RISCV][Clang] Add bf16-type vector support for RVV
---
clang/include/clang/AST/Type.h| 4 +--
clang/include/clang/Basic/RISCVVTypes.def | 35 +++
.../clang/Basic/riscv_vector_common.td| 1 +
.../clang/Support/RISCVVIntrinsicUtils.h | 11 +++---
clang/lib/AST/ASTContext.cpp | 12 +--
clang/lib/AST/Type.cpp| 7 ++--
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 3 ++
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 25 +
.../rvv-intrinsic-datatypes.cpp | 13 +++
clang/test/Sema/riscv-types.c | 19 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 8 +++--
11 files changed, 117 insertions(+), 21 deletions(-)
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index f64cd5e0ef64910..f99c4faa7170527 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -7294,7 +7294,7 @@ inline bool Type::isRVVType() const {
inline bool Type::isRVVType(unsigned ElementCount) const {
bool Ret = false;
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (NumEls == ElementCount)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
@@ -7305,7 +7305,7 @@ inline bool Type::isRVVType(unsigned Bitwidth, bool
IsFloat) const {
bool Ret = false;
#define RVV_TYPE(Name, Id, SingletonId)
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (ElBits == Bitwidth && IsFloat == IsFP)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index 575bca58b51e023..af44cdcd53e5bd0 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -12,7 +12,8 @@
// A builtin type that has not been covered by any other #define
// Defining this macro covers all the builtins.
//
-// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP)
+// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP,
+// IsBF)
// A RISC-V V scalable vector.
//
// - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
@@ -45,7 +46,8 @@
#endif
#ifndef RVV_VECTOR_TYPE
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
IsFP)\
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
+IsFP, IsBF)
\
RVV_TYPE(Name, Id, SingletonId)
#endif
@@ -55,13 +57,20 @@
#endif
#ifndef RVV_VECTOR_TYPE_INT
-#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
IsSigned) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
\
+IsSigned)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false,
\
+ false)
#endif
#ifndef RVV_VECTOR_TYPE_FLOAT
-#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true,
false)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_BFLOAT
+#define RVV_VECTOR_TYPE_BFLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, false,
true)
#endif
//===- Vector types
---===//
@@ -125,6 +134,19 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2,
RvvFloat16m2Ty, 8, 16,
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16,
16, 1)
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32,
16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4_t", RvvBFloat16mf4, RvvBFloat16mf4Ty,
+ 1, 16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2_t", RvvBFloat16mf2, RvvBFloat16mf2Ty,
+ 2,
[llvm] [clang] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/71140
>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/5] [RISCV][Clang] Add bf16-type vector support for RVV
---
clang/include/clang/AST/Type.h| 4 +--
clang/include/clang/Basic/RISCVVTypes.def | 35 +++
.../clang/Basic/riscv_vector_common.td| 1 +
.../clang/Support/RISCVVIntrinsicUtils.h | 11 +++---
clang/lib/AST/ASTContext.cpp | 12 +--
clang/lib/AST/Type.cpp| 7 ++--
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 3 ++
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 25 +
.../rvv-intrinsic-datatypes.cpp | 13 +++
clang/test/Sema/riscv-types.c | 19 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 8 +++--
11 files changed, 117 insertions(+), 21 deletions(-)
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index f64cd5e0ef64910..f99c4faa7170527 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -7294,7 +7294,7 @@ inline bool Type::isRVVType() const {
inline bool Type::isRVVType(unsigned ElementCount) const {
bool Ret = false;
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (NumEls == ElementCount)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
@@ -7305,7 +7305,7 @@ inline bool Type::isRVVType(unsigned Bitwidth, bool
IsFloat) const {
bool Ret = false;
#define RVV_TYPE(Name, Id, SingletonId)
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (ElBits == Bitwidth && IsFloat == IsFP)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index 575bca58b51e023..af44cdcd53e5bd0 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -12,7 +12,8 @@
// A builtin type that has not been covered by any other #define
// Defining this macro covers all the builtins.
//
-// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP)
+// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP,
+// IsBF)
// A RISC-V V scalable vector.
//
// - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
@@ -45,7 +46,8 @@
#endif
#ifndef RVV_VECTOR_TYPE
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
IsFP)\
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
+IsFP, IsBF)
\
RVV_TYPE(Name, Id, SingletonId)
#endif
@@ -55,13 +57,20 @@
#endif
#ifndef RVV_VECTOR_TYPE_INT
-#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
IsSigned) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
\
+IsSigned)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false,
\
+ false)
#endif
#ifndef RVV_VECTOR_TYPE_FLOAT
-#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true,
false)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_BFLOAT
+#define RVV_VECTOR_TYPE_BFLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, false,
true)
#endif
//===- Vector types
---===//
@@ -125,6 +134,19 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2,
RvvFloat16m2Ty, 8, 16,
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16,
16, 1)
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32,
16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4_t", RvvBFloat16mf4, RvvBFloat16mf4Ty,
+ 1, 16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2_t", RvvBFloat16mf2, RvvBFloat16mf2Ty,
+ 2,
[llvm] [clang] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
@@ -6046,6 +6046,13 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
!TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin"))
Diag(Loc, diag::err_riscv_type_requires_extension, D)
<< Ty << "zvfh or zvfhmin";
+ // Check if enabled zfbfmin/zvfbfmin for BFloat16
+ if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ false,
+/* IsBFloat */ true) &&
+ !TI.hasFeature("experimental-zfbfmin") &&
sunshaoce wrote:
Removed. Thanks!
https://github.com/llvm/llvm-project/pull/71140
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/71140
>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/4] [RISCV][Clang] Add bf16-type vector support for RVV
---
clang/include/clang/AST/Type.h| 4 +--
clang/include/clang/Basic/RISCVVTypes.def | 35 +++
.../clang/Basic/riscv_vector_common.td| 1 +
.../clang/Support/RISCVVIntrinsicUtils.h | 11 +++---
clang/lib/AST/ASTContext.cpp | 12 +--
clang/lib/AST/Type.cpp| 7 ++--
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 3 ++
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 25 +
.../rvv-intrinsic-datatypes.cpp | 13 +++
clang/test/Sema/riscv-types.c | 19 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 8 +++--
11 files changed, 117 insertions(+), 21 deletions(-)
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index f64cd5e0ef64910..f99c4faa7170527 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -7294,7 +7294,7 @@ inline bool Type::isRVVType() const {
inline bool Type::isRVVType(unsigned ElementCount) const {
bool Ret = false;
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (NumEls == ElementCount)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
@@ -7305,7 +7305,7 @@ inline bool Type::isRVVType(unsigned Bitwidth, bool
IsFloat) const {
bool Ret = false;
#define RVV_TYPE(Name, Id, SingletonId)
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (ElBits == Bitwidth && IsFloat == IsFP)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index 575bca58b51e023..af44cdcd53e5bd0 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -12,7 +12,8 @@
// A builtin type that has not been covered by any other #define
// Defining this macro covers all the builtins.
//
-// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP)
+// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP,
+// IsBF)
// A RISC-V V scalable vector.
//
// - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
@@ -45,7 +46,8 @@
#endif
#ifndef RVV_VECTOR_TYPE
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
IsFP)\
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
+IsFP, IsBF)
\
RVV_TYPE(Name, Id, SingletonId)
#endif
@@ -55,13 +57,20 @@
#endif
#ifndef RVV_VECTOR_TYPE_INT
-#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
IsSigned) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
\
+IsSigned)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false,
\
+ false)
#endif
#ifndef RVV_VECTOR_TYPE_FLOAT
-#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true,
false)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_BFLOAT
+#define RVV_VECTOR_TYPE_BFLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, false,
true)
#endif
//===- Vector types
---===//
@@ -125,6 +134,19 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2,
RvvFloat16m2Ty, 8, 16,
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16,
16, 1)
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32,
16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4_t", RvvBFloat16mf4, RvvBFloat16mf4Ty,
+ 1, 16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2_t", RvvBFloat16mf2, RvvBFloat16mf2Ty,
+ 2,
[llvm] [clang] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
sunshaoce wrote: > I believe we need to update `Sema::checkRVVTypeSupport` too Addressed. https://github.com/llvm/llvm-project/pull/71140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/71140
>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/3] [RISCV][Clang] Add bf16-type vector support for RVV
---
clang/include/clang/AST/Type.h| 4 +--
clang/include/clang/Basic/RISCVVTypes.def | 35 +++
.../clang/Basic/riscv_vector_common.td| 1 +
.../clang/Support/RISCVVIntrinsicUtils.h | 11 +++---
clang/lib/AST/ASTContext.cpp | 12 +--
clang/lib/AST/Type.cpp| 7 ++--
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 3 ++
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 25 +
.../rvv-intrinsic-datatypes.cpp | 13 +++
clang/test/Sema/riscv-types.c | 19 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 8 +++--
11 files changed, 117 insertions(+), 21 deletions(-)
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index f64cd5e0ef64910..f99c4faa7170527 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -7294,7 +7294,7 @@ inline bool Type::isRVVType() const {
inline bool Type::isRVVType(unsigned ElementCount) const {
bool Ret = false;
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (NumEls == ElementCount)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
@@ -7305,7 +7305,7 @@ inline bool Type::isRVVType(unsigned Bitwidth, bool
IsFloat) const {
bool Ret = false;
#define RVV_TYPE(Name, Id, SingletonId)
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (ElBits == Bitwidth && IsFloat == IsFP)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index 575bca58b51e023..af44cdcd53e5bd0 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -12,7 +12,8 @@
// A builtin type that has not been covered by any other #define
// Defining this macro covers all the builtins.
//
-// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP)
+// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP,
+// IsBF)
// A RISC-V V scalable vector.
//
// - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
@@ -45,7 +46,8 @@
#endif
#ifndef RVV_VECTOR_TYPE
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
IsFP)\
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
+IsFP, IsBF)
\
RVV_TYPE(Name, Id, SingletonId)
#endif
@@ -55,13 +57,20 @@
#endif
#ifndef RVV_VECTOR_TYPE_INT
-#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
IsSigned) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
\
+IsSigned)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false,
\
+ false)
#endif
#ifndef RVV_VECTOR_TYPE_FLOAT
-#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true,
false)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_BFLOAT
+#define RVV_VECTOR_TYPE_BFLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, false,
true)
#endif
//===- Vector types
---===//
@@ -125,6 +134,19 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2,
RvvFloat16m2Ty, 8, 16,
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16,
16, 1)
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32,
16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf4_t", RvvBFloat16mf4, RvvBFloat16mf4Ty,
+ 1, 16, 1)
+RVV_VECTOR_TYPE_BFLOAT("__rvv_bfloat16mf2_t", RvvBFloat16mf2, RvvBFloat16mf2Ty,
+ 2,
[llvm] [clang] [RISCV] Introduce and use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/sunshaoce edited https://github.com/llvm/llvm-project/pull/71140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Use BF16 in Xsfvfwmaccqqq intrinsics (PR #71140)
https://github.com/sunshaoce created
https://github.com/llvm/llvm-project/pull/71140
BF16 implementation based on @joshua-arch1's https://reviews.llvm.org/D152498
Fixed the incorrect f16 type introduced in
https://github.com/llvm/llvm-project/pull/68296
-
Co-authored-by: Jun Sha (Joshua)
>From d8d0fcdd00b422e48af733ef638fe9857a05686e Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Fri, 3 Nov 2023 11:50:58 +0800
Subject: [PATCH 1/2] [RISCV][Clang] Add bf16-type vector support for RVV
---
clang/include/clang/AST/Type.h| 4 +--
clang/include/clang/Basic/RISCVVTypes.def | 35 +++
.../clang/Basic/riscv_vector_common.td| 1 +
.../clang/Support/RISCVVIntrinsicUtils.h | 11 +++---
clang/lib/AST/ASTContext.cpp | 12 +--
clang/lib/AST/Type.cpp| 7 ++--
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 3 ++
clang/lib/Support/RISCVVIntrinsicUtils.cpp| 25 +
.../rvv-intrinsic-datatypes.cpp | 13 +++
clang/test/Sema/riscv-types.c | 19 ++
clang/utils/TableGen/RISCVVEmitter.cpp| 8 +++--
11 files changed, 117 insertions(+), 21 deletions(-)
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index f64cd5e0ef64910..f99c4faa7170527 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -7294,7 +7294,7 @@ inline bool Type::isRVVType() const {
inline bool Type::isRVVType(unsigned ElementCount) const {
bool Ret = false;
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (NumEls == ElementCount)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
@@ -7305,7 +7305,7 @@ inline bool Type::isRVVType(unsigned Bitwidth, bool
IsFloat) const {
bool Ret = false;
#define RVV_TYPE(Name, Id, SingletonId)
#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
-IsFP)
\
+IsFP, IsBF)
\
if (ElBits == Bitwidth && IsFloat == IsFP)
\
Ret |= isSpecificBuiltinType(BuiltinType::Id);
#include "clang/Basic/RISCVVTypes.def"
diff --git a/clang/include/clang/Basic/RISCVVTypes.def
b/clang/include/clang/Basic/RISCVVTypes.def
index 575bca58b51e023..af44cdcd53e5bd0 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -12,7 +12,8 @@
// A builtin type that has not been covered by any other #define
// Defining this macro covers all the builtins.
//
-// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP)
+// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP,
+// IsBF)
// A RISC-V V scalable vector.
//
// - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
@@ -45,7 +46,8 @@
#endif
#ifndef RVV_VECTOR_TYPE
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
IsFP)\
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,
\
+IsFP, IsBF)
\
RVV_TYPE(Name, Id, SingletonId)
#endif
@@ -55,13 +57,20 @@
#endif
#ifndef RVV_VECTOR_TYPE_INT
-#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
IsSigned) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF,
\
+IsSigned)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false,
\
+ false)
#endif
#ifndef RVV_VECTOR_TYPE_FLOAT
-#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
- RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true,
false)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_BFLOAT
+#define RVV_VECTOR_TYPE_BFLOAT(Name, Id, SingletonId, NumEls, ElBits, NF)
\
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, false,
true)
#endif
//===- Vector types
---===//
@@ -125,6 +134,19 @@ RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2,
RvvFloat16m2Ty, 8, 16,
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16,
16, 1)
RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32,
16, 1)
[clang] [llvm] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)
@@ -813,6 +813,14 @@ def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">, AssemblerPredicate<(all_of FeatureVendorXSfcie), "'XSfcie' (SiFive Custom Instruction Extension SCIE.)">; +def FeatureVendorXSfvfwmaccqqq +: SubtargetFeature<"xsfvfwmaccqqq", "HasVendorXSfvfwmaccqqq", "true", + "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))", + [FeatureStdExtZve32x]>; sunshaoce wrote: and `zvfbfmin` https://github.com/llvm/llvm-project/pull/68296 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Support Xsfvfwmaccqqq extensions (PR #68296)
@@ -103,3 +103,15 @@ let SupportOverloading = false in {
defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3],
UseGPR=0>;
}
}
+
+multiclass RVVVFWMACCBuiltinSet> suffixes_prototypes> {
+ let OverloadedName = NAME,
+ Name = NAME,
+ HasMasked = false,
+ Log2LMUL = [-2, -1, 0, 1, 2] in
+defm NAME : RVVOutOp1Op2BuiltinSet;
sunshaoce wrote:
> The SiFive custom vector extension Xsfvfwmaccqqq introduces the Bfloat16
> matrix multiply accumulate instruction.
This is wrong! It should be `bfloat16` instead of `float16`. Need to be based
on: https://reviews.llvm.org/D152498
https://github.com/llvm/llvm-project/pull/68296
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[clang] [llvm] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)
@@ -0,0 +1,307 @@ +//==- RISCVSchedXiangShanNanHu.td - XiangShan-NanHu Scheduling Definitions --*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===-===// + +//===-===// + +// XiangShan is a high-performance open-source RISC-V processor developed by +// the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences. sunshaoce wrote: I think this should be a more formal name: `the Institute of Computing Technology (ICT), Chinese Academy of Sciences` https://github.com/llvm/llvm-project/pull/70232 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)
sunshaoce wrote: LGTM. If no one else has any objections, I think we can merge it. https://github.com/llvm/llvm-project/pull/68295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)
@@ -178,6 +178,19 @@ multiclass CustomSiFiveVCIX;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr>
+: RVInstVCCustom2 {
+ let vm = 1;
+ let funct6_lo2 = funct6{1-0};
+}
+}
+
+multiclass CustomSiFiveVMACC funct6, RISCVVFormat opv, string
opcodestr> {
+ def _VV : CustomSiFiveVMACC;
sunshaoce wrote:
I still think `4x8x4` or similar can be used instead of `VV`, but using `VV`
can indeed avoid adding new multiclass.
https://github.com/llvm/llvm-project/pull/68295
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[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)
sunshaoce wrote: `clang/test/Preprocessor/riscv-target-features.c` need to be modified. https://github.com/llvm/llvm-project/pull/68295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)
@@ -103,3 +103,27 @@ let SupportOverloading = false in {
defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3],
UseGPR=0>;
}
}
+
+multiclass RVVVQMACCBuiltinSet> suffixes_prototypes> {
+ let OverloadedName = NAME,
+ Name = NAME,
+ HasMasked = false,
+ Log2LMUL = [0, 1, 2, 3] in
+defm NAME : RVVOutOp1Op2BuiltinSet;
+}
+
+let UnMaskedPolicyScheme = HasPolicyOperand in
+ let RequiredFeatures = ["Xsfvqmaccdod"] in {
+defm sf_vqmaccu_2x8x2 : RVVVQMACCBuiltinSet<[["", "4", "44SUvUv"]]>;
+defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "4", "44Svv"]]>;
sunshaoce wrote:
`<"sf_vqmacc_2x8x2", "i", [["2x8x2", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>`
This way of writing can void using `"4"`.
https://github.com/llvm/llvm-project/pull/68295
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[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)
@@ -178,6 +178,19 @@ multiclass CustomSiFiveVCIX;
}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr>
+: RVInstVCCustom2 {
+ let vm = 1;
+ let funct6_lo2 = funct6{1-0};
+}
+}
+
+multiclass CustomSiFiveVMACC funct6, RISCVVFormat opv, string
opcodestr> {
+ def _VV : CustomSiFiveVMACC;
sunshaoce wrote:
I am confused about why we need to add the suffix `_VV`. Why not just use `""`
instead?
https://github.com/llvm/llvm-project/pull/68295
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[clang] [RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (PR #68295)
@@ -0,0 +1,57 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \ +# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN:| FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \ +# RUN:| llvm-objdump -d --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod - \ +# RUN:| FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \ +# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sf.vqmaccu.2x8x2 v8, v4, v20 sunshaoce wrote: I don't understand something, why aren't there any with `v0.t`? https://github.com/llvm/llvm-project/pull/68295 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support Xsfvfnrclipxfqf extensions (PR #68297)
@@ -630,7 +630,7 @@ TEST(getTargetFeatureForExtension,
RetrieveTargetFeatureFromOneExt) {
TEST(RiscvExtensionsHelp, CheckExtensions) {
std::string ExpectedOutput =
-R"(All available -march extensions for RISC-V
+ R"(All available -march extensions for RISC-V
sunshaoce wrote:
How about using `clang-format off`here?
https://github.com/llvm/llvm-project/pull/68297
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[clang] [llvm][tblgen] Add `Source Filename` for `emitSourceFileHeader` (PR #65744)
" + sys::path::filename(Record.getInputFilename())," In-Reply-To: https://github.com/sunshaoce closed https://github.com/llvm/llvm-project/pull/65744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm][tblgen] Add `Source Filename` for `emitSourceFileHeader` (PR #65744)
" + sys::path::filename(Record.getInputFilename()),"
In-Reply-To:
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/65744
>From 8fd7007fa437a0eefb66015861f76f65095c31bc Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sat, 23 Sep 2023 11:38:33 +0800
Subject: [PATCH 1/3] [llvm][tblgen] Add `SourcePath` for
`emitSourceFileHeader`
---
llvm/include/llvm/TableGen/TableGenBackend.h | 3 ++-
llvm/lib/TableGen/TableGenBackend.cpp| 7 ++-
llvm/utils/TableGen/VTEmitter.cpp| 3 ++-
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/TableGen/TableGenBackend.h
b/llvm/include/llvm/TableGen/TableGenBackend.h
index 39f1e14bc950841..7bbd163b0433aca 100644
--- a/llvm/include/llvm/TableGen/TableGenBackend.h
+++ b/llvm/include/llvm/TableGen/TableGenBackend.h
@@ -50,7 +50,8 @@ template class OptClass : Opt {
/// emitSourceFileHeader - Output an LLVM style file header to the specified
/// raw_ostream.
-void emitSourceFileHeader(StringRef Desc, raw_ostream );
+void emitSourceFileHeader(StringRef Desc, raw_ostream ,
+ StringRef SourcePath = "");
} // End llvm namespace
diff --git a/llvm/lib/TableGen/TableGenBackend.cpp
b/llvm/lib/TableGen/TableGenBackend.cpp
index 705c3a17a765750..164443a347dcc53 100644
--- a/llvm/lib/TableGen/TableGenBackend.cpp
+++ b/llvm/lib/TableGen/TableGenBackend.cpp
@@ -40,7 +40,8 @@ static void printLine(raw_ostream , const Twine ,
char Fill,
OS << Suffix << '\n';
}
-void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream ) {
+void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream ,
+StringRef SourcePath) {
printLine(OS, "/*===- TableGen'erated file ", '-', "*- C++ -*-===*\\");
StringRef Prefix("|* ");
StringRef Suffix(" *|");
@@ -59,4 +60,8 @@ void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream
) {
printLine(OS, Prefix, ' ', Suffix);
printLine(OS, "\\*===", '-', "===*/");
OS << '\n';
+
+ // Print the path of source file
+ if (!SourcePath.empty())
+OS << "// Generated from: " << SourcePath << "\n\n";
}
diff --git a/llvm/utils/TableGen/VTEmitter.cpp
b/llvm/utils/TableGen/VTEmitter.cpp
index d398a7e7b58f40a..03fa3d64b41fe6c 100644
--- a/llvm/utils/TableGen/VTEmitter.cpp
+++ b/llvm/utils/TableGen/VTEmitter.cpp
@@ -30,7 +30,8 @@ class VTEmitter {
} // End anonymous namespace.
void VTEmitter::run(raw_ostream ) {
- emitSourceFileHeader("ValueTypes Source Fragment", OS);
+ emitSourceFileHeader("ValueTypes Source Fragment", OS,
+ Records.getInputFilename());
std::array VTsByNumber = {};
auto ValueTypes = Records.getAllDerivedDefinitions("ValueType");
>From 0d138680a7d663b8373834223cc6665dc9e3a6ba Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sun, 24 Sep 2023 00:52:02 +0800
Subject: [PATCH 2/3] add more tests
---
clang/utils/TableGen/ClangASTNodesEmitter.cpp | 4 +-
.../TableGen/ClangASTPropertiesEmitter.cpp| 8 ++--
clang/utils/TableGen/ClangAttrEmitter.cpp | 48 +++
.../ClangCommentCommandInfoEmitter.cpp| 10 ++--
...mentHTMLNamedCharacterReferenceEmitter.cpp | 5 +-
.../TableGen/ClangCommentHTMLTagsEmitter.cpp | 4 +-
.../TableGen/ClangOpenCLBuiltinEmitter.cpp| 6 +--
clang/utils/TableGen/ClangSyntaxEmitter.cpp | 4 +-
.../utils/TableGen/ClangTypeNodesEmitter.cpp | 2 +-
lldb/utils/TableGen/LLDBOptionDefEmitter.cpp | 2 +-
.../utils/TableGen/LLDBPropertyDefEmitter.cpp | 4 +-
llvm/include/llvm/TableGen/TableGenBackend.h | 3 +-
llvm/lib/TableGen/TableGenBackend.cpp | 6 +--
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +-
llvm/utils/TableGen/AsmWriterEmitter.cpp | 2 +-
llvm/utils/TableGen/VTEmitter.cpp | 3 +-
mlir/tools/mlir-tblgen/DialectGen.cpp | 4 +-
mlir/tools/mlir-tblgen/EnumsGen.cpp | 4 +-
mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp | 2 +-
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 4 +-
mlir/tools/mlir-tblgen/RewriterGen.cpp| 2 +-
mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 22 +
22 files changed, 81 insertions(+), 70 deletions(-)
diff --git a/clang/utils/TableGen/ClangASTNodesEmitter.cpp
b/clang/utils/TableGen/ClangASTNodesEmitter.cpp
index 2b8d7a9efdf10c9..16a1c74b9d91ad6 100644
--- a/clang/utils/TableGen/ClangASTNodesEmitter.cpp
+++ b/clang/utils/TableGen/ClangASTNodesEmitter.cpp
@@ -169,7 +169,7 @@ void ClangASTNodesEmitter::deriveChildTree() {
void ClangASTNodesEmitter::run(raw_ostream ) {
deriveChildTree();
- emitSourceFileHeader("List of AST nodes of a particular kind", OS);
+ emitSourceFileHeader("List of AST nodes of a particular kind", OS, Records);
// Write the preamble
OS << "#ifndef ABSTRACT_" << macroHierarchyName() << "\n";
@@ -205,7 +205,7 @@ void clang::EmitClangASTNodes(RecordKeeper , raw_ostream
,
void clang::EmitClangDeclContext(RecordKeeper , raw_ostream ) {
// FIXME:
[clang] [llvm][tblgen] Add `Source Filename` for `emitSourceFileHeader` (PR #65744)
" + sys::path::filename(Record.getInputFilename())," In-Reply-To: https://github.com/sunshaoce edited https://github.com/llvm/llvm-project/pull/65744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm][tblgen] Add `SourcePath` for `emitSourceFileHeader` (PR #65744)
" + sys::path::filename(Record.getInputFilename())," In-Reply-To: sunshaoce wrote: Addressed. Thanks! Now it is ``` /*===- TableGen'erated file -*- C++ -*-===*\ |**| |* ValueTypes Source Fragment *| |**| |* Automatically generated file, do not edit! *| |* From: ValueTypes.td*| |**| \*===--===*/ ``` https://github.com/llvm/llvm-project/pull/65744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm][tblgen] Add `SourcePath` for `emitSourceFileHeader` (PR #65744)
" + sys::path::filename(Record.getInputFilename()),"
In-Reply-To:
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/65744
>From 23d0b738bf40ea44e159f4f8d7355d4d6bc0688d Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sat, 23 Sep 2023 11:38:33 +0800
Subject: [PATCH 1/3] [llvm][tblgen] Add `SourcePath` for
`emitSourceFileHeader`
---
llvm/include/llvm/TableGen/TableGenBackend.h | 3 ++-
llvm/lib/TableGen/TableGenBackend.cpp| 7 ++-
llvm/utils/TableGen/VTEmitter.cpp| 3 ++-
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/TableGen/TableGenBackend.h
b/llvm/include/llvm/TableGen/TableGenBackend.h
index 39f1e14bc950841..7bbd163b0433aca 100644
--- a/llvm/include/llvm/TableGen/TableGenBackend.h
+++ b/llvm/include/llvm/TableGen/TableGenBackend.h
@@ -50,7 +50,8 @@ template class OptClass : Opt {
/// emitSourceFileHeader - Output an LLVM style file header to the specified
/// raw_ostream.
-void emitSourceFileHeader(StringRef Desc, raw_ostream );
+void emitSourceFileHeader(StringRef Desc, raw_ostream ,
+ StringRef SourcePath = "");
} // End llvm namespace
diff --git a/llvm/lib/TableGen/TableGenBackend.cpp
b/llvm/lib/TableGen/TableGenBackend.cpp
index 135ec643bc3a7df..a50df8dbdcfb220 100644
--- a/llvm/lib/TableGen/TableGenBackend.cpp
+++ b/llvm/lib/TableGen/TableGenBackend.cpp
@@ -40,7 +40,8 @@ static void printLine(raw_ostream , const Twine ,
char Fill,
OS << Suffix << '\n';
}
-void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream ) {
+void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream ,
+StringRef SourcePath) {
printLine(OS, "/*===- TableGen'erated file ", '-', "*- C++ -*-===*\\");
StringRef Prefix("|* ");
StringRef Suffix(" *|");
@@ -59,4 +60,8 @@ void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream
) {
printLine(OS, Prefix, ' ', Suffix);
printLine(OS, "\\*===", '-', "===*/");
OS << '\n';
+
+ // Print the path of source file
+ if (!SourcePath.empty())
+OS << "// Generated from: " << SourcePath << "\n\n";
}
diff --git a/llvm/utils/TableGen/VTEmitter.cpp
b/llvm/utils/TableGen/VTEmitter.cpp
index d398a7e7b58f40a..03fa3d64b41fe6c 100644
--- a/llvm/utils/TableGen/VTEmitter.cpp
+++ b/llvm/utils/TableGen/VTEmitter.cpp
@@ -30,7 +30,8 @@ class VTEmitter {
} // End anonymous namespace.
void VTEmitter::run(raw_ostream ) {
- emitSourceFileHeader("ValueTypes Source Fragment", OS);
+ emitSourceFileHeader("ValueTypes Source Fragment", OS,
+ Records.getInputFilename());
std::array VTsByNumber = {};
auto ValueTypes = Records.getAllDerivedDefinitions("ValueType");
>From d07486764071679c8cbcd5e7c4905eb41b4770b3 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sun, 24 Sep 2023 00:52:02 +0800
Subject: [PATCH 2/3] add more tests
---
clang/utils/TableGen/ClangASTNodesEmitter.cpp | 4 +-
.../TableGen/ClangASTPropertiesEmitter.cpp| 8 ++--
clang/utils/TableGen/ClangAttrEmitter.cpp | 47 +++
.../ClangCommentCommandInfoEmitter.cpp| 8 ++--
...mentHTMLNamedCharacterReferenceEmitter.cpp | 4 +-
.../TableGen/ClangCommentHTMLTagsEmitter.cpp | 5 +-
.../TableGen/ClangOpenCLBuiltinEmitter.cpp| 6 +--
clang/utils/TableGen/ClangSyntaxEmitter.cpp | 4 +-
.../utils/TableGen/ClangTypeNodesEmitter.cpp | 2 +-
lldb/utils/TableGen/LLDBOptionDefEmitter.cpp | 2 +-
.../utils/TableGen/LLDBPropertyDefEmitter.cpp | 4 +-
llvm/include/llvm/TableGen/TableGenBackend.h | 3 +-
llvm/lib/TableGen/TableGenBackend.cpp | 6 +--
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +-
llvm/utils/TableGen/AsmWriterEmitter.cpp | 2 +-
llvm/utils/TableGen/VTEmitter.cpp | 3 +-
mlir/tools/mlir-tblgen/DialectGen.cpp | 4 +-
mlir/tools/mlir-tblgen/EnumsGen.cpp | 4 +-
mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp | 2 +-
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 4 +-
mlir/tools/mlir-tblgen/RewriterGen.cpp| 2 +-
mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 22 +
22 files changed, 81 insertions(+), 67 deletions(-)
diff --git a/clang/utils/TableGen/ClangASTNodesEmitter.cpp
b/clang/utils/TableGen/ClangASTNodesEmitter.cpp
index 2b8d7a9efdf10c9..16a1c74b9d91ad6 100644
--- a/clang/utils/TableGen/ClangASTNodesEmitter.cpp
+++ b/clang/utils/TableGen/ClangASTNodesEmitter.cpp
@@ -169,7 +169,7 @@ void ClangASTNodesEmitter::deriveChildTree() {
void ClangASTNodesEmitter::run(raw_ostream ) {
deriveChildTree();
- emitSourceFileHeader("List of AST nodes of a particular kind", OS);
+ emitSourceFileHeader("List of AST nodes of a particular kind", OS, Records);
// Write the preamble
OS << "#ifndef ABSTRACT_" << macroHierarchyName() << "\n";
@@ -205,7 +205,7 @@ void clang::EmitClangASTNodes(RecordKeeper , raw_ostream
,
void clang::EmitClangDeclContext(RecordKeeper , raw_ostream ) {
// FIXME:
[clang] [llvm][tblgen] Add `SourcePath` for `emitSourceFileHeader` (PR #65744)
sunshaoce wrote: I am not sure how to keep only the `llvm-project//Filename` path except by hard-coding. Or how to keep only the base file name? This could limit it to within 80 characters. https://github.com/llvm/llvm-project/pull/65744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm][tblgen] Add `SourcePath` for `emitSourceFileHeader` (PR #65744)
sunshaoce wrote:
> ⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️
>
> You can test this locally with the following command:
> ```shell
> git-clang-format --diff b8b4ee6b450766796b162b4811a6b3f723d07268
> d07486764071679c8cbcd5e7c4905eb41b4770b3 --
> clang/utils/TableGen/ClangASTNodesEmitter.cpp
> clang/utils/TableGen/ClangASTPropertiesEmitter.cpp
> clang/utils/TableGen/ClangAttrEmitter.cpp
> clang/utils/TableGen/ClangCommentCommandInfoEmitter.cpp
> clang/utils/TableGen/ClangCommentHTMLNamedCharacterReferenceEmitter.cpp
> clang/utils/TableGen/ClangCommentHTMLTagsEmitter.cpp
> clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp
> clang/utils/TableGen/ClangSyntaxEmitter.cpp
> clang/utils/TableGen/ClangTypeNodesEmitter.cpp
> lldb/utils/TableGen/LLDBOptionDefEmitter.cpp
> lldb/utils/TableGen/LLDBPropertyDefEmitter.cpp
> llvm/include/llvm/TableGen/TableGenBackend.h
> llvm/lib/TableGen/TableGenBackend.cpp
> llvm/utils/TableGen/AsmMatcherEmitter.cpp
> llvm/utils/TableGen/AsmWriterEmitter.cpp llvm/utils/TableGen/VTEmitter.cpp
> mlir/tools/mlir-tblgen/DialectGen.cpp mlir/tools/mlir-tblgen/EnumsGen.cpp
> mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
> mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
> mlir/tools/mlir-tblgen/RewriterGen.cpp
> mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
> ```
>
> View the diff from clang-format here.
> ```diff
> diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp
> b/clang/utils/TableGen/ClangAttrEmitter.cpp
> index 6ba82a22df1e..dddc9b9896ef 100644
> --- a/clang/utils/TableGen/ClangAttrEmitter.cpp
> +++ b/clang/utils/TableGen/ClangAttrEmitter.cpp
> @@ -3170,27 +3170,27 @@ namespace clang {
>
> // Emits the enumeration list for attributes.
> void EmitClangAttrList(RecordKeeper , raw_ostream ) {
> - emitSourceFileHeader("List of all attributes that Clang recognizes", OS,
> - Records);
> +emitSourceFileHeader("List of all attributes that Clang recognizes", OS,
> + Records);
>
> - AttrClassHierarchy Hierarchy(Records);
> +AttrClassHierarchy Hierarchy(Records);
>
> - // Add defaulting macro definitions.
> - Hierarchy.emitDefaultDefines(OS);
> - emitDefaultDefine(OS, "PRAGMA_SPELLING_ATTR", nullptr);
> +// Add defaulting macro definitions.
> +Hierarchy.emitDefaultDefines(OS);
> +emitDefaultDefine(OS, "PRAGMA_SPELLING_ATTR", nullptr);
>
> - std::vector Attrs = Records.getAllDerivedDefinitions("Attr");
> - std::vector PragmaAttrs;
> - for (auto *Attr : Attrs) {
> -if (!Attr->getValueAsBit("ASTNode"))
> - continue;
> +std::vector Attrs = Records.getAllDerivedDefinitions("Attr");
> +std::vector PragmaAttrs;
> +for (auto *Attr : Attrs) {
> + if (!Attr->getValueAsBit("ASTNode"))
> +continue;
>
> -// Add the attribute to the ad-hoc groups.
> -if (AttrHasPragmaSpelling(Attr))
> - PragmaAttrs.push_back(Attr);
> + // Add the attribute to the ad-hoc groups.
> + if (AttrHasPragmaSpelling(Attr))
> +PragmaAttrs.push_back(Attr);
>
> -// Place it in the hierarchy.
> -Hierarchy.classifyAttr(Attr);
> + // Place it in the hierarchy.
> + Hierarchy.classifyAttr(Attr);
>}
>
>// Emit the main attribute list.
> ```
Is this suggestion correct?
https://github.com/llvm/llvm-project/pull/65744
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm][tblgen] Add `SourcePath` for `emitSourceFileHeader` (PR #65744)
https://github.com/sunshaoce updated
https://github.com/llvm/llvm-project/pull/65744
>From 23d0b738bf40ea44e159f4f8d7355d4d6bc0688d Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sat, 23 Sep 2023 11:38:33 +0800
Subject: [PATCH 1/2] [llvm][tblgen] Add `SourcePath` for
`emitSourceFileHeader`
---
llvm/include/llvm/TableGen/TableGenBackend.h | 3 ++-
llvm/lib/TableGen/TableGenBackend.cpp| 7 ++-
llvm/utils/TableGen/VTEmitter.cpp| 3 ++-
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/TableGen/TableGenBackend.h
b/llvm/include/llvm/TableGen/TableGenBackend.h
index 39f1e14bc950841..7bbd163b0433aca 100644
--- a/llvm/include/llvm/TableGen/TableGenBackend.h
+++ b/llvm/include/llvm/TableGen/TableGenBackend.h
@@ -50,7 +50,8 @@ template class OptClass : Opt {
/// emitSourceFileHeader - Output an LLVM style file header to the specified
/// raw_ostream.
-void emitSourceFileHeader(StringRef Desc, raw_ostream );
+void emitSourceFileHeader(StringRef Desc, raw_ostream ,
+ StringRef SourcePath = "");
} // End llvm namespace
diff --git a/llvm/lib/TableGen/TableGenBackend.cpp
b/llvm/lib/TableGen/TableGenBackend.cpp
index 135ec643bc3a7df..a50df8dbdcfb220 100644
--- a/llvm/lib/TableGen/TableGenBackend.cpp
+++ b/llvm/lib/TableGen/TableGenBackend.cpp
@@ -40,7 +40,8 @@ static void printLine(raw_ostream , const Twine ,
char Fill,
OS << Suffix << '\n';
}
-void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream ) {
+void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream ,
+StringRef SourcePath) {
printLine(OS, "/*===- TableGen'erated file ", '-', "*- C++ -*-===*\\");
StringRef Prefix("|* ");
StringRef Suffix(" *|");
@@ -59,4 +60,8 @@ void llvm::emitSourceFileHeader(StringRef Desc, raw_ostream
) {
printLine(OS, Prefix, ' ', Suffix);
printLine(OS, "\\*===", '-', "===*/");
OS << '\n';
+
+ // Print the path of source file
+ if (!SourcePath.empty())
+OS << "// Generated from: " << SourcePath << "\n\n";
}
diff --git a/llvm/utils/TableGen/VTEmitter.cpp
b/llvm/utils/TableGen/VTEmitter.cpp
index d398a7e7b58f40a..03fa3d64b41fe6c 100644
--- a/llvm/utils/TableGen/VTEmitter.cpp
+++ b/llvm/utils/TableGen/VTEmitter.cpp
@@ -30,7 +30,8 @@ class VTEmitter {
} // End anonymous namespace.
void VTEmitter::run(raw_ostream ) {
- emitSourceFileHeader("ValueTypes Source Fragment", OS);
+ emitSourceFileHeader("ValueTypes Source Fragment", OS,
+ Records.getInputFilename());
std::array VTsByNumber = {};
auto ValueTypes = Records.getAllDerivedDefinitions("ValueType");
>From d07486764071679c8cbcd5e7c4905eb41b4770b3 Mon Sep 17 00:00:00 2001
From: Shao-Ce SUN
Date: Sun, 24 Sep 2023 00:52:02 +0800
Subject: [PATCH 2/2] add more tests
---
clang/utils/TableGen/ClangASTNodesEmitter.cpp | 4 +-
.../TableGen/ClangASTPropertiesEmitter.cpp| 8 ++--
clang/utils/TableGen/ClangAttrEmitter.cpp | 47 +++
.../ClangCommentCommandInfoEmitter.cpp| 8 ++--
...mentHTMLNamedCharacterReferenceEmitter.cpp | 4 +-
.../TableGen/ClangCommentHTMLTagsEmitter.cpp | 5 +-
.../TableGen/ClangOpenCLBuiltinEmitter.cpp| 6 +--
clang/utils/TableGen/ClangSyntaxEmitter.cpp | 4 +-
.../utils/TableGen/ClangTypeNodesEmitter.cpp | 2 +-
lldb/utils/TableGen/LLDBOptionDefEmitter.cpp | 2 +-
.../utils/TableGen/LLDBPropertyDefEmitter.cpp | 4 +-
llvm/include/llvm/TableGen/TableGenBackend.h | 3 +-
llvm/lib/TableGen/TableGenBackend.cpp | 6 +--
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +-
llvm/utils/TableGen/AsmWriterEmitter.cpp | 2 +-
llvm/utils/TableGen/VTEmitter.cpp | 3 +-
mlir/tools/mlir-tblgen/DialectGen.cpp | 4 +-
mlir/tools/mlir-tblgen/EnumsGen.cpp | 4 +-
mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp | 2 +-
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 4 +-
mlir/tools/mlir-tblgen/RewriterGen.cpp| 2 +-
mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 22 +
22 files changed, 81 insertions(+), 67 deletions(-)
diff --git a/clang/utils/TableGen/ClangASTNodesEmitter.cpp
b/clang/utils/TableGen/ClangASTNodesEmitter.cpp
index 2b8d7a9efdf10c9..16a1c74b9d91ad6 100644
--- a/clang/utils/TableGen/ClangASTNodesEmitter.cpp
+++ b/clang/utils/TableGen/ClangASTNodesEmitter.cpp
@@ -169,7 +169,7 @@ void ClangASTNodesEmitter::deriveChildTree() {
void ClangASTNodesEmitter::run(raw_ostream ) {
deriveChildTree();
- emitSourceFileHeader("List of AST nodes of a particular kind", OS);
+ emitSourceFileHeader("List of AST nodes of a particular kind", OS, Records);
// Write the preamble
OS << "#ifndef ABSTRACT_" << macroHierarchyName() << "\n";
@@ -205,7 +205,7 @@ void clang::EmitClangASTNodes(RecordKeeper , raw_ostream
,
void clang::EmitClangDeclContext(RecordKeeper , raw_ostream ) {
// FIXME: Find a .td file format to allow for this to be represented better.
[clang] 876df74 - [flang][driver] Allow main program to be in an archive
Author: Shao-Ce SUN
Date: 2023-04-28T09:53:25+08:00
New Revision: 876df74dd47196a9ca3b4fff21ffb5441491a0a0
URL:
https://github.com/llvm/llvm-project/commit/876df74dd47196a9ca3b4fff21ffb5441491a0a0
DIFF:
https://github.com/llvm/llvm-project/commit/876df74dd47196a9ca3b4fff21ffb5441491a0a0.diff
LOG: [flang][driver] Allow main program to be in an archive
Add --undefined=_QQmain to the link line, so that a Fortran main program
will be included in the link job even if it is in an archive (unless we
are building a shared object). For now, this is only applied to the Gnu
toolchain.
We also add a section on the linker invocation to docs/FlangDriver.md.
The new tests require llvm-ar to construct an archive we can include in
the link job. This is a new dependency for flang/test (which already
depends on similar tools such as llvm-objdump).
See discussions in
https://github.com/llvm/llvm-project/issues/54787
which this patch fixes.
Reviewed By: awarzynski
Differential Revision: https://reviews.llvm.org/D134821
Added:
flang/test/Driver/link-c-main.c
flang/test/Driver/link-f90-main.f90
Modified:
clang/lib/Driver/ToolChains/Gnu.cpp
flang/docs/FlangDriver.md
flang/test/CMakeLists.txt
flang/test/Driver/linker-flags.f90
Removed:
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index b0716322bc141..c4a276126b653 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -598,6 +598,14 @@ void tools::gnutools::Linker::ConstructJob(Compilation ,
const JobAction ,
// these dependencies need to be listed before the C runtime below (i.e.
// AddRuntTimeLibs).
if (D.IsFlangMode()) {
+// A Fortran main program will be lowered to a function named _QQmain. Make
+// _QQmain an undefined symbol, so that it's correctly resolved even when
+// creating executable from archives. This is a workaround for how and
where
+// Flang's `main` is defined. For more context, see:
+// * https://github.com/llvm/llvm-project/issues/54787
+if (!Args.hasArg(options::OPT_shared))
+ CmdArgs.push_back("--undefined=_QQmain");
+
addFortranRuntimeLibraryPath(ToolChain, Args, CmdArgs);
addFortranRuntimeLibs(ToolChain, CmdArgs);
CmdArgs.push_back("-lm");
diff --git a/flang/docs/FlangDriver.md b/flang/docs/FlangDriver.md
index 6c2a473820634..9522e223b17b5 100644
--- a/flang/docs/FlangDriver.md
+++ b/flang/docs/FlangDriver.md
@@ -149,13 +149,6 @@ flang-new -ccc-print-phases -c file.f
+- 3: backend, {2}, assembler
4: assembler, {3}, object
```
-Note that currently Flang does not support code-generation and `flang-new` will
-fail during the second step above with the following error:
-```bash
-error: code-generation is not available yet
-```
-The other phases are printed nonetheless when using `-ccc-print-phases`, as
-that reflects what `clangDriver`, the library, will try to create and run.
For actions specific to the frontend (e.g. preprocessing or code generation), a
command to call the frontend driver is generated (more specifically, an
@@ -205,6 +198,41 @@ is `ParseSyntaxOnlyAction`, which corresponds to
`-fsyntax-only`. In other
words, `flang-new -fc1 ` is equivalent to `flang-new -fc1
-fsyntax-only
`.
+## Linker invocation
+> **_NOTE:_** Linker invocation through the `flang-new` driver is so far
+> experimental. This section describes the currently intended design, and not
+> necessarily what is implemented.
+
+Calling
+```bash
+flang-new -flang-experimental-exec prog.f90
+```
+will, on a high level, do two things:
+* call the frontend driver, `flang-new -fc1`, to build the object file `prog.o`
+* call the system linker to build the executable `a.out`.
+
+In both invocations, `flang-new` will add default options to the frontend
driver
+and the linker invocations. To see the exact invocations on your system, you
can
+call
+```bash
+flang-new -### prog.f90
+```
+The link line will contain a fair number of options, which will depend on your
+system. Compared to when linking a C program with `clang`, the main additions
+are (on GNU/linux),
+* `--undefined=_QQmain`: A Fortran main program will appear in the
corresponding
+ object file as a function called `_QQmain`. This flag makes sure that an
+ object file containing a Fortran main program (i.e., a symbol `_QQmain`) be
+ included in the linking also when it is bundled in an archive.
+* `-lFortran_main`: The Fortran_main archive is part of Flang's runtime. It
+ exports the symbol `main`, i.e., a c main function, which will make some
+ initial configuration before calling `_QQmain`, and clean up before
returning.
+* `-lFortranRuntime`: Flang's Fortran runtime, containing, for example,
+ implementations of intrinsic functions.
+* `-lFortranDecimal`: Part of Flang's runtime, containing routines for parsing
+ and formatting decimal
[clang] 36278b7 - [Flang][RISCV] Emit target features for RISC-V
Author: Shao-Ce SUN Date: 2023-03-15T19:39:13+08:00 New Revision: 36278b735fa193c954bf38c82ca81a5608bc5187 URL: https://github.com/llvm/llvm-project/commit/36278b735fa193c954bf38c82ca81a5608bc5187 DIFF: https://github.com/llvm/llvm-project/commit/36278b735fa193c954bf38c82ca81a5608bc5187.diff LOG: [Flang][RISCV] Emit target features for RISC-V Fix the issue of .o file generated by `Flang` with `Flags` info is 0x0 under RISC-V. Reviewed By: awarzynski, kiranchandramohan Differential Revision: https://reviews.llvm.org/D145883 Added: flang/test/Driver/code-gen-rv64.f90 flang/test/Driver/target-cpu-features-invalid.f90 Modified: clang/lib/Driver/ToolChains/Flang.cpp flang/test/Driver/target-cpu-features.f90 Removed: diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 84d93f56a4419..10a518c34351d 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -105,7 +105,7 @@ void Flang::addTargetOptions(const ArgList , default: break; case llvm::Triple::aarch64: -[[fallthrough]]; + case llvm::Triple::riscv64: case llvm::Triple::x86_64: getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); break; diff --git a/flang/test/Driver/code-gen-rv64.f90 b/flang/test/Driver/code-gen-rv64.f90 new file mode 100644 index 0..69d08b28c94ae --- /dev/null +++ b/flang/test/Driver/code-gen-rv64.f90 @@ -0,0 +1,17 @@ +! Test -emit-obj (RISC-V 64) + +! REQUIRES: riscv-registered-target + +! RUN: rm -f %t.o +! RUN: %flang_fc1 -triple riscv64-unknown-linux-gnu \ +! RUN: -target-feature +d -target-feature +c -emit-obj %s -o %t.o +! RUN: llvm-readelf -h %t.o | FileCheck %s + +! RUN: rm -f %t.o +! RUN: %flang --target=riscv64-unknown-linux-gnu -c %s -o %t.o +! RUN: llvm-readelf -h %t.o | FileCheck %s + +! If Flang failed to emit target-feature info, then Flags will be 0x0. +! 0x5 means set EF_RISCV_RVC (0x1) and EF_RISCV_FLOAT_ABI_DOUBLE (0x4) +! CHECK: Flags: 0x5, RVC, double-float ABI +end program diff --git a/flang/test/Driver/target-cpu-features-invalid.f90 b/flang/test/Driver/target-cpu-features-invalid.f90 new file mode 100644 index 0..7ecbe597637c6 --- /dev/null +++ b/flang/test/Driver/target-cpu-features-invalid.f90 @@ -0,0 +1,13 @@ +! REQUIRES: aarch64-registered-target + +! Test that invalid cpu and features are ignored. + +! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \ +! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU + +! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \ +! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-FEATURE + + +! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor) +! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature) diff --git a/flang/test/Driver/target-cpu-features.f90 b/flang/test/Driver/target-cpu-features.f90 index 1ce416f0cf533..ca2ed274a6b6e 100644 --- a/flang/test/Driver/target-cpu-features.f90 +++ b/flang/test/Driver/target-cpu-features.f90 @@ -1,5 +1,3 @@ -! REQUIRES: aarch64-registered-target, x86-registered-target - ! Test that -mcpu/march are used and that the -target-cpu and -target-features ! are also added to the fc1 command. @@ -22,14 +20,8 @@ ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H - -! Test that invalid cpu and features are ignored. - -! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-cpu supercpu \ -! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU - -! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \ -! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-FEATURE +! RUN: %flang --target=riscv64-linux-gnu -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-RV64 ! CHECK-A57: "-fc1" "-triple" "aarch64-unknown-linux-gnu" @@ -52,5 +44,5 @@ ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu" ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase" -! CHECK-INVALID-CPU: 'supercpu' is not a recognized processor for this target (ignoring processor) -! CHECK-INVALID-FEATURE: '+superspeed' is not a recognized feature for this target (ignoring feature) +! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu" +! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+c" ___ cfe-commits mailing list cfe-commits@lists.llvm.org
[clang] b1fdcd5 - [Flang] Allow compile *.f03, *.f08 file
Author: Shao-Ce SUN
Date: 2023-03-12T01:11:42+08:00
New Revision: b1fdcd5fbc09f9f3e1c8a8b954aa8f9067401b31
URL:
https://github.com/llvm/llvm-project/commit/b1fdcd5fbc09f9f3e1c8a8b954aa8f9067401b31
DIFF:
https://github.com/llvm/llvm-project/commit/b1fdcd5fbc09f9f3e1c8a8b954aa8f9067401b31.diff
LOG: [Flang] Allow compile *.f03, *.f08 file
Fix issue [#61260](https://github.com/llvm/llvm-project/issues/61260)
Reviewed By: awarzynski
Differential Revision: https://reviews.llvm.org/D145845
Added:
flang/test/Driver/supported-suffices/f03-suffix.f03
flang/test/Driver/supported-suffices/f08-suffix.f08
Modified:
clang/lib/Driver/Types.cpp
Removed:
diff --git a/clang/lib/Driver/Types.cpp b/clang/lib/Driver/Types.cpp
index a890cc58ee421..7d6308d757bc7 100644
--- a/clang/lib/Driver/Types.cpp
+++ b/clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@ types::ID types::lookupTypeForExtension(llvm::StringRef
Ext) {
.Case("cui", TY_PP_CUDA)
.Case("cxx", TY_CXX)
.Case("CXX", TY_CXX)
+ .Case("F03", TY_Fortran)
+ .Case("f03", TY_PP_Fortran)
+ .Case("F08", TY_Fortran)
+ .Case("f08", TY_PP_Fortran)
.Case("F90", TY_Fortran)
.Case("f90", TY_PP_Fortran)
.Case("F95", TY_Fortran)
diff --git a/flang/test/Driver/supported-suffices/f03-suffix.f03
b/flang/test/Driver/supported-suffices/f03-suffix.f03
new file mode 100644
index 0..6e03f9f43fc60
--- /dev/null
+++ b/flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f03
+end program f03
diff --git a/flang/test/Driver/supported-suffices/f08-suffix.f08
b/flang/test/Driver/supported-suffices/f08-suffix.f08
new file mode 100644
index 0..d5bcf4ce1de1c
--- /dev/null
+++ b/flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "-o" "{{.*}}.o"
+program f08
+end program f08
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[clang] 56cc0bb - Revert "[Flang] Allow compile *.f03, *.f08 file"
Author: Shao-Ce SUN
Date: 2023-03-12T00:06:09+08:00
New Revision: 56cc0bbe41fd41fb0766062ca0975eba64e92447
URL:
https://github.com/llvm/llvm-project/commit/56cc0bbe41fd41fb0766062ca0975eba64e92447
DIFF:
https://github.com/llvm/llvm-project/commit/56cc0bbe41fd41fb0766062ca0975eba64e92447.diff
LOG: Revert "[Flang] Allow compile *.f03, *.f08 file"
The test will fail in the MSVC environment.
This reverts commit 171794de533b400edb47f0e6df4375a7ae052fc8.
Added:
Modified:
clang/lib/Driver/Types.cpp
Removed:
flang/test/Driver/supported-suffices/f03-suffix.f03
flang/test/Driver/supported-suffices/f08-suffix.f08
diff --git a/clang/lib/Driver/Types.cpp b/clang/lib/Driver/Types.cpp
index 7d6308d757bc7..a890cc58ee421 100644
--- a/clang/lib/Driver/Types.cpp
+++ b/clang/lib/Driver/Types.cpp
@@ -331,10 +331,6 @@ types::ID types::lookupTypeForExtension(llvm::StringRef
Ext) {
.Case("cui", TY_PP_CUDA)
.Case("cxx", TY_CXX)
.Case("CXX", TY_CXX)
- .Case("F03", TY_Fortran)
- .Case("f03", TY_PP_Fortran)
- .Case("F08", TY_Fortran)
- .Case("f08", TY_PP_Fortran)
.Case("F90", TY_Fortran)
.Case("f90", TY_PP_Fortran)
.Case("F95", TY_Fortran)
diff --git a/flang/test/Driver/supported-suffices/f03-suffix.f03
b/flang/test/Driver/supported-suffices/f03-suffix.f03
deleted file mode 100644
index e1c74e065ca14..0
--- a/flang/test/Driver/supported-suffices/f03-suffix.f03
+++ /dev/null
@@ -1,5 +0,0 @@
-! RUN: %flang -### %s 2>&1 | FileCheck %s
-
-! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
-program f03
-end program f03
diff --git a/flang/test/Driver/supported-suffices/f08-suffix.f08
b/flang/test/Driver/supported-suffices/f08-suffix.f08
deleted file mode 100644
index e9039d14529b1..0
--- a/flang/test/Driver/supported-suffices/f08-suffix.f08
+++ /dev/null
@@ -1,5 +0,0 @@
-! RUN: %flang -### %s 2>&1 | FileCheck %s
-
-! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
-program f08
-end program f08
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[clang] 171794d - [Flang] Allow compile *.f03, *.f08 file
Author: Shao-Ce SUN
Date: 2023-03-11T23:23:21+08:00
New Revision: 171794de533b400edb47f0e6df4375a7ae052fc8
URL:
https://github.com/llvm/llvm-project/commit/171794de533b400edb47f0e6df4375a7ae052fc8
DIFF:
https://github.com/llvm/llvm-project/commit/171794de533b400edb47f0e6df4375a7ae052fc8.diff
LOG: [Flang] Allow compile *.f03, *.f08 file
Fix issue [#61260](https://github.com/llvm/llvm-project/issues/61260)
Reviewed By: awarzynski
Differential Revision: https://reviews.llvm.org/D145845
Added:
flang/test/Driver/supported-suffices/f03-suffix.f03
flang/test/Driver/supported-suffices/f08-suffix.f08
Modified:
clang/lib/Driver/Types.cpp
Removed:
diff --git a/clang/lib/Driver/Types.cpp b/clang/lib/Driver/Types.cpp
index a890cc58ee421..7d6308d757bc7 100644
--- a/clang/lib/Driver/Types.cpp
+++ b/clang/lib/Driver/Types.cpp
@@ -331,6 +331,10 @@ types::ID types::lookupTypeForExtension(llvm::StringRef
Ext) {
.Case("cui", TY_PP_CUDA)
.Case("cxx", TY_CXX)
.Case("CXX", TY_CXX)
+ .Case("F03", TY_Fortran)
+ .Case("f03", TY_PP_Fortran)
+ .Case("F08", TY_Fortran)
+ .Case("f08", TY_PP_Fortran)
.Case("F90", TY_Fortran)
.Case("f90", TY_PP_Fortran)
.Case("F95", TY_Fortran)
diff --git a/flang/test/Driver/supported-suffices/f03-suffix.f03
b/flang/test/Driver/supported-suffices/f03-suffix.f03
new file mode 100644
index 0..e1c74e065ca14
--- /dev/null
+++ b/flang/test/Driver/supported-suffices/f03-suffix.f03
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f03
+end program f03
diff --git a/flang/test/Driver/supported-suffices/f08-suffix.f08
b/flang/test/Driver/supported-suffices/f08-suffix.f08
new file mode 100644
index 0..e9039d14529b1
--- /dev/null
+++ b/flang/test/Driver/supported-suffices/f08-suffix.f08
@@ -0,0 +1,5 @@
+! RUN: %flang -### %s 2>&1 | FileCheck %s
+
+! CHECK: "{{.*}}flang-new" "-fc1" {{.*}} "/tmp/{{.*}}.o"
+program f08
+end program f08
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[clang] 7167a42 - [RISCV] Add zihintntl instructions
Author: Shao-Ce SUN
Date: 2022-08-22T12:06:30+08:00
New Revision: 7167a4207ee2c07cb192da1788f919332f83b456
URL:
https://github.com/llvm/llvm-project/commit/7167a4207ee2c07cb192da1788f919332f83b456
DIFF:
https://github.com/llvm/llvm-project/commit/7167a4207ee2c07cb192da1788f919332f83b456.diff
LOG: [RISCV] Add zihintntl instructions
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D121670
Added:
llvm/test/MC/RISCV/rv32zihintntl-valid.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 38cef26cdc845..deb333c46dedd 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -18,6 +18,7 @@
// CHECK-NOT: __riscv_compressed
// CHECK-NOT: __riscv_b
// CHECK-NOT: __riscv_bitmanip
+// CHECK-NOT: __riscv_zihintntl
// CHECK-NOT: __riscv_zba
// CHECK-NOT: __riscv_zbb
// CHECK-NOT: __riscv_zbc
@@ -110,6 +111,14 @@
// CHECK-C-EXT: __riscv_c 200{{$}}
// CHECK-C-EXT: __riscv_compressed 1
+// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv32izihintntl0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu
-menable-experimental-extensions \
+// RUN: -march=rv64izihintntl0p2 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
+// CHECK-ZIHINTNTL-EXT: __riscv_zihintntl 2000{{$}}
+
// RUN: %clang -target riscv32-unknown-linux-gnu \
// RUN: -march=rv32izba1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 524df1a2e859b..a666337ee5619 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -104,6 +104,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
+{"zihintntl", RISCVExtensionVersion{0, 2}},
+
{"zbe", RISCVExtensionVersion{0, 93}},
{"zbf", RISCVExtensionVersion{0, 93}},
{"zbm", RISCVExtensionVersion{0, 93}},
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 83ae2f70b0f41..6d9836f28a1bd 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -61,6 +61,13 @@ def HasStdExtZihintpause :
Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of
FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
+def FeatureStdExtZihintntl
+: SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true",
+ "'zihintntl' (Non-Temporal Locality Hints)">;
+def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
+AssemblerPredicate<(all_of
FeatureStdExtZihintntl),
+"'Zihintntl' (Non-Temporal Locality
Hints)">;
+
def FeatureStdExtZfhmin
: SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
"'Zfhmin' (Half-Precision Floating-Point Minimal)",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 224974e40e3c2..9b5154d1264e1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -961,6 +961,13 @@ def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs,
X0)>;
def : InstAlias<"hfence.vvma", (HFENCE_VVMA X0, X0)>;
def : InstAlias<"hfence.vvma $rs", (HFENCE_VVMA GPR:$rs, X0)>;
+let Predicates = [HasStdExtZihintntl] in {
+ def : InstAlias<"ntl.p1", (ADD X0, X0, X2)>;
+ def : InstAlias<"ntl.pall", (ADD X0, X0, X3)>;
+ def : InstAlias<"ntl.s1", (ADD X0, X0, X4)>;
+ def : InstAlias<"ntl.all",(ADD X0, X0, X5)>;
+} // Predicates = [HasStdExtZihintntl]
+
let EmitPriority = 0 in {
def : InstAlias<"lb $rd, (${rs1})",
(LB GPR:$rd, GPR:$rs1, 0)>;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index a4598c18ec6e0..864429e52003a 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtD = false;
bool HasStdExtC = false;
bool HasStdExtZihintpause = false;
+ bool HasStdExtZihintntl = false;
bool HasStdExtZba = false;
bool HasStdExtZbb = false;
bool
[clang] e180cc5 - [Driver][test] Make RISCV tests robust with PATH=
Author: Shao-Ce SUN
Date: 2022-06-15T22:25:22+08:00
New Revision: e180cc5ff1a133c533e68bb92024d2455d5e6978
URL:
https://github.com/llvm/llvm-project/commit/e180cc5ff1a133c533e68bb92024d2455d5e6978
DIFF:
https://github.com/llvm/llvm-project/commit/e180cc5ff1a133c533e68bb92024d2455d5e6978.diff
LOG: [Driver][test] Make RISCV tests robust with PATH=
When `riscv64-unknown-linux-gnu-ld` is in the PATH, `clang -### -fuse-ld=ld
--target=riscv64-unknown-linux-gnu` will use unknown-linux-gnu-ld first, which
causes the error in the lit test.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D127589
Added:
Modified:
clang/test/Driver/riscv64-toolchain.c
Removed:
diff --git a/clang/test/Driver/riscv64-toolchain.c
b/clang/test/Driver/riscv64-toolchain.c
index ec3707412e2aa..78ce26c181284 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -15,7 +15,7 @@
// In the below tests, --rtlib=platform is used so that the driver ignores
// the configure-time CLANG_DEFAULT_RTLIB option when choosing the runtime lib
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
// RUN: --target=riscv64-unknown-elf --rtlib=platform \
// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1
-no-pie \
@@ -30,7 +30,7 @@
// C-RV64-BAREMETAL-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
// C-RV64-BAREMETAL-LP64:
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
-// RUN: %clang -### %s -fuse-ld= \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= \
// RUN: --target=riscv64-unknown-elf --rtlib=platform \
// RUN: --sysroot= \
// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -44,7 +44,7 @@
// C-RV64-BAREMETAL-NOSYSROOT-LP64: "--start-group" "-lc" "-lgloss"
"--end-group" "-lgcc"
// C-RV64-BAREMETAL-NOSYSROOT-LP64:
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
// RUN: --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf 2>&1 \
@@ -60,7 +60,7 @@
// CXX-RV64-BAREMETAL-LP64: "-lstdc++" "--start-group" "-lc" "-lgloss"
"--end-group" "-lgcc"
// CXX-RV64-BAREMETAL-LP64:
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
-// RUN: %clangxx -### %s -fuse-ld= \
+// RUN: env "PATH=" %clangxx -### %s -fuse-ld= \
// RUN: --target=riscv64-unknown-elf -stdlib=libstdc++ --rtlib=platform \
// RUN: --sysroot= \
// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \
@@ -75,7 +75,7 @@
// CXX-RV64-BAREMETAL-NOSYSROOT-LP64: "-lstdc++" "--start-group" "-lc"
"-lgloss" "--end-group" "-lgcc"
// CXX-RV64-BAREMETAL-NOSYSROOT-LP64:
"{{.*}}/Inputs/basic_riscv64_tree/lib/gcc/riscv64-unknown-elf/8.0.1{{/|}}crtend.o"
-// RUN: %clang -### %s -fuse-ld= -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \
// RUN: --target=riscv64-unknown-linux-gnu --rtlib=platform -mabi=lp64 \
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -90,7 +90,7 @@
// C-RV64-LINUX-MULTI-LP64:
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64"
// C-RV64-LINUX-MULTI-LP64:
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64"
-// RUN: %clang -### %s -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang -### %s -fuse-ld=ld -no-pie \
// RUN: --target=riscv64-unknown-linux-gnu --rtlib=platform -march=rv64imafd
\
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
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[clang] fa9c8ba - [RISCV] Support k-ext clang intrinsics
Author: Shao-Ce SUN Date: 2022-03-05T13:57:18+08:00 New Revision: fa9c8bab0c7a7aed423191baa8a980533ae5602a URL: https://github.com/llvm/llvm-project/commit/fa9c8bab0c7a7aed423191baa8a980533ae5602a DIFF: https://github.com/llvm/llvm-project/commit/fa9c8bab0c7a7aed423191baa8a980533ae5602a.diff LOG: [RISCV] Support k-ext clang intrinsics Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D112774 Added: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkc.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkx.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkc.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkx.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c Modified: clang/include/clang/Basic/BuiltinsRISCV.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Sema/SemaChecking.cpp clang/test/Driver/riscv-arch.c clang/test/Preprocessor/riscv-target-features.c Removed: diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def index 495a036e576f8..73ec6eae7e955 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -19,11 +19,15 @@ TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb") TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit") -// Zbc extension -TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc") -TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc") +// Zbc or Zbkc extension +TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc") +TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc") TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "zbc") +// Zbkx +TARGET_BUILTIN(__builtin_riscv_xperm4, "LiLiLi", "nc", "zbkx") +TARGET_BUILTIN(__builtin_riscv_xperm8, "LiLiLi", "nc", "zbkx") + // Zbe extension TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe") TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc", @@ -67,5 +71,52 @@ TARGET_BUILTIN(__builtin_riscv_fsr_32, "LiLiLiLi", "nc", "experimental-zbt") TARGET_BUILTIN(__builtin_riscv_fsl_64, "WiWiWiWi", "nc", "experimental-zbt,64bit") TARGET_BUILTIN(__builtin_riscv_fsr_64, "WiWiWiWi", "nc", "experimental-zbt,64bit") +// Zbkb extension +TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb") +TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb") +TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb") + +// Zknd extension +TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUc", "nc", "zknd") +TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUc", "nc", "zknd") +TARGET_BUILTIN(__builtin_riscv_aes64ds_64, "WiWiWi", "nc", "zknd,64bit") +TARGET_BUILTIN(__builtin_riscv_aes64dsm_64, "WiWiWi", "nc", "zknd,64bit") +TARGET_BUILTIN(__builtin_riscv_aes64im_64, "WiWi", "nc", "zknd,64bit") + +// Zknd & zkne +TARGET_BUILTIN(__builtin_riscv_aes64ks1i_64, "WiWiIUi", "nc", "zknd|zkne,64bit") +TARGET_BUILTIN(__builtin_riscv_aes64ks2_64, "WiWiWi", "nc", "zknd|zkne,64bit") + +// Zkne extension +TARGET_BUILTIN(__builtin_riscv_aes32esi_32, "ZiZiZiIUc", "nc", "zkne") +TARGET_BUILTIN(__builtin_riscv_aes32esmi_32, "ZiZiZiIUc", "nc", "zkne") +TARGET_BUILTIN(__builtin_riscv_aes64es_64, "WiWiWi", "nc", "zkne,64bit") +TARGET_BUILTIN(__builtin_riscv_aes64esm_64, "WiWiWi", "nc", "zkne,64bit") + +// Zknh extension +TARGET_BUILTIN(__builtin_riscv_sha256sig0, "LiLi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha256sig1, "LiLi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha256sum0, "LiLi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha256sum1, "LiLi", "nc", "zknh") + +TARGET_BUILTIN(__builtin_riscv_sha512sig0h_32, "ZiZiZi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha512sig0l_32, "ZiZiZi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha512sig1h_32, "ZiZiZi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha512sig1l_32, "ZiZiZi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha512sum0r_32, "ZiZiZi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha512sum1r_32, "ZiZiZi", "nc", "zknh") +TARGET_BUILTIN(__builtin_riscv_sha512sig0_64, "WiWi", "nc", "zknh,64bit")
[clang] a8b4b91 - [NFC][clang] Simplify `isOneOf` function
Author: Shao-Ce SUN
Date: 2022-02-24T19:12:34+08:00
New Revision: a8b4b9104c8f7ab5edb8651a900e61279e8bf931
URL:
https://github.com/llvm/llvm-project/commit/a8b4b9104c8f7ab5edb8651a900e61279e8bf931
DIFF:
https://github.com/llvm/llvm-project/commit/a8b4b9104c8f7ab5edb8651a900e61279e8bf931.diff
LOG: [NFC][clang] Simplify `isOneOf` function
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D117740
Added:
Modified:
clang/include/clang/Lex/Token.h
Removed:
diff --git a/clang/include/clang/Lex/Token.h b/clang/include/clang/Lex/Token.h
index 00fbe6d18f721..7115d68f0f269 100644
--- a/clang/include/clang/Lex/Token.h
+++ b/clang/include/clang/Lex/Token.h
@@ -99,9 +99,8 @@ class Token {
bool isOneOf(tok::TokenKind K1, tok::TokenKind K2) const {
return is(K1) || is(K2);
}
- template
- bool isOneOf(tok::TokenKind K1, tok::TokenKind K2, Ts... Ks) const {
-return is(K1) || isOneOf(K2, Ks...);
+ template bool isOneOf(tok::TokenKind K1, Ts... Ks) const {
+return is(K1) || isOneOf(Ks...);
}
/// Return true if this is a raw identifier (when lexing
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[clang] 9cc49c1 - Revert "[NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`"
Author: Shao-Ce SUN
Date: 2022-02-16T11:57:49+08:00
New Revision: 9cc49c1951dcc4db594bf1f90755e16f89efd1ca
URL:
https://github.com/llvm/llvm-project/commit/9cc49c1951dcc4db594bf1f90755e16f89efd1ca
DIFF:
https://github.com/llvm/llvm-project/commit/9cc49c1951dcc4db594bf1f90755e16f89efd1ca.diff
LOG: Revert "[NFC][MC] remove unused argument `MCRegisterInfo` in
`MCCodeEmitter`"
This reverts commit fe25c06cc5bdc2ef9427309f8ec1434aad69dc7a.
Added:
Modified:
bolt/include/bolt/Core/BinaryContext.h
bolt/lib/Core/BinaryContext.cpp
clang/tools/driver/cc1as_main.cpp
llvm/include/llvm/MC/TargetRegistry.h
llvm/lib/CodeGen/LLVMTargetMachine.cpp
llvm/lib/DWARFLinker/DWARFStreamer.cpp
llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/tools/llvm-dwp/llvm-dwp.cpp
llvm/tools/llvm-exegesis/lib/LlvmState.cpp
llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
llvm/tools/llvm-mc/llvm-mc.cpp
llvm/tools/llvm-mca/llvm-mca.cpp
llvm/tools/llvm-ml/llvm-ml.cpp
llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
llvm/unittests/MC/DwarfLineTableHeaders.cpp
mlir/lib/Dialect/GPU/Transforms/SerializeToHsaco.cpp
Removed:
diff --git a/bolt/include/bolt/Core/BinaryContext.h
b/bolt/include/bolt/Core/BinaryContext.h
index aff770112be1c..c626af3a897d6 100644
--- a/bolt/include/bolt/Core/BinaryContext.h
+++ b/bolt/include/bolt/Core/BinaryContext.h
@@ -1192,14 +1192,14 @@ class BinaryContext {
/*PIC=*/!HasFixedLoadAddress));
MCEInstance.LocalCtx->setObjectFileInfo(MCEInstance.LocalMOFI.get());
MCEInstance.MCE.reset(
-TheTarget->createMCCodeEmitter(*MII, *MCEInstance.LocalCtx));
+TheTarget->createMCCodeEmitter(*MII, *MRI, *MCEInstance.LocalCtx));
return MCEInstance;
}
/// Creating MCStreamer instance.
std::unique_ptr
createStreamer(llvm::raw_pwrite_stream ) const {
-MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *Ctx);
+MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *Ctx);
MCAsmBackend *MAB =
TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions());
std::unique_ptr OW = MAB->createObjectWriter(OS);
diff --git a/bolt/lib/Core/BinaryContext.cpp b/bolt/lib/Core/BinaryContext.cpp
index 36745580217ed..a197e59719adc 100644
--- a/bolt/lib/Core/BinaryContext.cpp
+++ b/bolt/lib/Core/BinaryContext.cpp
@@ -223,7 +223,7 @@ BinaryContext::createBinaryContext(const ObjectFile *File,
bool IsPIC,
InstructionPrinter->setPrintImmHex(true);
std::unique_ptr MCE(
- TheTarget->createMCCodeEmitter(*MII, *Ctx));
+ TheTarget->createMCCodeEmitter(*MII, *MRI, *Ctx));
// Make sure we don't miss any output on core dumps.
outs().SetUnbuffered();
diff --git a/clang/tools/driver/cc1as_main.cpp
b/clang/tools/driver/cc1as_main.cpp
index 26b4eb27a290a..6459d1534b39e 100644
--- a/clang/tools/driver/cc1as_main.cpp
+++ b/clang/tools/driver/cc1as_main.cpp
@@ -455,7 +455,7 @@ static bool ExecuteAssemblerImpl(AssemblerInvocation ,
std::unique_ptr CE;
if (Opts.ShowEncoding)
- CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
+ CE.reset(TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
std::unique_ptr MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
@@ -475,7 +475,7 @@ static bool ExecuteAssemblerImpl(AssemblerInvocation ,
}
std::unique_ptr CE(
-TheTarget->createMCCodeEmitter(*MCII, Ctx));
+TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx));
std::unique_ptr MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions));
assert(MAB && "Unable to create asm backend!");
diff --git a/llvm/include/llvm/MC/TargetRegistry.h
b/llvm/include/llvm/MC/TargetRegistry.h
index 954f7d69b033d..6f6804aef30c1 100644
--- a/llvm/include/llvm/MC/TargetRegistry.h
+++ b/llvm/include/llvm/MC/TargetRegistry.h
@@ -175,6 +175,7 @@ class Target {
const MCInstrInfo ,
const MCRegisterInfo );
using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo ,
+ const MCRegisterInfo ,
MCContext );
using ELFStreamerCtorTy =
MCStreamer *(*)(const Triple , MCContext ,
@@ -505,10 +506,11 @@ class Target {
/// createMCCodeEmitter - Create a target specific code emitter.
MCCodeEmitter *createMCCodeEmitter(const
[clang] 62b59c5 - [NFC][clang] Fix comments.
Author: Shao-Ce SUN
Date: 2022-01-05T14:49:03+08:00
New Revision: 62b59c59a6d9bab0c45808dcb96cf09047b9cba1
URL:
https://github.com/llvm/llvm-project/commit/62b59c59a6d9bab0c45808dcb96cf09047b9cba1
DIFF:
https://github.com/llvm/llvm-project/commit/62b59c59a6d9bab0c45808dcb96cf09047b9cba1.diff
LOG: [NFC][clang] Fix comments.
Added:
Modified:
clang/test/Parser/extra-semi-resulting-in-nullstmt.cpp
Removed:
diff --git a/clang/test/Parser/extra-semi-resulting-in-nullstmt.cpp
b/clang/test/Parser/extra-semi-resulting-in-nullstmt.cpp
index a09d942c5892..2a10392c4c05 100644
--- a/clang/test/Parser/extra-semi-resulting-in-nullstmt.cpp
+++ b/clang/test/Parser/extra-semi-resulting-in-nullstmt.cpp
@@ -17,13 +17,13 @@ void test() {
;
// This removal of extra semi also consumes all the comments.
- // clang-format: off
+ // clang-format off
;;;
- // clang-format: on
+ // clang-format on
- // clang-format: off
+ // clang-format off
;NULLMACRO(ZZ);
- // clang-format: on
+ // clang-format on
{}; // expected-warning {{empty expression statement has no effect; remove
unnecessary ';' to silence this warning}}
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[clang] ec501f1 - [clang][CodeGen] Remove the signed version of createExpression
Author: Shao-Ce SUN
Date: 2021-12-27T14:16:08+08:00
New Revision: ec501f15a8b8ace2b283732740d6d65d40d82e09
URL:
https://github.com/llvm/llvm-project/commit/ec501f15a8b8ace2b283732740d6d65d40d82e09
DIFF:
https://github.com/llvm/llvm-project/commit/ec501f15a8b8ace2b283732740d6d65d40d82e09.diff
LOG: [clang][CodeGen] Remove the signed version of createExpression
Fix a TODO. Remove the callers of this signed version and delete.
Reviewed By: CodaFi
Differential Revision: https://reviews.llvm.org/D116014
Added:
Modified:
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CGDebugInfo.h
llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c
llvm/include/llvm-c/DebugInfo.h
llvm/include/llvm/IR/DIBuilder.h
llvm/lib/IR/DIBuilder.cpp
llvm/lib/IR/DebugInfo.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp
b/clang/lib/CodeGen/CGDebugInfo.cpp
index 6e189a61dd206..b976dcb3058e7 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -722,7 +722,7 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType
*BT) {
auto *LowerBound =
llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(
llvm::Type::getInt64Ty(CGM.getLLVMContext()), 0));
- SmallVector Expr(
+ SmallVector Expr(
{llvm::dwarf::DW_OP_constu, NumElemsPerVG, llvm::dwarf::DW_OP_bregx,
/* AArch64::VG */ 46, 0, llvm::dwarf::DW_OP_mul,
llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
@@ -768,7 +768,7 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType
*BT) {
}
// Element count = (VLENB / SEW) x LMUL
- SmallVector Expr(
+ SmallVector Expr(
// The DW_OP_bregx operation has two operands: a register which is
// specified by an unsigned LEB128 number, followed by a signed
LEB128
// offset.
@@ -4325,7 +4325,7 @@ void CGDebugInfo::CreateLexicalBlock(SourceLocation Loc) {
}
void CGDebugInfo::AppendAddressSpaceXDeref(
-unsigned AddressSpace, SmallVectorImpl ) const {
+unsigned AddressSpace, SmallVectorImpl ) const {
Optional DWARFAddressSpace =
CGM.getTarget().getDWARFAddressSpace(AddressSpace);
if (!DWARFAddressSpace)
@@ -4494,7 +4494,7 @@ llvm::DILocalVariable *CGDebugInfo::EmitDeclare(const
VarDecl *VD,
Line = getLineNumber(VD->getLocation());
Column = getColumnNumber(VD->getLocation());
}
- SmallVector Expr;
+ SmallVector Expr;
llvm::DINode::DIFlags Flags = llvm::DINode::FlagZero;
if (VD->isImplicit())
Flags |= llvm::DINode::FlagArtificial;
@@ -4720,7 +4720,7 @@ void CGDebugInfo::EmitDeclareOfBlockDeclRefVariable(
target.getStructLayout(blockInfo.StructureType)
->getElementOffset(blockInfo.getCapture(VD).getIndex()));
- SmallVector addr;
+ SmallVector addr;
addr.push_back(llvm::dwarf::DW_OP_deref);
addr.push_back(llvm::dwarf::DW_OP_plus_uconst);
addr.push_back(offset.getQuantity());
@@ -5191,7 +5191,7 @@ void CGDebugInfo::EmitGlobalVariable(llvm::GlobalVariable
*Var,
} else {
auto Align = getDeclAlignIfRequired(D, CGM.getContext());
-SmallVector Expr;
+SmallVector Expr;
unsigned AddressSpace =
CGM.getContext().getTargetAddressSpace(D->getType());
if (CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) {
diff --git a/clang/lib/CodeGen/CGDebugInfo.h b/clang/lib/CodeGen/CGDebugInfo.h
index 14ff0eeabd21b..d782bd97f5903 100644
--- a/clang/lib/CodeGen/CGDebugInfo.h
+++ b/clang/lib/CodeGen/CGDebugInfo.h
@@ -363,7 +363,7 @@ class CGDebugInfo {
/// Extended dereferencing mechanism is has the following format:
/// DW_OP_constu DW_OP_swap DW_OP_xderef
void AppendAddressSpaceXDeref(unsigned AddressSpace,
-SmallVectorImpl ) const;
+SmallVectorImpl ) const;
/// A helper function to collect debug info for the default elements of a
/// block.
diff --git a/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c
b/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c
index 794fa6b06ab69..81f4748c5518a 100644
--- a/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c
+++ b/llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c
@@ -865,7 +865,7 @@ value llvm_instr_set_debug_loc(LLVMValueRef Inst,
LLVMMetadataRef Loc) {
LLVMMetadataRef llvm_dibuild_create_constant_value_expression(value Builder,
value Value) {
return LLVMDIBuilderCreateConstantValueExpression(DIBuilder_val(Builder),
-(int64_t)Int_val(Value));
+(uint64_t)Int_val(Value));
}
LLVMMetadataRef llvm_dibuild_create_global_variable_expression_native(
diff --git a/llvm/include/llvm-c/DebugInfo.h b/llvm/include/llvm-c/DebugInfo.h
index
[clang] 5c3d718 - [RISCV] Support Zfhmin extension
Author: Shao-Ce SUN
Date: 2021-11-06T01:41:02+08:00
New Revision: 5c3d7184b43575e4cbf1da2fa6ba88485eaca4e3
URL:
https://github.com/llvm/llvm-project/commit/5c3d7184b43575e4cbf1da2fa6ba88485eaca4e3
DIFF:
https://github.com/llvm/llvm-project/commit/5c3d7184b43575e4cbf1da2fa6ba88485eaca4e3.diff
LOG: [RISCV] Support Zfhmin extension
According to RISC-V Unprivileged ISA 15.6.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D111866
Added:
llvm/test/MC/RISCV/rv32zfhmin-invalid.s
llvm/test/MC/RISCV/rv32zfhmin-valid.s
Modified:
clang/test/Driver/riscv-arch.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 4634cb7e9c9fb..bbbc0f3ded78a 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -426,6 +426,15 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFH %s
// RV32-EXPERIMENTAL-ZFH: "-target-feature" "+experimental-zfh"
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izfhmin -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-ZFHMIN-NOFLAG %s
+// RV32-EXPERIMENTAL-ZFHMIN-NOFLAG: error: invalid arch name 'rv32izfhmin'
+// RV32-EXPERIMENTAL-ZFHMIN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izfhmin0p1
-menable-experimental-extensions -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZFHMIN
%s
+// RV32-EXPERIMENTAL-ZFHMIN: "-target-feature" "+experimental-zfhmin"
+
// RUN: %clang -target riscv32-unknown-elf -march=rv32izvamo -### %s -c 2>&1 |
\
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVAMO-NOFLAG %s
// RV32-EXPERIMENTAL-ZVAMO-NOFLAG: error: invalid arch name 'rv32izvamo'
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 8bbfc757f0755..8e984002f90d2 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -64,6 +64,7 @@ static const RISCVSupportedExtension
SupportedExperimentalExtensions[] = {
{"zvamo", RISCVExtensionVersion{0, 10}},
{"zvlsseg", RISCVExtensionVersion{0, 10}},
+{"zfhmin", RISCVExtensionVersion{0, 1}},
{"zfh", RISCVExtensionVersion{0, 1}},
};
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 48dbcfee886c2..772a4f8ecd535 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -41,10 +41,18 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
+def FeatureStdExtZfhmin
+: SubtargetFeature<"experimental-zfhmin", "HasStdExtZfhmin", "true",
+ "'Zfhmin' (Half-Precision Floating-Point Minimal)",
+ [FeatureStdExtF]>;
+def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
+ AssemblerPredicate<(all_of FeatureStdExtZfhmin),
+ "'Zfhmin' (Half-Precision Floating-Point
Minimal)">;
+
def FeatureStdExtZfh
: SubtargetFeature<"experimental-zfh", "HasStdExtZfh", "true",
"'Zfh' (Half-Precision Floating-Point)",
- [FeatureStdExtF]>;
+ [FeatureStdExtZfhmin, FeatureStdExtF]>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bcbca9d2fa5a8..193c5b4c91db3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1166,7 +1166,7 @@ bool RISCVTargetLowering::shouldSinkOperands(
bool RISCVTargetLowering::isFPImmLegal(const APFloat , EVT VT,
bool ForCodeSize) const {
- if (VT == MVT::f16 && !Subtarget.hasStdExtZfh())
+ if (VT == MVT::f16 && !Subtarget.hasStdExtZfhmin())
return false;
if (VT == MVT::f32 && !Subtarget.hasStdExtF())
return false;
@@ -1186,9 +1186,9 @@ bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT)
const {
MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext ,
CallingConv::ID CC,
EVT VT) const {
- // Use f32 to pass f16 if it is legal and Zfh is not
[clang] d4f25d0 - [RISCV] add Half-precision test for vle/vse
Author: Shao-Ce Sun
Date: 2021-09-14T08:55:22+08:00
New Revision: d4f25d0046fc9d1a42d9974e75cfba14ff3d535e
URL:
https://github.com/llvm/llvm-project/commit/d4f25d0046fc9d1a42d9974e75cfba14ff3d535e
DIFF:
https://github.com/llvm/llvm-project/commit/d4f25d0046fc9d1a42d9974e75cfba14ff3d535e.diff
LOG: [RISCV] add Half-precision test for vle/vse
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D109681
Added:
Modified:
clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
Removed:
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
index 3e9c6c0e3412c..9da035126fd99 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
@@ -1195,3 +1195,63 @@ vfloat16m4_t test_vle16_v_f16m4(const _Float16 *base,
size_t vl) {
vfloat16m8_t test_vle16_v_f16m8(const _Float16 *base, size_t vl) {
return vle16_v_f16m8(base, vl);
}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16mf4_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call
@llvm.riscv.vle.mask.nxv1f16.i64( [[MASKEDOFF:%.*]], * [[TMP0]], [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret [[TMP1]]
+//
+vfloat16mf4_t test_vle16_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
const _Float16 *base, size_t vl) {
+ return vle16_v_f16mf4_m (mask, maskedoff, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16mf2_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call
@llvm.riscv.vle.mask.nxv2f16.i64( [[MASKEDOFF:%.*]], * [[TMP0]], [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret [[TMP1]]
+//
+vfloat16mf2_t test_vle16_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
const _Float16 *base, size_t vl) {
+ return vle16_v_f16mf2_m (mask, maskedoff, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m1_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call
@llvm.riscv.vle.mask.nxv4f16.i64( [[MASKEDOFF:%.*]], * [[TMP0]], [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret [[TMP1]]
+//
+vfloat16m1_t test_vle16_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff,
const _Float16 *base, size_t vl) {
+ return vle16_v_f16m1_m (mask, maskedoff, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m2_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call
@llvm.riscv.vle.mask.nxv8f16.i64( [[MASKEDOFF:%.*]], * [[TMP0]], [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret [[TMP1]]
+//
+vfloat16m2_t test_vle16_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff,
const _Float16 *base, size_t vl) {
+ return vle16_v_f16m2_m (mask, maskedoff, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m4_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call
@llvm.riscv.vle.mask.nxv16f16.i64( [[MASKEDOFF:%.*]],
* [[TMP0]], [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret [[TMP1]]
+//
+vfloat16m4_t test_vle16_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff,
const _Float16 *base, size_t vl) {
+ return vle16_v_f16m4_m (mask, maskedoff, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m8_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call
@llvm.riscv.vle.mask.nxv32f16.i64( [[MASKEDOFF:%.*]],
* [[TMP0]], [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret [[TMP1]]
+//
+vfloat16m8_t test_vle16_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff,
const _Float16 *base, size_t vl) {
+ return vle16_v_f16m8_m (mask, maskedoff, base, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
index cdf62055c2b41..23ad316fb90ed 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
@@ -1195,3 +1195,63 @@ void test_vse16_v_f16m4(_Float16 *base, vfloat16m4_t
value, size_t vl) {
void test_vse16_v_f16m8(_Float16 *base, vfloat16m8_t value, size_t vl) {
return vse16_v_f16m8(base, value, vl);
}
+
+// CHECK-RV64-LABEL: @test_vse16_v_f16mf4_m(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:call void @llvm.riscv.vse.mask.nxv1f16.i64( [[VALUE:%.*]], * [[TMP0]],
[[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vse16_v_f16mf4_m (vbool64_t mask, _Float16 *base, vfloat16mf4_t
value, size_t
[clang] ad14ccc - [clang][flang] Improve the consistency of the code-base
Author: Shao-Ce Sun
Date: 2021-02-25T21:25:43+08:00
New Revision: ad14ccc8c22e1480db7bfc1a176311e6f572c588
URL:
https://github.com/llvm/llvm-project/commit/ad14ccc8c22e1480db7bfc1a176311e6f572c588
DIFF:
https://github.com/llvm/llvm-project/commit/ad14ccc8c22e1480db7bfc1a176311e6f572c588.diff
LOG: [clang][flang] Improve the consistency of the code-base
In clang:
Replace argc_ with Argc
Replace argv_ with Argv
Replace argv with Args
In flang:
Replace argc_ with argc
Replace argv_ with argv
Replace argv with args
Reviewed By: awarzynski, aganea
Differential Revision: https://reviews.llvm.org/D97138
Added:
Modified:
clang/tools/driver/driver.cpp
flang/tools/flang-driver/driver.cpp
Removed:
diff --git a/clang/tools/driver/driver.cpp b/clang/tools/driver/driver.cpp
index f67af6790fff..a13c1c4a3834 100644
--- a/clang/tools/driver/driver.cpp
+++ b/clang/tools/driver/driver.cpp
@@ -340,25 +340,25 @@ static int ExecuteCC1Tool(SmallVectorImpl
) {
return 1;
}
-int main(int argc_, const char **argv_) {
+int main(int Argc, const char **Argv) {
noteBottomOfStack();
- llvm::InitLLVM X(argc_, argv_);
+ llvm::InitLLVM X(Argc, Argv);
llvm::setBugReportMsg("PLEASE submit a bug report to " BUG_REPORT_URL
" and include the crash backtrace, preprocessed "
"source, and associated run script.\n");
- SmallVector argv(argv_, argv_ + argc_);
+ SmallVector Args(Argv, Argv + Argc);
if (llvm::sys::Process::FixupStandardFileDescriptors())
return 1;
llvm::InitializeAllTargets();
- auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(argv[0]);
+ auto TargetAndMode = ToolChain::getTargetAndModeFromProgramName(Args[0]);
llvm::BumpPtrAllocator A;
llvm::StringSaver Saver(A);
// Parse response files using the GNU syntax, unless we're in CL mode. There
- // are two ways to put clang in CL compatibility mode: argv[0] is either
+ // are two ways to put clang in CL compatibility mode: Args[0] is either
// clang-cl or cl, or --driver-mode=cl is on the command line. The normal
// command line parsing can't happen until after response file parsing, so we
// have to manually search for a --driver-mode=cl argument the hard way.
@@ -366,20 +366,20 @@ int main(int argc_, const char **argv_) {
// response files written by clang will tokenize the same way in either mode.
bool ClangCLMode = false;
if (StringRef(TargetAndMode.DriverMode).equals("--driver-mode=cl") ||
- llvm::find_if(argv, [](const char *F) {
+ llvm::find_if(Args, [](const char *F) {
return F && strcmp(F, "--driver-mode=cl") == 0;
- }) != argv.end()) {
+ }) != Args.end()) {
ClangCLMode = true;
}
enum { Default, POSIX, Windows } RSPQuoting = Default;
- for (const char *F : argv) {
+ for (const char *F : Args) {
if (strcmp(F, "--rsp-quoting=posix") == 0)
RSPQuoting = POSIX;
else if (strcmp(F, "--rsp-quoting=windows") == 0)
RSPQuoting = Windows;
}
- // Determines whether we want nullptr markers in argv to indicate response
+ // Determines whether we want nullptr markers in Args to indicate response
// files end-of-lines. We only use this for the /LINK driver argument with
// clang-cl.exe on Windows.
bool MarkEOLs = ClangCLMode;
@@ -390,31 +390,31 @@ int main(int argc_, const char **argv_) {
else
Tokenizer = ::cl::TokenizeGNUCommandLine;
- if (MarkEOLs && argv.size() > 1 && StringRef(argv[1]).startswith("-cc1"))
+ if (MarkEOLs && Args.size() > 1 && StringRef(Args[1]).startswith("-cc1"))
MarkEOLs = false;
- llvm::cl::ExpandResponseFiles(Saver, Tokenizer, argv, MarkEOLs);
+ llvm::cl::ExpandResponseFiles(Saver, Tokenizer, Args, MarkEOLs);
// Handle -cc1 integrated tools, even if -cc1 was expanded from a response
// file.
- auto FirstArg = std::find_if(argv.begin() + 1, argv.end(),
+ auto FirstArg = std::find_if(Args.begin() + 1, Args.end(),
[](const char *A) { return A != nullptr; });
- if (FirstArg != argv.end() && StringRef(*FirstArg).startswith("-cc1")) {
+ if (FirstArg != Args.end() && StringRef(*FirstArg).startswith("-cc1")) {
// If -cc1 came from a response file, remove the EOL sentinels.
if (MarkEOLs) {
- auto newEnd = std::remove(argv.begin(), argv.end(), nullptr);
- argv.resize(newEnd - argv.begin());
+ auto newEnd = std::remove(Args.begin(), Args.end(), nullptr);
+ Args.resize(newEnd - Args.begin());
}
-return ExecuteCC1Tool(argv);
+return ExecuteCC1Tool(Args);
}
// Handle options that need handling before the real command line parsing in
// Driver::BuildCompilation()
bool CanonicalPrefixes = true;
- for (int i = 1, size = argv.size(); i < size; ++i) {
+ for (int i = 1, size = Args.size(); i < size; ++i) {
// Skip end-of-line response file
