[clang] 01b9e61 - [Clang][Codegen] Truncate initializers of union bitfield members
Author: Tomas Matheson
Date: 2021-01-28T09:19:19Z
New Revision: 01b9e613c28b833327ab4de93d0638a5c8d3514f
URL:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f
DIFF:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f.diff
LOG: [Clang][Codegen] Truncate initializers of union bitfield members
If an initial value is given for a bitfield that does not fit in the
bitfield, the value should be truncated. Constant folding for
expressions did not account for this truncation in the case of union
member functions, despite a warning being emitted. In some contexts,
evaluation of expressions was not enabled unless C++11, ROPI or RWPI
was enabled.
Differential Revision: https://reviews.llvm.org/D93101
Added:
Modified:
clang/lib/AST/ExprConstant.cpp
clang/test/CodeGenCXX/bitfield-layout.cpp
Removed:
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index c1973720e49a..0f0c33b0ac85 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -9798,7 +9798,14 @@ bool RecordExprEvaluator::VisitInitListExpr(const
InitListExpr *E) {
ThisOverrideRAII ThisOverride(*Info.CurrentCall, &This,
isa(InitExpr));
-return EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr);
+if (EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr)) {
+ if (Field->isBitField())
+return truncateBitfieldValue(Info, InitExpr, Result.getUnionValue(),
+ Field);
+ return true;
+}
+
+return false;
}
if (!Result.hasValue())
diff --git a/clang/test/CodeGenCXX/bitfield-layout.cpp
b/clang/test/CodeGenCXX/bitfield-layout.cpp
index 49b196253f3c..79dbf9c691c4 100644
--- a/clang/test/CodeGenCXX/bitfield-layout.cpp
+++ b/clang/test/CodeGenCXX/bitfield-layout.cpp
@@ -2,6 +2,7 @@
// RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=aarch64_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=thumbv7_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
+// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -emit-llvm -o - -O3
-std=c++11 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s
// CHECK-LP64: %union.Test1 = type { i32, [4 x i8] }
union Test1 {
@@ -84,3 +85,68 @@ int test_init() {
// CHECK: ret i32 0
return 0;
}
+
+extern "C" {
+int test_trunc_int() {
+ union {
+int i : 4; // truncated to 0b == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_int()
+// CHECK: ret i32 -1
+
+int test_trunc_three_bits() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_three_bits()
+// CHECK: ret i32 -1
+
+int test_trunc_1() {
+ union {
+int i : 1; // truncated to 0b1 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_1()
+// CHECK: ret i32 -1
+
+int test_trunc_zero() {
+ union {
+int i : 4; // truncated to 0b == 0
+ } const U = {80}; // 0b0101
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_zero()
+// CHECK: ret i32 0
+
+int test_constexpr() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_constexpr()
+// CHECK: ret i32 -1
+
+int test_notrunc() {
+ union {
+int i : 12; // not truncated
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_notrunc()
+// CHECK: ret i32 15
+
+long long test_trunc_long_long() {
+ union {
+long long i : 14; // truncated to 0b0001001101 ==
+ } const U = {0b010001001101};
+ return U.i;
+}
+// CHECK: define dso_local i64 @test_trunc_long_long()
+// CHECK: ret i64 3917
+}
___
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[clang] 01b9e61 - [Clang][Codegen] Truncate initializers of union bitfield members
Author: Tomas Matheson
Date: 2021-01-28T09:19:19Z
New Revision: 01b9e613c28b833327ab4de93d0638a5c8d3514f
URL:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f
DIFF:
https://github.com/llvm/llvm-project/commit/01b9e613c28b833327ab4de93d0638a5c8d3514f.diff
LOG: [Clang][Codegen] Truncate initializers of union bitfield members
If an initial value is given for a bitfield that does not fit in the
bitfield, the value should be truncated. Constant folding for
expressions did not account for this truncation in the case of union
member functions, despite a warning being emitted. In some contexts,
evaluation of expressions was not enabled unless C++11, ROPI or RWPI
was enabled.
Differential Revision: https://reviews.llvm.org/D93101
Added:
Modified:
clang/lib/AST/ExprConstant.cpp
clang/test/CodeGenCXX/bitfield-layout.cpp
Removed:
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index c1973720e49a..0f0c33b0ac85 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -9798,7 +9798,14 @@ bool RecordExprEvaluator::VisitInitListExpr(const
InitListExpr *E) {
ThisOverrideRAII ThisOverride(*Info.CurrentCall, &This,
isa(InitExpr));
-return EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr);
+if (EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr)) {
+ if (Field->isBitField())
+return truncateBitfieldValue(Info, InitExpr, Result.getUnionValue(),
+ Field);
+ return true;
+}
+
+return false;
}
if (!Result.hasValue())
diff --git a/clang/test/CodeGenCXX/bitfield-layout.cpp
b/clang/test/CodeGenCXX/bitfield-layout.cpp
index 49b196253f3c..79dbf9c691c4 100644
--- a/clang/test/CodeGenCXX/bitfield-layout.cpp
+++ b/clang/test/CodeGenCXX/bitfield-layout.cpp
@@ -2,6 +2,7 @@
// RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=aarch64_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
// RUN: %clang_cc1 %s -triple=thumbv7_be-none-eabi -emit-llvm -o - -O3 |
FileCheck %s
+// RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -emit-llvm -o - -O3
-std=c++11 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s
// CHECK-LP64: %union.Test1 = type { i32, [4 x i8] }
union Test1 {
@@ -84,3 +85,68 @@ int test_init() {
// CHECK: ret i32 0
return 0;
}
+
+extern "C" {
+int test_trunc_int() {
+ union {
+int i : 4; // truncated to 0b == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_int()
+// CHECK: ret i32 -1
+
+int test_trunc_three_bits() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_three_bits()
+// CHECK: ret i32 -1
+
+int test_trunc_1() {
+ union {
+int i : 1; // truncated to 0b1 == -1
+ } const U = {15}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_1()
+// CHECK: ret i32 -1
+
+int test_trunc_zero() {
+ union {
+int i : 4; // truncated to 0b == 0
+ } const U = {80}; // 0b0101
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_trunc_zero()
+// CHECK: ret i32 0
+
+int test_constexpr() {
+ union {
+int i : 3; // truncated to 0b111 == -1
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_constexpr()
+// CHECK: ret i32 -1
+
+int test_notrunc() {
+ union {
+int i : 12; // not truncated
+ } const U = {1 + 2 + 4 + 8}; // 0b
+ return U.i;
+}
+// CHECK: define dso_local i32 @test_notrunc()
+// CHECK: ret i32 15
+
+long long test_trunc_long_long() {
+ union {
+long long i : 14; // truncated to 0b0001001101 ==
+ } const U = {0b010001001101};
+ return U.i;
+}
+// CHECK: define dso_local i64 @test_trunc_long_long()
+// CHECK: ret i64 3917
+}
___
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[clang] b14a6f0 - [ARM][MVE] vcreateq lane ordering for big endian
Author: Tomas Matheson
Date: 2021-04-30T13:48:05+01:00
New Revision: b14a6f06cc8763830a25023edf5b9ccee18e426a
URL:
https://github.com/llvm/llvm-project/commit/b14a6f06cc8763830a25023edf5b9ccee18e426a
DIFF:
https://github.com/llvm/llvm-project/commit/b14a6f06cc8763830a25023edf5b9ccee18e426a.diff
LOG: [ARM][MVE] vcreateq lane ordering for big endian
Use of bitcast resulted in lanes being swapped for vcreateq with big
endian. Fix this by using vreinterpret. No code change for little
endian. Adds IR lit test.
Differential Revision: https://reviews.llvm.org/D101606
Added:
Modified:
clang/include/clang/Basic/arm_mve.td
clang/test/CodeGen/arm-mve-intrinsics/admin.c
Removed:
diff --git a/clang/include/clang/Basic/arm_mve.td
b/clang/include/clang/Basic/arm_mve.td
index 8106f9a5a9def..55c2fbe7f0217 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -1543,7 +1543,7 @@ foreach desttype = T.All in {
let params = T.All in {
let pnt = PNT_None in {
def vcreateq: Intrinsic), $a, 0),
+(vreinterpret (ielt_const (ielt_const (undef VecOf), $a, 0),
$b, 1), Vector)>;
def vuninitializedq: Intrinsic;
}
diff --git a/clang/test/CodeGen/arm-mve-intrinsics/admin.c
b/clang/test/CodeGen/arm-mve-intrinsics/admin.c
index 137231557011a..6c81cda00bac8 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/admin.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/admin.c
@@ -1,51 +1,82 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse |
FileCheck %s
-// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa
-early-cse | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse |
FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa
-early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse |
FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa
-early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+
#include
-// CHECK-LABEL: @test_vcreateq_f16(
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]],
i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64
[[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
-// CHECK-NEXT:ret <8 x half> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f16(
+// CHECK-LE-NEXT: entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64
[[A:%.*]], i64 0
+// CHECK-LE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64
[[B:%.*]], i64 1
+// CHECK-LE-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
+// CHECK-LE-NEXT:ret <8 x half> [[TMP2]]
+//
+// CHECK-BE-LABEL: @test_vcreateq_f16(
+// CHECK-BE-NEXT: entry:
+// CHECK-BE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64
[[A:%.*]], i64 0
+// CHECK-BE-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64
[[B:%.*]], i64 1
+// CHECK-BE-NEXT:[[TMP2:%.*]] = call <8 x half>
@llvm.arm.mve.vreinterpretq.v8f16.v2i64(<2 x i64> [[TMP1]])
+// CHECK-BE-NEXT:ret <8 x half> [[TMP2]]
//
float16x8_t test_vcreateq_f16(uint64_t a, uint64_t b)
{
return vcreateq_f16(a, b);
}
-// CHECK-LABEL: @test_vcreateq_f32(
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]],
i64 0
-// CHECK-NEXT:[[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64
[[B:%.*]], i64 1
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
-// CHECK-NEXT:ret <4 x float> [[TMP2]]
+// CHECK-LE-LABEL: @test_vcreateq_f32(
+// CHECK-LE-NEXT: entry:
+// CHECK-LE-NEXT:[[TMP0:%.*]] = insertelement <2 x i64> undef, i64
[flang] [clang] [mlir] [clang-tools-extra] [libcxx] [libc] [compiler-rt] [llvm] [AsmWriter] Ensure getMnemonic doesn't return invalid pointers (PR #75783)
https://github.com/tmatheson-arm approved this pull request. LGMT, surprised this didn't blow up earlier. https://github.com/llvm/llvm-project/pull/75783 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm created
https://github.com/llvm/llvm-project/pull/75947
- [AArch64] add missing test case for v9.4-A
- [AArch64] Add FEAT_PAuthLR assembler support
- [AArch64] Codegen support for FEAT_PAuthLR
>From 3b1722f0cf3c0dd80ca5736724c77c36608b112b Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From df263e1d4aab1f099cdedfdc37670eb17c65696c Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 9 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 517 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index d1dbced2466eae..f727da0fdb765d 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,8 +622,13 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
- "Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+ "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
//===--===//
// Architectures.
@@ -810,7 +815,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 690ac0dcda6212..cb63d8726744d4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class Clea
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From 1d4208d53830e0ef8dadad9be12e7ef2b53c6190 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 516 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[lldb] [clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From d3201659d87260acaf1d20a96705e290caf21693 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From 1d4208d53830e0ef8dadad9be12e7ef2b53c6190 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 516 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From a6039367acca5de4c925925c1cefc56097ae496a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From b84addbf39d1734f1b860dba1e9a6acab3558ae7 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 28
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 516 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From a6039367acca5de4c925925c1cefc56097ae496a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From a5baa372f55196fe6ac0fe7979fbd736ba82f411 Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 7 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 29
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 517 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index c600bcaab2b3ea..95e171109b4eb0 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,6 +622,11 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
//===--===//
// Architectures.
//
@@ -807,7 +812,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 68e87f491a09e4..92bf9f4ec2a21b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string asm>
+ : I<(outs), (ins), asm, "", "", []>,
+Sched<[WriteI, ReadI]> {
+ let Inst{31} = 0b1; // sf
+ let Inst{30} = 0b1;
+ let Inst{29} = 0b0; // S
+ let Inst{28-21} = 0b1101011
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/75947
>From 29eb3db45ac1782d6cdcff106bd6088f06bbc680 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 2 Feb 2023 13:19:05 +
Subject: [PATCH 1/3] [AArch64] add missing test case for v9.4-A
---
clang/test/Preprocessor/aarch64-target-features.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index db89aa7b608ad5..b3da54162da04b 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -600,6 +600,7 @@
// RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
+// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - |
FileCheck
--check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s
// CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1
// CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1
>From 6db8387da6aa6ad533559ee147e01b990c27deee Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Wed, 1 Feb 2023 18:16:07 +
Subject: [PATCH 2/3] [AArch64] Add FEAT_PAuthLR assembler support
Add assembly/disassembly support for the new PAuthLR instructions
introduced in Armv9.5-A:
- AUTIASPPC/AUTIBSPPC
- PACIASPPC/PACIBSPPC
- PACNBIASPPC/PACNBIBSPPC
- RETAASPPC/RETABSPPC
- PACM
Documentation for these instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/
---
llvm/lib/Target/AArch64/AArch64.td| 9 +-
.../lib/Target/AArch64/AArch64InstrFormats.td | 74 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp| 28
.../Disassembler/AArch64Disassembler.cpp | 18 +++
.../MCTargetDesc/AArch64AsmBackend.cpp| 14 ++
.../MCTargetDesc/AArch64ELFObjectWriter.cpp | 4 +
.../AArch64/MCTargetDesc/AArch64FixupKinds.h | 5 +
.../MCTargetDesc/AArch64MCCodeEmitter.cpp | 29
.../MC/AArch64/armv9.5a-pauthlr-diagnostics.s | 57 +++
llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s | 12 ++
llvm/test/MC/AArch64/armv9.5a-pauthlr.s | 151 ++
.../Disassembler/AArch64/armv9.5a-pauthlr.txt | 78 +
15 files changed, 518 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-diagnostics.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr-reloc.s
create mode 100644 llvm/test/MC/AArch64/armv9.5a-pauthlr.s
create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.5a-pauthlr.txt
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index db92a94e40e4b5..97e92a57a7ff4b 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -622,8 +622,13 @@ def FeatureLdpAlignedOnly :
SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only",
"HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to
2 * element_size">;
+// AArch64 2023 Architecture Extensions (v9.5-A)
+
def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
- "Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+"Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+
+def FeaturePAuthLR : SubtargetFeature<"pauth-lr", "HasPAuthLR",
+"true", "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
//===--===//
// Architectures.
@@ -810,7 +815,7 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-let F = [HasPAuth] in
+let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 690ac0dcda6212..cb63d8726744d4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2368,6 +2368,80 @@ class ClearAuth data, string asm>
let Inst{4-0} = Rd;
}
+// v9.5-A FEAT_PAuth_LR
+
+class SignAuthFixedRegs opcode2, bits<6> opcode, string a
[clang] 92dc23c - [AArch64] add missing test case for v9.4-A
Author: Tomas Matheson Date: 2023-12-21T14:18:33Z New Revision: 92dc23c0e054183e8adf41aad2a2609cefc392c0 URL: https://github.com/llvm/llvm-project/commit/92dc23c0e054183e8adf41aad2a2609cefc392c0 DIFF: https://github.com/llvm/llvm-project/commit/92dc23c0e054183e8adf41aad2a2609cefc392c0.diff LOG: [AArch64] add missing test case for v9.4-A Added: Modified: clang/test/Preprocessor/aarch64-target-features.c Removed: diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index db89aa7b608ad5..b3da54162da04b 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -600,6 +600,7 @@ // RUN: %clang -target aarch64-none-elf -march=armv9.1-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // RUN: %clang -target aarch64-none-elf -march=armv9.2-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // RUN: %clang -target aarch64-none-elf -march=armv9.3-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s +// RUN: %clang -target aarch64-none-elf -march=armv9.4-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // RUN: %clang -target aarch64-none-elf -march=armv9.5-a -x c -E -dM %s -o - | FileCheck --check-prefixes=CHECK-V81-OR-LATER,CHECK-V83-OR-LATER,CHECK-V85-OR-LATER %s // CHECK-V81-OR-LATER: __ARM_FEATURE_ATOMICS 1 // CHECK-V85-OR-LATER: __ARM_FEATURE_BTI 1 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 5992ce9 - [AArch64] Codegen support for FEAT_PAuthLR
Author: Tomas Matheson Date: 2023-12-21T14:18:33Z New Revision: 5992ce90b8c0fac06436c3c86621fbf6d5398ee5 URL: https://github.com/llvm/llvm-project/commit/5992ce90b8c0fac06436c3c86621fbf6d5398ee5 DIFF: https://github.com/llvm/llvm-project/commit/5992ce90b8c0fac06436c3c86621fbf6d5398ee5.diff LOG: [AArch64] Codegen support for FEAT_PAuthLR - Adds a new +pc option to -mbranch-protection that will enable the use of PC as a diversifier in PAC branch protection code. - When +pauth-lr is enabled (-march=armv9.5a+pauth-lr) in combination with -mbranch-protection=pac-ret+pc, the new 9.5-a instructions (pacibsppc, retaasppc, etc) are used. Documentation for the relevant instructions can be found here: https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/ Co-authored-by: Lucas Prates Added: clang/test/Driver/aarch64-pauth-lr.c llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll Modified: clang/include/clang/Basic/LangOptions.def clang/include/clang/Basic/TargetInfo.h clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/AArch64.cpp clang/lib/Basic/Targets/ARM.cpp clang/lib/CodeGen/CodeGenModule.cpp clang/lib/CodeGen/Targets/AArch64.cpp clang/lib/Driver/ToolChains/Clang.cpp clang/test/CodeGen/aarch64-branch-protection-attr.c clang/test/Driver/aarch64-v95a.c llvm/include/llvm/TargetParser/AArch64TargetParser.h llvm/include/llvm/TargetParser/ARMTargetParserCommon.h llvm/lib/Target/AArch64/AArch64InstrInfo.cpp llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h llvm/lib/Target/AArch64/AArch64PointerAuth.cpp llvm/lib/TargetParser/ARMTargetParserCommon.cpp llvm/test/CodeGen/AArch64/sign-return-address.ll llvm/unittests/TargetParser/TargetParserTest.cpp Removed: diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 152d9f65f86dbe..21abc346cf17ac 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -456,6 +456,7 @@ ENUM_LANGOPT(SignReturnAddressScope, SignReturnAddressScopeKind, 2, SignReturnAd ENUM_LANGOPT(SignReturnAddressKey, SignReturnAddressKeyKind, 1, SignReturnAddressKeyKind::AKey, "Key used for return address signing") LANGOPT(BranchTargetEnforcement, 1, 0, "Branch-target enforcement enabled") +LANGOPT(BranchProtectionPAuthLR, 1, 0, "Use PC as a diversifier using PAuthLR NOP instructions.") LANGOPT(SpeculativeLoadHardening, 1, 0, "Speculative load hardening enabled") diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index aa0f5023104a1a..ac3c324c6c29c4 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -1372,6 +1372,7 @@ class TargetInfo : public TransferrableTargetInfo, LangOptions::SignReturnAddressKeyKind SignKey = LangOptions::SignReturnAddressKeyKind::AKey; bool BranchTargetEnforcement = false; +bool BranchProtectionPAuthLR = false; }; /// Determine if the Architecture in this TargetInfo supports branch diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 1b02087425b751..965d402af2d7b3 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6999,6 +6999,8 @@ def msign_return_address_key_EQ : Joined<["-"], "msign-return-address-key=">, Values<"a_key,b_key">; def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">, MarshallingInfoFlag>; +def mbranch_protection_pauth_lr : Flag<["-"], "mbranch-protection-pauth-lr">, + MarshallingInfoFlag>; def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">, MarshallingInfoNegativeFlag>; def cfguard_no_checks : Flag<["-"], "cfguard-no-checks">, diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index def16c032c869e..3ee39133fcee72 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -225,6 +225,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef, BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey; BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement; + BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR; return true; } diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index ce7e4d4639ceac..6e1842fc64e505 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -419,6 +419,7 @@ bool ARMTargetInfo::validateBranchProtection(StringRef Spec, StringRef Arch, BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey; BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement; + BPI.BranchProtectionPAuthLR = PBP.BranchProtec
[clang] [llvm] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
tmatheson-arm wrote: Manually merged to avoid squashing the commits: 92dc23c0e054183e8adf41aad2a2609cefc392c0 934b1099cbf14fa3f86a269dff957da8e5fb619f 5992ce90b8c0fac06436c3c86621fbf6d5398ee5 https://github.com/llvm/llvm-project/pull/75947 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Support for 9.5-A PAuthLR (PR #75947)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/75947 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 9f0f558 - Revert "[AArch64] Codegen support for FEAT_PAuthLR"
Author: Tomas Matheson
Date: 2023-12-21T16:25:55Z
New Revision: 9f0f5587426a4ff24b240018cf8bf3acc3c566ae
URL:
https://github.com/llvm/llvm-project/commit/9f0f5587426a4ff24b240018cf8bf3acc3c566ae
DIFF:
https://github.com/llvm/llvm-project/commit/9f0f5587426a4ff24b240018cf8bf3acc3c566ae.diff
LOG: Revert "[AArch64] Codegen support for FEAT_PAuthLR"
This reverts commit 5992ce90b8c0fac06436c3c86621fbf6d5398ee5.
Builtbot failures with expensive checks enabled.
Added:
Modified:
clang/include/clang/Basic/LangOptions.def
clang/include/clang/Basic/TargetInfo.h
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/CodeGen/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/CodeGen/aarch64-branch-protection-attr.c
clang/test/Driver/aarch64-v95a.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/include/llvm/TargetParser/ARMTargetParserCommon.h
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
llvm/lib/TargetParser/ARMTargetParserCommon.cpp
llvm/test/CodeGen/AArch64/sign-return-address.ll
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
clang/test/Driver/aarch64-pauth-lr.c
llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
diff --git a/clang/include/clang/Basic/LangOptions.def
b/clang/include/clang/Basic/LangOptions.def
index 21abc346cf17ac..152d9f65f86dbe 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -456,7 +456,6 @@ ENUM_LANGOPT(SignReturnAddressScope,
SignReturnAddressScopeKind, 2, SignReturnAd
ENUM_LANGOPT(SignReturnAddressKey, SignReturnAddressKeyKind, 1,
SignReturnAddressKeyKind::AKey,
"Key used for return address signing")
LANGOPT(BranchTargetEnforcement, 1, 0, "Branch-target enforcement enabled")
-LANGOPT(BranchProtectionPAuthLR, 1, 0, "Use PC as a diversifier using PAuthLR
NOP instructions.")
LANGOPT(SpeculativeLoadHardening, 1, 0, "Speculative load hardening enabled")
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index ac3c324c6c29c4..aa0f5023104a1a 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1372,7 +1372,6 @@ class TargetInfo : public TransferrableTargetInfo,
LangOptions::SignReturnAddressKeyKind SignKey =
LangOptions::SignReturnAddressKeyKind::AKey;
bool BranchTargetEnforcement = false;
-bool BranchProtectionPAuthLR = false;
};
/// Determine if the Architecture in this TargetInfo supports branch
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 2b93ddf033499c..9678165bfd98e8 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -7000,8 +7000,6 @@ def msign_return_address_key_EQ : Joined<["-"],
"msign-return-address-key=">,
Values<"a_key,b_key">;
def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">,
MarshallingInfoFlag>;
-def mbranch_protection_pauth_lr : Flag<["-"], "mbranch-protection-pauth-lr">,
- MarshallingInfoFlag>;
def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">,
MarshallingInfoNegativeFlag>;
def cfguard_no_checks : Flag<["-"], "cfguard-no-checks">,
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 3ee39133fcee72..def16c032c869e 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -225,7 +225,6 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
- BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 6e1842fc64e505..ce7e4d4639ceac 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -419,7 +419,6 @@ bool ARMTargetInfo::validateBranchProtection(StringRef
Spec, StringRef Arch,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
- BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index d78f2594a23764..b2e173d0d6949e 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1106,9 +1106,6 @@ void CodeGenModule::Release() {
if (LangOpts.BranchTargetEnforcement)
[clang] 7bd1721 - Re-land "[AArch64] Codegen support for FEAT_PAuthLR" (#75947)
Author: Tomas Matheson
Date: 2023-12-21T18:32:55Z
New Revision: 7bd17212ef23a72ea224a037126d33d3e02553fe
URL:
https://github.com/llvm/llvm-project/commit/7bd17212ef23a72ea224a037126d33d3e02553fe
DIFF:
https://github.com/llvm/llvm-project/commit/7bd17212ef23a72ea224a037126d33d3e02553fe.diff
LOG: Re-land "[AArch64] Codegen support for FEAT_PAuthLR" (#75947)
This reverts commit 9f0f5587426a4ff24b240018cf8bf3acc3c566ae.
Fix expensive checks failure by properly marking register def for ADR.
Added:
clang/test/Driver/aarch64-pauth-lr.c
llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
Modified:
clang/include/clang/Basic/LangOptions.def
clang/include/clang/Basic/TargetInfo.h
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/CodeGen/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/CodeGen/aarch64-branch-protection-attr.c
clang/test/Driver/aarch64-v95a.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/include/llvm/TargetParser/ARMTargetParserCommon.h
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
llvm/lib/TargetParser/ARMTargetParserCommon.cpp
llvm/test/CodeGen/AArch64/sign-return-address.ll
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/include/clang/Basic/LangOptions.def
b/clang/include/clang/Basic/LangOptions.def
index 152d9f65f86dbe..21abc346cf17ac 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -456,6 +456,7 @@ ENUM_LANGOPT(SignReturnAddressScope,
SignReturnAddressScopeKind, 2, SignReturnAd
ENUM_LANGOPT(SignReturnAddressKey, SignReturnAddressKeyKind, 1,
SignReturnAddressKeyKind::AKey,
"Key used for return address signing")
LANGOPT(BranchTargetEnforcement, 1, 0, "Branch-target enforcement enabled")
+LANGOPT(BranchProtectionPAuthLR, 1, 0, "Use PC as a diversifier using PAuthLR
NOP instructions.")
LANGOPT(SpeculativeLoadHardening, 1, 0, "Speculative load hardening enabled")
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index aa0f5023104a1a..ac3c324c6c29c4 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1372,6 +1372,7 @@ class TargetInfo : public TransferrableTargetInfo,
LangOptions::SignReturnAddressKeyKind SignKey =
LangOptions::SignReturnAddressKeyKind::AKey;
bool BranchTargetEnforcement = false;
+bool BranchProtectionPAuthLR = false;
};
/// Determine if the Architecture in this TargetInfo supports branch
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 9678165bfd98e8..2b93ddf033499c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -7000,6 +7000,8 @@ def msign_return_address_key_EQ : Joined<["-"],
"msign-return-address-key=">,
Values<"a_key,b_key">;
def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">,
MarshallingInfoFlag>;
+def mbranch_protection_pauth_lr : Flag<["-"], "mbranch-protection-pauth-lr">,
+ MarshallingInfoFlag>;
def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">,
MarshallingInfoNegativeFlag>;
def cfguard_no_checks : Flag<["-"], "cfguard-no-checks">,
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index def16c032c869e..3ee39133fcee72 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -225,6 +225,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::BKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
+ BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index ce7e4d4639ceac..6e1842fc64e505 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -419,6 +419,7 @@ bool ARMTargetInfo::validateBranchProtection(StringRef
Spec, StringRef Arch,
BPI.SignKey = LangOptions::SignReturnAddressKeyKind::AKey;
BPI.BranchTargetEnforcement = PBP.BranchTargetEnforcement;
+ BPI.BranchProtectionPAuthLR = PBP.BranchProtectionPAuthLR;
return true;
}
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index b2e173d0d6949e..d78f2594a23764 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -1106,6 +1106,9 @@ void CodeGenModule::Release() {
if (LangOpt
[llvm] [clang] [AArch64] Assembly support for the Armv9.5-A Memory System Extensions (PR #76237)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76237 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] d022f32 - Revert "[ARM] __ARM_ARCH macro definition fix (#81493)"
Author: Tomas Matheson
Date: 2024-02-19T12:19:16Z
New Revision: d022f32c73c57b59a9121eba909f5034e89c628e
URL:
https://github.com/llvm/llvm-project/commit/d022f32c73c57b59a9121eba909f5034e89c628e
DIFF:
https://github.com/llvm/llvm-project/commit/d022f32c73c57b59a9121eba909f5034e89c628e.diff
LOG: Revert "[ARM] __ARM_ARCH macro definition fix (#81493)"
This reverts commit 89c1bf1230e011f2f0e43554c278205fa1819de5.
This has been unimplemenented for a while, and GCC does not implement
it, therefore we need to consider whether we should just deprecate it
in the ACLE instead.
Added:
Modified:
clang/docs/ReleaseNotes.rst
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Basic/Targets/ARM.h
clang/test/Preprocessor/arm-target-features.c
llvm/include/llvm/TargetParser/ARMTargetParser.h
llvm/lib/TargetParser/ARMTargetParser.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 45ace4191592d3..649ad655905af2 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -292,8 +292,6 @@ X86 Support
Arm and AArch64 Support
^^^
-- Fixed the incorrect definition of the __ARM_ARCH macro for architectures
greater than or equal to v8.1.
-
Android Support
^^^
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index dd0218e6ebed81..68032961451d90 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -367,20 +367,8 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
// ACLE predefines. Many can only have one possible value on v8 AArch64.
Builder.defineMacro("__ARM_ACLE", "200");
-
- // __ARM_ARCH is defined as an integer value indicating the current ARM ISA.
- // For ISAs up to and including v8, __ARM_ARCH is equal to the major version
- // number. For ISAs from v8.1 onwards, __ARM_ARCH is scaled up to include the
- // minor version number, e.g. for ARM architecture ARMvX.Y:
- // __ARM_ARCH = X * 100 + Y.
- if (ArchInfo->Version.getMajor() == 8 && ArchInfo->Version.getMinor() == 0)
-Builder.defineMacro("__ARM_ARCH",
-std::to_string(ArchInfo->Version.getMajor()));
- else
-Builder.defineMacro("__ARM_ARCH",
-std::to_string(ArchInfo->Version.getMajor() * 100 +
- ArchInfo->Version.getMinor().value()));
-
+ Builder.defineMacro("__ARM_ARCH",
+ std::to_string(ArchInfo->Version.getMajor()));
Builder.defineMacro("__ARM_ARCH_PROFILE",
std::string("'") + (char)ArchInfo->Profile + "'");
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index cd7fb95259d9db..55b71557452fa0 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -130,7 +130,6 @@ void ARMTargetInfo::setArchInfo(llvm::ARM::ArchKind Kind) {
SubArch = llvm::ARM::getSubArch(ArchKind);
ArchProfile = llvm::ARM::parseArchProfile(SubArch);
ArchVersion = llvm::ARM::parseArchVersion(SubArch);
- ArchMinorVersion = llvm::ARM::parseArchMinorVersion(SubArch);
// cache CPU related strings
CPUAttr = getCPUAttr();
@@ -737,16 +736,9 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (!CPUAttr.empty())
Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
- // __ARM_ARCH is defined as an integer value indicating the current ARM ISA.
- // For ISAs up to and including v8, __ARM_ARCH is equal to the major version
- // number. For ISAs from v8.1 onwards, __ARM_ARCH is scaled up to include the
- // minor version number, e.g. for ARM architecture ARMvX.Y:
- // __ARM_ARCH = X * 100 + Y.
- if (ArchVersion >= 9 || ArchMinorVersion != 0)
-Builder.defineMacro("__ARM_ARCH",
-Twine(ArchVersion * 100 + ArchMinorVersion));
- else
-Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
+ // ACLE 6.4.1 ARM/Thumb instruction set architecture
+ // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
+ Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
if (ArchVersion >= 8) {
// ACLE 6.5.7 Crypto Extension
diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h
index df06e4d120637a..71322a094f5edb 100644
--- a/clang/lib/Basic/Targets/ARM.h
+++ b/clang/lib/Basic/Targets/ARM.h
@@ -60,7 +60,6 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public
TargetInfo {
llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T;
llvm::ARM::ProfileKind ArchProfile;
unsigned ArchVersion;
- unsigned ArchMinorVersion;
LLVM_PREFERRED_TYPE(FPUMode)
unsigned FPU : 5;
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83277 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [NFC][ARM][AArch64] Deduplicated code. (PR #82785)
@@ -1369,13 +1369,20 @@ class TargetInfo : public TransferrableTargetInfo,
}
struct BranchProtectionInfo {
-LangOptions::SignReturnAddressScopeKind SignReturnAddr =
-LangOptions::SignReturnAddressScopeKind::None;
-LangOptions::SignReturnAddressKeyKind SignKey =
-LangOptions::SignReturnAddressKeyKind::AKey;
-bool BranchTargetEnforcement = false;
-bool BranchProtectionPAuthLR = false;
-bool GuardedControlStack = false;
+LangOptions::SignReturnAddressScopeKind SignReturnAddr;
+LangOptions::SignReturnAddressKeyKind SignKey;
+bool BranchTargetEnforcement;
+bool BranchProtectionPAuthLR;
+bool GuardedControlStack;
+
+BranchProtectionInfo() = default;
+
+const char *getSignReturnAddrStr() const {
+ static const char *SignReturnAddrStr[] = {"none", "non-leaf", "all"};
+ assert(static_cast(SignReturnAddr) <= 2 &&
+ "Unexpected SignReturnAddressScopeKind");
+ return SignReturnAddrStr[static_cast(SignReturnAddr)];
+}
tmatheson-arm wrote:
```suggestion
const char *getSignReturnAddrStr() const {
switch (SignReturnAddr) {
case None:
return "none";
case NonLeaf:
return "non-leaf";
case All:
return "all";
}
assert(false && "Unexpected SignReturnAddressScopeKind");
}
```
https://github.com/llvm/llvm-project/pull/82785
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[clang] [NFC][ARM][AArch64] Deduplicated code. (PR #82785)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/82785 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][ARM][AArch64] Add branch protection attributes to the defaults. (PR #83277)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/83277 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [flang] [clang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
https://github.com/tmatheson-arm commented: This looks like a great improvement over the existing system to me. https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -3,8 +3,7 @@ // FEAT_D128 is optional (off by default) for v9.4a and older, and can be enabled using +d128 // RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a%s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a+d128 %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a+nod128 %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### --target=aarch64-none-elf -march=armv9.4-a+nod128 %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // ENABLED: "-target-feature" "+d128" // NOT_ENABLED-NOT: "-target-feature" "+d128" -// DISABLED: "-target-feature" "-d128" tmatheson-arm wrote: So features that are explicitly disabled with a `+noXYZ` will no longer appear in the `-cc1` command line as `-taget-feature -XYZ`? Is that always the case, what about for features that are on by default? https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -308,6 +312,104 @@ inline constexpr ExtensionInfo Extensions[] = {
};
// clang-format on
+struct ExtensionSet {
+ // Set of extensions which are currently enabled.
+ ExtensionBitset Enabled;
+ // Set of extensions which have been enabled or disabled at any point. Used
+ // to avoid cluttering the cc1 command-line with lots of unneeded features.
+ ExtensionBitset Touched;
+ // Base architecture version, which we need to know because some feature
+ // dependencies change depending on this.
+ const ArchInfo *BaseArch;
+
+ ExtensionSet() : Enabled(), Touched(), BaseArch(nullptr) {}
+
+ // Enable the given architecture extension, and any other extensions it
+ // depends on. Does not change the base architecture, or follow dependencies
+ // between features which are only related by required arcitecture versions.
+ void enable(ArchExtKind E);
+
+ // Disable the given architecture extension, and any other extensions which
+ // depend on it. Does not change the base architecture, or follow
+ // dependencies between features which are only related by required
+ // arcitecture versions.
+ void disable(ArchExtKind E);
+
+ // Add default extensions for the given CPU. Records the base architecture,
+ // to later resolve dependencies which depend on it.
+ void addCPUDefaults(const CpuInfo &CPU);
+
+ // Add default extensions for the given architecture version. Records the
+ // base architecture, to later resolve dependencies which depend on it.
+ void addArchDefaults(const ArchInfo &Arch);
+
+ // Add or remove a feature based on a modifier string. The string must be of
tmatheson-arm wrote:
I'm a bit unclear on the terminology. Often "extension" is taken to mean
something which has an entry in `ArchExtKind`, whereas "feature" is an LLVM
backend feature. In the Arm ARM they are referred to as extensions and there is
no concept of features.
Should this be "Add or remove an extension"?
https://github.com/llvm/llvm-project/pull/78270
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[flang] [clang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,20 +1,21 @@ // RAS is off by default for v8a, but can be enabled by +ras (this is not architecturally valid) // RUN: %clang --target=aarch64-none-elf -march=armv8a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s +// RUN: %clang --target=aarch64-none-elf -march=armv8.2a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -march=armv8-a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=generic+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // CHECK-RAS: "-target-feature" "+ras" -// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// CHECK-NORAS: "-target-feature" "-ras" +// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// CHECK-ABSENT-NOT: "-target-feature" ++ras" tmatheson-arm wrote: typo? https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
+
+ // Special cases for dependencies which vary depending on the base
+ // architecture version.
+ if (BaseArch) {
+// +sve implies +f32mm if the base architecture is v8.6A+ or v9.1A+
+// It isn't the case in general that sve implies both f64mm and f32mm
+if (E == AEK_SVE && BaseArch->is_superset(ARMV8_6A))
+ enable(AEK_F32MM);
+
+// +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+
+if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) &&
+!BaseArch->is_superset(ARMV9A))
+ enable(AEK_FP16FML);
+
+// For all architectures, +crypto enables +aes and +sha2.
+if (E == AEK_CRYPTO) {
+ enable(AEK_AES);
+ enable(AEK_SHA2);
+}
+
+// For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4.
+if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) {
+ enable(AEK_SHA3);
+ enable(AEK_SM4);
+}
+ }
+}
+
+void AArch64::ExtensionSet::disable(ArchExtKind E) {
+ // -crypto always disables aes, sha2, sha3 and sm4, even for architectures
+ // where the latter two would not be enabled by +crypto.
+ if (E == AEK_CRYPTO) {
+disable(AEK_AES);
+disable(AEK_SHA2);
+disable(AEK_SHA3);
+disable(AEK_SM4);
+ }
+
+ if (!Enabled.test(E))
+return;
tmatheson-arm wrote:
Does it matter that this won't disable dependent extensions, like it would do
if the current extension was enabled?
https://github.com/llvm/llvm-project/pull/78270
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[clang] [llvm] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,25 +1,25 @@
// RUN: %clang --target=aarch64 -### -c %s 2>&1 | FileCheck
-check-prefix=GENERIC-V8A %s
// RUN: %clang --target=aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck
-check-prefix=GENERIC-V8A %s
-// GENERIC-V8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic" "-target-feature" "+neon" "-target-feature" "+v8a"
+// GENERIC-V8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic" "-target-feature" "+v8a"
tmatheson-arm wrote:
Is something specific happening with neon/noneon, and shouldn't it be checked
for here?
https://github.com/llvm/llvm-project/pull/78270
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[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
tmatheson-arm wrote:
One concern I have is that `ExtensionDependencies` expresses the dependencies
as a directed graph, but in reality we probably just want a tree, as this code
assumes.
https://github.com/llvm/llvm-project/pull/78270
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[llvm] [flang] [clang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,9 +1,9 @@ // RUN: %clang -### --target=aarch64-none-elf -march=armv8.4a+memtag %s 2>&1 | FileCheck %s // RUN: %clang -### --target=aarch64-none-elf -march=armv8.5a+memtag %s 2>&1 | FileCheck %s +// RUN: %clang -### --target=aarch64-none-elf -mcpu=cortex-a510 %s 2>&1 | FileCheck %s // CHECK: "-target-feature" "+mte" -// RUN: %clang -### --target=aarch64-none-elf -march=armv8.4a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE -// RUN: %clang -### --target=aarch64-none-elf -march=armv8.5a+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE +// RUN: %clang -### --target=aarch64-none-elf -mcpu=cortex-a510+nomemtag %s 2>&1 | FileCheck %s --check-prefix=NOMTE tmatheson-arm wrote: This seems like a material change to what is being tested, it might be better split out. (Applies to several files where `-march` has been substituted with `-mcpu`) https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
+
+ // Special cases for dependencies which vary depending on the base
+ // architecture version.
+ if (BaseArch) {
+// +sve implies +f32mm if the base architecture is v8.6A+ or v9.1A+
+// It isn't the case in general that sve implies both f64mm and f32mm
+if (E == AEK_SVE && BaseArch->is_superset(ARMV8_6A))
+ enable(AEK_F32MM);
+
+// +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+
+if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) &&
+!BaseArch->is_superset(ARMV9A))
+ enable(AEK_FP16FML);
+
+// For all architectures, +crypto enables +aes and +sha2.
+if (E == AEK_CRYPTO) {
+ enable(AEK_AES);
+ enable(AEK_SHA2);
+}
+
+// For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4.
+if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) {
+ enable(AEK_SHA3);
+ enable(AEK_SM4);
+}
+ }
+}
+
+void AArch64::ExtensionSet::disable(ArchExtKind E) {
+ // -crypto always disables aes, sha2, sha3 and sm4, even for architectures
+ // where the latter two would not be enabled by +crypto.
+ if (E == AEK_CRYPTO) {
+disable(AEK_AES);
+disable(AEK_SHA2);
+disable(AEK_SHA3);
+disable(AEK_SM4);
+ }
+
+ if (!Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Disable " << lookupExtensionByID(E).Name <<
"\n");
+
+ Touched.set(E);
+ Enabled.reset(E);
+
+ // Recursively disable all features that depends on this one.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Earlier)
+ disable(Dep.Later);
+}
+
+void AArch64::ExtensionSet::toLLVMFeatureList(
+std::vector &Features) const {
+ if (BaseArch && !BaseArch->ArchFeature.empty())
+Features.push_back(BaseArch->ArchFeature);
+
+ for (const auto &E : Extensions) {
+if (E.Feature.empty() || !Touched.test(E.ID))
+ continue;
+if (Enabled.test(E.ID))
+ Features.push_back(E.Feature);
+else
+ Features.push_back(E.NegFeature);
tmatheson-arm wrote:
When exactly do we need negative features?
https://github.com/llvm/llvm-project/pull/78270
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[flang] [clang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -711,10 +819,10 @@ StringRef getArchExtFeature(StringRef ArchExt); StringRef resolveCPUAlias(StringRef CPU); // Information by Name -std::optional getArchForCpu(StringRef CPU); tmatheson-arm wrote: Why the switch back to raw pointers from std::optional? This seems to undo what was done in https://reviews.llvm.org/D142539 Does this new implementation rely on there being one global copy of `ArchInfo`? A while back I tried to make this work so that `ArchInfo::operator==` made use of this address, but that ended up being unworkable so we switched to allowing copying of `ArchInfo` objects. https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,49 +1,51 @@
// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 |
FileCheck %s --check-prefix=SME-IMPLY
-// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+bf16"
+// SME-IMPLY: "-target-feature" "+bf16"{{.*}} "-target-feature" "+sme"
// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme %s -### 2>&1 |
FileCheck %s --check-prefix=NOSME
-// NOSME: "-target-feature" "-sme"
+// NOSME-NOT: "-target-feature" "{{\+|-}}sme"
// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosme %s -### 2>&1
| FileCheck %s --check-prefix=SME-REVERT
// SME-REVERT-NOT: "-target-feature" "+sme"
-// SME-REVERT: "-target-feature" "+bf16" "-target-feature" "-sme"
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+// SME-REVERT: "-target-feature" "+bf16"{{.*}} "-target-feature" "-sme"
tmatheson-arm wrote:
So here, `+sme+nosme` should no longer explicitly remove `sme-f64f64` etc,
which are dependencies of `+sme`, instead they default to off and are not
mentioned on the `-cc1` command line? In other words, there is no behaviour
change here, iiuc.
Do we have any later checks that the features are reassembled correctly? Checks
for preprocessor macros maybe.
https://github.com/llvm/llvm-project/pull/78270
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[llvm] [clang] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -308,6 +312,104 @@ inline constexpr ExtensionInfo Extensions[] = {
};
// clang-format on
+struct ExtensionSet {
+ // Set of extensions which are currently enabled.
+ ExtensionBitset Enabled;
+ // Set of extensions which have been enabled or disabled at any point. Used
+ // to avoid cluttering the cc1 command-line with lots of unneeded features.
+ ExtensionBitset Touched;
+ // Base architecture version, which we need to know because some feature
+ // dependencies change depending on this.
+ const ArchInfo *BaseArch;
tmatheson-arm wrote:
What does this point to exactly? What owns the thing it points to?
https://github.com/llvm/llvm-project/pull/78270
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[clang] [llvm] [flang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -1,20 +1,21 @@ // RAS is off by default for v8a, but can be enabled by +ras (this is not architecturally valid) // RUN: %clang --target=aarch64-none-elf -march=armv8a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s +// RUN: %clang --target=aarch64-none-elf -march=armv8.2a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -march=armv8-a+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=generic+ras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // RUN: %clang --target=aarch64-none-elf -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-RAS %s // CHECK-RAS: "-target-feature" "+ras" -// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-NORAS %s -// CHECK-NORAS: "-target-feature" "-ras" +// RUN: %clang --target=aarch64-none-elf -march=armv8a+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// RUN: %clang --target=aarch64-none-elf -mcpu=generic+noras -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ABSENT %s +// CHECK-ABSENT-NOT: "-target-feature" ++ras" // RAS is on by default for v8.2a, but can be disabled by +noras -// FIXME: in the current implementation, RAS is not on by default at all for v8.2a (the test says it all...) -// RUN: %clang --target=aarch64 -march=armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=V82ARAS %s -// RUN: %clang --target=aarch64 -march=armv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=V82ARAS %s +// RUN: %clang --target=aarch64 -march=armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-RAS %s +// RUN: %clang --target=aarch64 -march=armv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-RAS %s // V82ARAS-NOT: "-target-feature" "+ras" // V82ARAS-NOT: "-target-feature" "-ras" tmatheson-arm wrote: This check-prefix is no longer in use https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [clang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -3,15 +3,14 @@ // FEAT_ITE is optional (off by default) for v8.9a/9.4a and older, and can be enabled using +ite // RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a+ite %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a+noite %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### --target=aarch64-none-elf -march=armv8.8-a+noite %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a+ite %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a+noite %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### --target=aarch64-none-elf -march=armv9.3-a+noite %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED // FEAT_ITE is invalid before v8 // RUN: not %clang -### --target=arm-none-none-eabi -march=armv7-a+ite %s 2>&1 | FileCheck %s --check-prefix=INVALID // INVALID: error: unsupported argument 'armv7-a+ite' to option '-march=' // ENABLED: "-target-feature" "+ite" // NOT_ENABLED-NOT: "-target-feature" "+ite" tmatheson-arm wrote: Should this also check that the negative case isn't present? (Applies to many other files too.) https://github.com/llvm/llvm-project/pull/78270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[flang] [llvm] [clang] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)
@@ -150,3 +153,137 @@ void
AArch64::PrintSupportedExtensions(StringMap DescMap) {
}
}
}
+
+const llvm::AArch64::ExtensionInfo &
+lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
+ for (const auto &E : llvm::AArch64::Extensions)
+if (E.ID == ExtID)
+ return E;
+ assert(false && "Invalid extension ID");
+}
+
+void AArch64::ExtensionSet::enable(ArchExtKind E) {
+ if (Enabled.test(E))
+return;
+
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+
+ Touched.set(E);
+ Enabled.set(E);
+
+ // Recursively enable all features that this one depends on. This handles all
+ // of the simple cases, where the behaviour doesn't depend on the base
+ // architecture version.
+ for (auto Dep : ExtensionDependencies)
+if (E == Dep.Later)
+ enable(Dep.Earlier);
+
+ // Special cases for dependencies which vary depending on the base
+ // architecture version.
+ if (BaseArch) {
+// +sve implies +f32mm if the base architecture is v8.6A+ or v9.1A+
+// It isn't the case in general that sve implies both f64mm and f32mm
+if (E == AEK_SVE && BaseArch->is_superset(ARMV8_6A))
+ enable(AEK_F32MM);
+
+// +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+
+if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) &&
+!BaseArch->is_superset(ARMV9A))
+ enable(AEK_FP16FML);
+
+// For all architectures, +crypto enables +aes and +sha2.
+if (E == AEK_CRYPTO) {
+ enable(AEK_AES);
+ enable(AEK_SHA2);
+}
+
+// For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4.
+if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) {
+ enable(AEK_SHA3);
+ enable(AEK_SM4);
+}
+ }
tmatheson-arm wrote:
This logic is so much nicer than what we currently have.
https://github.com/llvm/llvm-project/pull/78270
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[clang] [Clang] Bring initFeatureMap back to AArch64TargetInfo. (PR #96832)
tmatheson-arm wrote: I think a test demonstrating the problem would be the fastest way forward. https://github.com/llvm/llvm-project/pull/96832 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64][TableGen] Create a ProcessorAlias record (PR #96249)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/96249 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64][TableGen] Create a ProcessorAlias record (PR #96249)
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35,
cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae,
cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75,
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c,
cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82,
cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4,
cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3,
neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae,
exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88,
thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone,
apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4,
apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16,
apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b,
oryon-1, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1, ampere1a,
ampere1b, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15,
apple-a16, apple-a17, apple-a7, apple-a8, apple-a9, apple-m1, apple-m2,
apple-m3, apple-m4, apple-s4, apple-s5, carmel, cobalt-100, cortex-a34,
cortex-a35, cortex-a510, cortex-a520, cortex-a520ae, cortex-a53, cortex-a55,
cortex-a57, cortex-a65, cortex-a65ae, cortex-a710, cortex-a715, cortex-a72,
cortex-a720, cortex-a720ae, cortex-a725, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-r82,
cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4,
cortex-x925, cyclone, exynos-m3, exynos-m4, exynos-m5, falkor, generic, grace,
kryo, neoverse-512tvb, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3,
neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, oryon-1, saphira,
thunderx, thunderx2t99, thunderx3t110, thunderxt81, thunderxt83, thunderxt88,
tsv110{{$}}
tmatheson-arm wrote:
I meant `AARCH64-SAME`, but you are right, that will potentially miss things.
I'd be happy with changing the actual output format, but it doesn't have to be
done in this PR.
https://github.com/llvm/llvm-project/pull/96249
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -11465,6 +11465,10 @@ static bool CheckMultiVersionFirstFunction(Sema &S,
FunctionDecl *FD) {
// otherwise it is treated as a normal function.
if (TA && !TA->isDefaultVersion())
return false;
+ // The target_version attribute only causes Multiversioning if this
+ // declaration is NOT the default version.
+ if (TVA && TVA->isDefaultVersion())
+return false;
tmatheson-arm wrote:
Is it allowed to have both `target` and `target_version` on the same function?
If so, can these early returns interfere with each other?
https://github.com/llvm/llvm-project/pull/96628
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -11523,10 +11525,17 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
const auto *OldTVA = OldFD->getAttr();
// If the old decl is NOT MultiVersioned yet, and we don't cause that
// to change, this is a simple redeclaration.
- if ((NewTA && !NewTA->isDefaultVersion() &&
- (!OldTA || OldTA->getFeaturesStr() == NewTA->getFeaturesStr())) ||
- (NewTVA && !NewTVA->isDefaultVersion() &&
- (!OldTVA || OldTVA->getName() == NewTVA->getName(
+ if (NewTA && !NewTA->isDefaultVersion() &&
+ (!OldTA || OldTA->getFeaturesStr() == NewTA->getFeaturesStr()))
+return false;
+
+ // The target_version attribute only causes Multiversioning if this
+ // declaration is NOT the default version. Moreover, the old declaration
+ // must be the default version (either explicitly via the attribute,
+ // or implicitly without it).
+ if (NewTVA && NewTVA->isDefaultVersion())
+return false;
tmatheson-arm wrote:
```suggestion
// If this is target_version("default") (implicit or explicit) it doesn't
trigger MV
if (!NewTVA || NewTVA->isDefaultVersion())
return false;
```
This is my understanding of what we want to do here.
https://github.com/llvm/llvm-project/pull/96628
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -11576,22 +11584,6 @@ static bool CheckTargetCausesMultiVersioning(Sema &S,
FunctionDecl *OldFD,
}
}
- if (NewTVA) {
tmatheson-arm wrote:
If you are reasoning based on that, it might be good to add an assert checking
it:
```
assert(!OldTVA || OldTVA->isDefaultVersion());
```
https://github.com/llvm/llvm-project/pull/96628
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -11523,10 +11525,17 @@ static bool CheckTargetCausesMultiVersioning(Sema &S, FunctionDecl *OldFD, const auto *OldTVA = OldFD->getAttr(); // If the old decl is NOT MultiVersioned yet, and we don't cause that // to change, this is a simple redeclaration. - if ((NewTA && !NewTA->isDefaultVersion() && - (!OldTA || OldTA->getFeaturesStr() == NewTA->getFeaturesStr())) || - (NewTVA && !NewTVA->isDefaultVersion() && - (!OldTVA || OldTVA->getName() == NewTVA->getName( + if (NewTA && !NewTA->isDefaultVersion() && + (!OldTA || OldTA->getFeaturesStr() == NewTA->getFeaturesStr())) +return false; + + // The target_version attribute only causes Multiversioning if this + // declaration is NOT the default version. Moreover, the old declaration + // must be the default version (either explicitly via the attribute, + // or implicitly without it). + if (NewTVA && NewTVA->isDefaultVersion()) +return false; + if (NewTVA && OldTVA && !OldTVA->isDefaultVersion()) return false; tmatheson-arm wrote: ```suggestion ``` We already know that `!isMultiVersioned()` at this point, because of the call site (and assert at the top of the function). Presumably these checks for the old version have already been done? https://github.com/llvm/llvm-project/pull/96628 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -11947,24 +11939,8 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
FunctionDecl *OldFD = OldDecl->getAsFunction();
- if (!OldFD->isMultiVersion() && MVKind == MultiVersionKind::None) {
-if (NewTVA || !OldFD->getAttr())
- return false;
-if (!NewFD->getType()->getAs()) {
- // Multiversion declaration doesn't have prototype.
- S.Diag(NewFD->getLocation(), diag::err_multiversion_noproto);
- NewFD->setInvalidDecl();
-} else {
- // No "target_version" attribute is equivalent to "default" attribute.
- NewFD->addAttr(TargetVersionAttr::CreateImplicit(
- S.Context, "default", NewFD->getSourceRange()));
- NewFD->setIsMultiVersion();
- OldFD->setIsMultiVersion();
- OldDecl = OldFD;
- Redeclaration = true;
-}
-return true;
- }
+ if (!OldFD->isMultiVersion() && MVKind == MultiVersionKind::None)
tmatheson-arm wrote:
`!OldFD->isMultiVersion()` is asserted at the top of the function, so this
looks unnecessary. However OldFD is redefined here. This is confusing. Does the
original assert still hold with the new assignment?
https://github.com/llvm/llvm-project/pull/96628
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -11465,6 +11465,10 @@ static bool CheckMultiVersionFirstFunction(Sema &S,
FunctionDecl *FD) {
// otherwise it is treated as a normal function.
if (TA && !TA->isDefaultVersion())
return false;
+ // The target_version attribute only causes Multiversioning if this
+ // declaration is NOT the default version.
+ if (TVA && TVA->isDefaultVersion())
+return false;
tmatheson-arm wrote:
```suggestion
if (!TVA || TVA->isDefaultVersion())
return false;
```
https://github.com/llvm/llvm-project/pull/96628
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
https://github.com/tmatheson-arm deleted https://github.com/llvm/llvm-project/pull/96628 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -102,8 +102,9 @@ int __attribute__((target_version("sha2"))) combine(void) {
return 1; }
// expected-error@+1 {{multiversioned function declaration has a different
calling convention}}
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void)
{ return 2; }
-int __attribute__((target_version("fp+aes+pmull+rcpc"))) unspec_args() {
return -1; }
+int unspec_args();
// expected-error@-1 {{multiversioned function must have a prototype}}
-// expected-error@+1 {{multiversioned function must have a prototype}}
+// expected-note@+1 {{function multiversioning caused by this declaration}}
+int __attribute__((target_version("fp"))) unspec_args() { return -1; }
int __attribute__((target_version("default"))) unspec_args() { return 0; }
tmatheson-arm wrote:
Can we keep the test to check that we _don't_ emit a diagnostic then?
https://github.com/llvm/llvm-project/pull/96628
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
@@ -102,8 +102,9 @@ int __attribute__((target_version("sha2"))) combine(void) {
return 1; }
// expected-error@+1 {{multiversioned function declaration has a different
calling convention}}
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void)
{ return 2; }
-int __attribute__((target_version("fp+aes+pmull+rcpc"))) unspec_args() {
return -1; }
+int unspec_args();
// expected-error@-1 {{multiversioned function must have a prototype}}
-// expected-error@+1 {{multiversioned function must have a prototype}}
+// expected-note@+1 {{function multiversioning caused by this declaration}}
+int __attribute__((target_version("fp"))) unspec_args() { return -1; }
int __attribute__((target_version("default"))) unspec_args() { return 0; }
tmatheson-arm wrote:
Either way lets keep the original test, if only to document what that case does
now.
https://github.com/llvm/llvm-project/pull/96628
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
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[clang] [clang][FMV] Do not omit explicit default target_version attribute. (PR #96628)
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[clang] [Clang] Bring initFeatureMap back to AArch64TargetInfo. (PR #96832)
tmatheson-arm wrote: Thank you for the example, I understand what is happening how. - Before #94279, we used to add CPU features in `AArch64::initFeatureMap`. - In #94279, we decided that actually you should do that in the Driver, which should put all `-target-features` it wants on the -cc1 command line. The Driver is responsible for expanding the CPU (and architecture) feature dependencies and their interaction with any modifiers on the command line. - This means that when `initFeatureMap` runs in `clang`, `FeaturesAsWritten` is populated with the CPU features and is used to initialise the `FeatureMap`. - In contrast, you are not using the `Driver`, and do not populate `FeaturesAsWritten` with the CPU features. - Instead, you expect `initFeatureMap` to add CPU features. This is not unreasonable, given that the CPU is passed the function and several other backends add CPU features at this stage. [This bit of code](https://github.com/llvm/llvm-project/pull/94279/files#diff-2ccae12096c75c4b8422ea0d2fdf6b195896d2554d62cce604e8fcb56a78ef62L1057-L1067) used to crudely add the CPU features to the end of the feature list. However there are some problems with that approach, which we attempted to rectify in #94279: - CPU features that were explicitly disabled on the command line could actually end up enabled in the backend - The architecture features (i.e. implied by `-march`) were not treated the same way as the CPU features (`-mcpu`) For example, if you wrote: `clang -mcpu=cortex-a75+norcpc -###`, you would see all the Cortex-A75 features expanded on the `-cc1` command line, but with RCPC disabled: `-target-feature -rcpc`. But in this case, `AArch64::initFeatureMap` would have re-added `+rcpc`, overriding the command line. (This is technically not the case after [this line](https://github.com/llvm/llvm-project/pull/94279/files#diff-2ccae12096c75c4b8422ea0d2fdf6b195896d2554d62cce604e8fcb56a78ef62L1092) was added, but the general point is that `initFeatureMap` broke feature dependency resolution in ways that are difficult to reason about). There doesn't seem to be a way to specify an architecture in `TargetOptions`, which looks odd to me. That means there is no way to select e.g. `armv9.4-a` in your example, except by manually adding the features in `TargetOptions::Features` or `TargetOptions::FeaturesAsWritten`. So the way that we set up the AArch64 backend in #94279 is to require you to calculate your feature set up front, which are then trivially passed through by the default `TargetInfo::initFeatureMap`. I'm not sure there is a clear answer on this one. I can't see a way to easily let `AArch64:: initFeatureMap` add CPU features again without breaking the dependency resolution. I am open to suggestions though. If you wanted to go the route of building the feature list before calling `initFeatureMap`, the functions `tools::getTargetFeatures` and `aarch64::getAArch64TargetFeatures` can do that for you. Currently they require a `const Driver &D`, but fundamentally I think they just need a `DiagnosticsEngine&` so that could be changed. I'm open to other suggestions too. https://github.com/llvm/llvm-project/pull/96832 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)
@@ -445,4 +445,21 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
Features.push_back("+no-bti-at-return-twice");
+
+ // Parse AArch64 CPU Features
+ const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
tmatheson-arm wrote:
Feels like this should be done in
`getAArch64ArchFeaturesFromMcpu`/`DecodeAArch64Mcpu`
https://github.com/llvm/llvm-project/pull/97749
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[clang] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)
@@ -445,4 +445,21 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
Features.push_back("+no-bti-at-return-twice");
+
+ // Parse AArch64 CPU Features
+ const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
+ StringRef CPUName;
+
+ if (CPUArg) {
+CPUName = CPUArg->getValue();
+if (CPUName == "native") {
+ llvm::StringMap HostFeatures;
+ if (llvm::sys::getHostCPUFeatures(HostFeatures)) {
+for (auto &F : HostFeatures) {
+ Features.push_back(
+Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+}
tmatheson-arm wrote:
```suggestion
for (auto &[Name, Enabled] : HostFeatures) {
Features.push_back(
Args.MakeArgString((Enabled ? "+" : "-") + Name));
}
```
https://github.com/llvm/llvm-project/pull/97749
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[clang] [clang][AArch64] Add getHostCPUFeatures to query for enabled features in cpu info (PR #97749)
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[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
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[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/97824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
@@ -15,22 +15,23 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/Host.h"
+#include
+
using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- StringMap features;
-
- if (!sys::getHostCPUFeatures(features))
+ if (std::optional> features =
+ sys::getHostCPUFeatures(features)) {
+if ((*features)["sse"])
tmatheson-arm wrote:
Maybe
```suggestion
if (features->lookup("sse"))
```
which does the same, but doesn't insert the default entry into the map.
https://github.com/llvm/llvm-project/pull/97824
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[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lldb] [llvm] [llvm][TargetParser] Return optional from getHostCPUFeatures (PR #97824)
@@ -22,13 +22,13 @@ using namespace llvm;
int main(int argc, char **argv) {
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
- if (std::optional> features =
+ if (const std::optional> features =
sys::getHostCPUFeatures(features)) {
-if ((*features)["sse"])
+if (features->contains("sse"))
tmatheson-arm wrote:
`contains` will only check if the key exists in the map, but you want to
actually get the `bool` if it exists and default to `false` if it doesn't. I
think `lookup` fits better.
https://github.com/llvm/llvm-project/pull/97824
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[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
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[clang] [lldb] [llvm] [AArch64][TargetParser] autogen ArchExtKind enum - renaming (PR #90320)
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[clang] 6c369cf - [AArch64] Changes missing from cfca97742723 (#90314)
Author: Tomas Matheson
Date: 2024-05-01T18:01:14+01:00
New Revision: 6c369cf937b7d9acb98a1fc46b1340cef7703e12
URL:
https://github.com/llvm/llvm-project/commit/6c369cf937b7d9acb98a1fc46b1340cef7703e12
DIFF:
https://github.com/llvm/llvm-project/commit/6c369cf937b7d9acb98a1fc46b1340cef7703e12.diff
LOG: [AArch64] Changes missing from cfca97742723 (#90314)
Added:
Modified:
clang/lib/Basic/CMakeLists.txt
clang/lib/CodeGen/CMakeLists.txt
clang/lib/Driver/CMakeLists.txt
clang/tools/driver/CMakeLists.txt
llvm/include/module.install.modulemap
llvm/include/module.modulemap
Removed:
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index 2e218ba7c84cca..824d4a0e2eee57 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -130,6 +130,9 @@ add_clang_library(clangBasic
DEPENDS
omp_gen
ClangDriverOptions
+ # These generated headers are included transitively.
+ ARMTargetParserTableGen
+ AArch64TargetParserTableGen
)
target_link_libraries(clangBasic
diff --git a/clang/lib/CodeGen/CMakeLists.txt
b/clang/lib/CodeGen/CMakeLists.txt
index 52216d93a302bb..7a933d0ed0d0d7 100644
--- a/clang/lib/CodeGen/CMakeLists.txt
+++ b/clang/lib/CodeGen/CMakeLists.txt
@@ -143,6 +143,9 @@ add_clang_library(clangCodeGen
DEPENDS
intrinsics_gen
ClangDriverOptions
+ # These generated headers are included transitively.
+ ARMTargetParserTableGen
+ AArch64TargetParserTableGen
LINK_LIBS
clangAST
diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt
index 58427e3f83c420..32a4378ab499fa 100644
--- a/clang/lib/Driver/CMakeLists.txt
+++ b/clang/lib/Driver/CMakeLists.txt
@@ -90,6 +90,9 @@ add_clang_library(clangDriver
DEPENDS
ClangDriverOptions
+ # These generated headers are included transitively.
+ ARMTargetParserTableGen
+ AArch64TargetParserTableGen
LINK_LIBS
clangBasic
diff --git a/clang/tools/driver/CMakeLists.txt
b/clang/tools/driver/CMakeLists.txt
index d70b92b0984e52..290bf2a42536dd 100644
--- a/clang/tools/driver/CMakeLists.txt
+++ b/clang/tools/driver/CMakeLists.txt
@@ -31,6 +31,9 @@ add_clang_tool(clang
DEPENDS
intrinsics_gen
+ # These generated headers are included transitively.
+ ARMTargetParserTableGen
+ AArch64TargetParserTableGen
${support_plugins}
GENERATE_DRIVER
)
diff --git a/llvm/include/module.install.modulemap
b/llvm/include/module.install.modulemap
index f7302830f561de..b917cddc78034c 100644
--- a/llvm/include/module.install.modulemap
+++ b/llvm/include/module.install.modulemap
@@ -31,5 +31,7 @@ module LLVM_Extern_Utils_DataTypes {
}
module LLVM_Extern_TargetParser_Gen {
+ textual header "llvm/TargetParser/ARMTargetParserDef.inc"
+ textual header "llvm/TargetParser/AArch64TargetParserDef.inc"
textual header "llvm/TargetParser/RISCVTargetParserDef.inc"
}
diff --git a/llvm/include/module.modulemap b/llvm/include/module.modulemap
index e60e03a282ac6e..b00da6d7cd28c7 100644
--- a/llvm/include/module.modulemap
+++ b/llvm/include/module.modulemap
@@ -345,6 +345,11 @@ extern module LLVM_Extern_Utils_DataTypes
"module.extern.modulemap"
// Build the module with the tablegen-generated files needed by the
// TargetParser module before building the TargetParser module itself.
module TargetParserGen {
+ module AArch64TargetParserDef {
+header "llvm/TargetParser/AArch64TargetParser.h"
+extern module LLVM_Extern_TargetParser_Gen "module.extern.modulemap"
+export *
+ }
module RISCVTargetParserDef {
header "llvm/TargetParser/RISCVTargetParser.h"
extern module LLVM_Extern_TargetParser_Gen "module.extern.modulemap"
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[clang] [lldb] [llvm] [AArch64][TargetParser] autogen ArchExtKind enum - renaming (PR #90320)
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[clang] 1b13bc0 - [AArch64] fix Windows buildbot failure
Author: Tomas Matheson Date: 2024-06-10T14:47:23+01:00 New Revision: 1b13bc05fe4a3b7b4916387543f0a64d41909e83 URL: https://github.com/llvm/llvm-project/commit/1b13bc05fe4a3b7b4916387543f0a64d41909e83 DIFF: https://github.com/llvm/llvm-project/commit/1b13bc05fe4a3b7b4916387543f0a64d41909e83.diff LOG: [AArch64] fix Windows buildbot failure Introduced by 2cf14398c9341feddb419e7ff9c8c5623a3da3db (#94279). See also 6c369cf937b7d9acb98a1fc46b1340cef7703e12. The build system cannot track transitive dependencies on generated headers for some reason. Added: Modified: clang/lib/AST/CMakeLists.txt Removed: diff --git a/clang/lib/AST/CMakeLists.txt b/clang/lib/AST/CMakeLists.txt index a5d3dacfc1a84..0328666d59b1f 100644 --- a/clang/lib/AST/CMakeLists.txt +++ b/clang/lib/AST/CMakeLists.txt @@ -139,4 +139,6 @@ add_clang_library(clangAST omp_gen ClangDriverOptions intrinsics_gen + # These generated headers are included transitively. + AArch64TargetParserTableGen ) ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] set AppleA14 architecture version to v8.4-a (PR #92600)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/92600 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Reland "[AArch64] Decouple feature dependency expansion. (#94279)" (PR #95231)
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[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/95214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -521,7 +521,14 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_SHA3, AArch64::AEK_FP16,
AArch64::AEK_FP16FML})},
-
+// Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as
+// requiring SVE, which is optional according to the Arm ARM and not
+// supported by the core. ARMv8.7a is the next closest choice.
tmatheson-arm wrote:
>From the Arm ARM:
> FEAT_SVE2 is OPTIONAL from Armv9.0.
In LLVM, SVE2 is an `Implied` (read: mandatory) feature of 9.0-a (wrong), and
SVE and SVE2 are both on by default for the architecture:
```
def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
[HasV8_5aOps, FeatureMEC, FeatureSVE2],
!listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,
FeatureSVE2])>;
```
It should be possible to remove SVE2 from the `Implied` list while keeping it
in the list of default extensions, which would avoid any user-facing changes.
I'm not sure why FEAT_MEC is enabled there either.
> FEAT_MEC is OPTIONAL from Armv9.2.
https://github.com/llvm/llvm-project/pull/95478
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[clang] [llvm] Parse target attribute (PR #95519)
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[clang] [llvm] Parse target attribute (PR #95519)
@@ -13725,12 +13725,10 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap, // Make a copy of the features as passed on the command line into the // beginning of the additional features from the function to override. -// AArch64 handles command line option features in parseTargetAttr(). -if (!Target->getTriple().isAArch64()) tmatheson-arm wrote: Removing this will break the dependency expansion done in `parseTargetAttr()` https://github.com/llvm/llvm-project/pull/95519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Parse target attribute (PR #95519)
https://github.com/tmatheson-arm requested changes to this pull request. https://github.com/llvm/llvm-project/pull/95519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisibleName; // Human readable name used in -march/-cpu,
e.g. "profile"
std::optional Alias; // An alias for this extension, if one
exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
- StringRef Feature; // -mattr enable string, e.g. "+spe"
- StringRef NegFeature; // -mattr disable string, e.g. "-spe"
+ StringRef ArchFeatureName; // The feature name defined by the
Architecture
tmatheson-arm wrote:
```suggestion
StringRef ArchFeatureName; // The feature name defined by the
Architecture e.g. FEAT_AdvSIMD
```
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisibleName; // Human readable name used in -march/-cpu,
e.g. "profile"
tmatheson-arm wrote:
This is also what is used in the `target` attribute.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -114,12 +114,14 @@ using ExtensionBitset = Bitset;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisibleName; // Human readable name used in -march/-cpu,
e.g. "profile"
std::optional Alias; // An alias for this extension, if one
exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
- StringRef Feature; // -mattr enable string, e.g. "+spe"
- StringRef NegFeature; // -mattr disable string, e.g. "-spe"
+ StringRef ArchFeatureName; // The feature name defined by the
Architecture
+ StringRef Description; // The textual description of the extension
+ StringRef TargetFeature;// -target-feature/-mattr enable string,
e.g. "+spe"
tmatheson-arm wrote:
```suggestion
StringRef PosTargetFeature;// -target-feature/-mattr enable string,
e.g. "+spe"
```
Keeps it consistent with `NegTargetFeature`, and makes it clear it includes the
`+`
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -23,6 +23,7 @@ class Extension< string TargetFeatureName,// String used for -target-feature and -march, unless overridden. string Spelling, // The XYZ in HasXYZ and AEK_XYZ. + string ArchitectureFeatureName, // The extension's "FEAT_*"" name(s) defined by the architecture tmatheson-arm wrote: Keep the name in sync with the name in the struct if you can https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -116,7 +116,9 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch)
{
std::optional
AArch64::parseArchExtension(StringRef ArchExt) {
for (const auto &A : Extensions) {
-if (ArchExt == A.Name || ArchExt == A.Alias)
+if (A.UserVisibleName.empty() && !A.Alias)
+ continue;
tmatheson-arm wrote:
This seems redundant when looking at the following `if` condition, maybe we
actually want to check if `ArchExt.empty()` instead?
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// = Architecture extensions =
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions
2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
tmatheson-arm wrote:
Use ARCH-NEXT to guarantee we don't miss any changes.
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1
| FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// = Architecture extensions =
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions
2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
tmatheson-arm wrote:
These should go in a separate file so that the tests can be autogenerated (or
autogenerate this file, if possible).
https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
https://github.com/tmatheson-arm deleted https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Reland "[AArch64] Decouple feature dependency expansion. (#94279)" (PR #95519)
https://github.com/tmatheson-arm approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/95519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][TargetParser] move CPUInfo into tablegen [NFC] (PR #92145)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/92145 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Reland "[AArch64] Decouple feature dependency expansion. (#94279)" (PR #95519)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/95519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
https://github.com/tmatheson-arm approved this pull request. https://github.com/llvm/llvm-project/pull/95805 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Split fmv and extensions (PR #92882)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/92882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Split fmv and extensions (PR #92882)
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/92882
>From b3e9e2f313d3c3a51b7b6690a5cca67a3ec87dd6 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Tue, 18 Jun 2024 22:23:11 +0100
Subject: [PATCH] [AArch64][TargetParser] Split FMV and extensions
---
clang/include/clang/Basic/TargetInfo.h| 5 -
clang/lib/AST/ASTContext.cpp | 4 +-
clang/lib/Basic/Targets/AArch64.cpp | 20 +-
clang/lib/Basic/Targets/AArch64.h | 1 -
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/lib/CodeGen/Targets/AArch64.cpp | 2 +-
clang/test/CodeGen/aarch64-fmv-dependencies.c | 92
.../llvm/TargetParser/AArch64TargetParser.h | 32 ++-
llvm/lib/Target/AArch64/AArch64.td| 1 +
llvm/lib/Target/AArch64/AArch64FMV.td | 99 +
llvm/lib/Target/AArch64/AArch64Features.td| 206 --
llvm/lib/TargetParser/AArch64TargetParser.cpp | 30 ++-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 36 ++-
13 files changed, 281 insertions(+), 249 deletions(-)
create mode 100644 llvm/lib/Target/AArch64/AArch64FMV.td
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 8a6511b9ced83..9b0ae2102e098 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1400,11 +1400,6 @@ class TargetInfo : public TransferrableTargetInfo,
return true;
}
- /// For given feature return dependent ones.
- virtual StringRef getFeatureDependencies(StringRef Feature) const {
-return StringRef();
- }
-
struct BranchProtectionInfo {
LangOptions::SignReturnAddressScopeKind SignReturnAddr;
LangOptions::SignReturnAddressKeyKind SignKey;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index aa22825602a40..5329fb6bf22f5 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13683,9 +13683,9 @@ static std::vector
getFMVBackendFeaturesFor(
const llvm::SmallVectorImpl &FMVFeatStrings) {
std::vector BackendFeats;
for (StringRef F : FMVFeatStrings) {
-if (auto FMVExt = llvm::AArch64::parseArchExtension(F)) {
+if (auto FMVExt = llvm::AArch64::parseFMVExtension(F)) {
SmallVector Feats;
- FMVExt->DependentFeatures.split(Feats, ',', -1, false);
+ FMVExt->Features.split(Feats, ',', -1, false);
for (StringRef F : Feats)
BackendFeats.push_back(F.str());
}
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index fba2ad00df96d..31d8121b91d10 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -673,34 +673,30 @@ AArch64TargetInfo::getVScaleRange(const LangOptions
&LangOpts) const {
unsigned AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const {
if (Name == "default")
return 0;
- if (auto Ext = llvm::AArch64::parseArchExtension(Name))
-return Ext->FmvPriority;
+ if (auto Ext = llvm::AArch64::parseFMVExtension(Name))
+return Ext->Priority;
return 0;
}
unsigned AArch64TargetInfo::multiVersionFeatureCost() const {
// Take the maximum priority as per feature cost, so more features win.
- return llvm::AArch64::ExtensionInfo::MaxFMVPriority;
+ constexpr unsigned MaxFMVPriority = 1000;
+ return MaxFMVPriority;
}
bool AArch64TargetInfo::doesFeatureAffectCodeGen(StringRef Name) const {
- if (auto Ext = llvm::AArch64::parseArchExtension(Name))
-return !Ext->DependentFeatures.empty();
+ // FMV extensions which imply no backend features do not affect codegen.
+ if (auto Ext = llvm::AArch64::parseFMVExtension(Name))
+return !Ext->Features.empty();
return false;
}
-StringRef AArch64TargetInfo::getFeatureDependencies(StringRef Name) const {
- if (auto Ext = llvm::AArch64::parseArchExtension(Name))
-return Ext->DependentFeatures;
- return StringRef();
-}
-
bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
// CPU features might be separated by '+', extract them and check
llvm::SmallVector Features;
FeatureStr.split(Features, "+");
for (auto &Feature : Features)
-if (!llvm::AArch64::parseArchExtension(Feature.trim()).has_value())
+if (!llvm::AArch64::parseFMVExtension(Feature.trim()).has_value())
return false;
return true;
}
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index c0a6bd2de6b04..71510fe289510 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -151,7 +151,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
std::optional>
getVScaleRange(const LangOptions &LangOpts) const override;
bool doesFeatureAffectCodeGen(StringRef Name) const override;
- StringRef getFeatureDependencies(StringRef Name) const override;
bool validateCpuSupports(StringRef FeatureStr) const override;
bool hasFeature(
[clang] [llvm] Split fmv and extensions (PR #92882)
https://github.com/tmatheson-arm ready_for_review https://github.com/llvm/llvm-project/pull/92882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Split fmv and extensions (PR #92882)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/92882 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PAC][ELF][AArch64] Encode signed GOT flag in PAuth core info (PR #96159)
https://github.com/tmatheson-arm approved this pull request. LGTM, just based on what I can see from implementation of the existing bits in the version field. https://github.com/llvm/llvm-project/pull/96159 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
tmatheson-arm wrote: > Mind sticking it in a gist at least so folks can use it for downstream > subtargets? [Here you go](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d) https://github.com/llvm/llvm-project/pull/97829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
https://github.com/tmatheson-arm closed https://github.com/llvm/llvm-project/pull/97829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)
@@ -0,0 +1,24 @@ +// REQUIRES: aarch64-registered-target tmatheson-arm wrote: I've kept them as-is so that they still correspond to the [generating script](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d). https://github.com/llvm/llvm-project/pull/97829 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -261,9 +261,9 @@ __attribute__((target_version("jscvt"))) int
default_def_with_version_decls(void
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+lse,-v9.5a" }
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+neon,+rdm,-v9.5a" }
// CHECK: attributes #[[ATTR5:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+dotprod,+fp-armv8,+neon,-v9.5a" }
-// CHECK: attributes #[[ATTR6:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
-// CHECK: attributes #[[ATTR7:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="-v9.5a" }
-// CHECK: attributes #[[ATTR8:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="+lse,-v9.5a" }
+// CHECK: attributes #[[ATTR6:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="-v9.5a" }
+// CHECK: attributes #[[ATTR7:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-features"="+lse,-v9.5a" }
+// CHECK: attributes #[[ATTR8:[0-9]+]] = { "no-trapping-math"="true"
"stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+jsconv,+neon,-v9.5a" }
tmatheson-arm wrote:
These attributes are not actually matched against anything, is there any point
testing them?
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
https://github.com/tmatheson-arm commented: It's really hard to tell what is changing here because the existing tests are so non-specific. https://github.com/llvm/llvm-project/pull/97761 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -4210,9 +4192,7 @@ void CodeGenModule::emitMultiVersionFunctions() {
return cast(Func);
};
-bool HasDefaultDecl = !FD->isTargetVersionMultiVersion();
-bool ShouldEmitResolver =
-!getContext().getTargetInfo().getTriple().isAArch64();
+bool ShouldEmitResolver = !getTarget().getTriple().isAArch64();
tmatheson-arm wrote:
```suggestion
// For AArch64, a resolver is only emitted if a function marked
target(default))
// is present and defined in this TU. For other architectures it is always
emitted.
bool ShouldEmitResolver = !getTarget().getTriple().isAArch64();
```
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
https://github.com/tmatheson-arm edited https://github.com/llvm/llvm-project/pull/97761 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (once we have seen the default definition).
+__attribute__((target_version("aes"))) void fmv(void) {}
+void caller(void) { fmv(); }
+__attribute__((target_version("default"))) void fmv(void) {}
tmatheson-arm wrote:
How does it demonstrate this? The unmangled symbol doesn't appear in the
output, as far as I can see.
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -4224,10 +4204,8 @@ void CodeGenModule::emitMultiVersionFunctions() {
llvm::Function *Func = createFunction(CurFD);
Options.emplace_back(Func, TA->getArchitecture(), Feats);
} else if (const auto *TVA = CurFD->getAttr()) {
-bool HasDefaultDef = TVA->isDefaultVersion() &&
- CurFD->doesThisDeclarationHaveABody();
-HasDefaultDecl |= TVA->isDefaultVersion();
-ShouldEmitResolver |= (CurFD->isUsed() || HasDefaultDef);
+ShouldEmitResolver |= (TVA->isDefaultVersion() &&
+ CurFD->doesThisDeclarationHaveABody());
tmatheson-arm wrote:
```suggestion
if (TVA->isDefaultVersion() &&
CurFD->doesThisDeclarationHaveABody())
ShouldEmitResolver = true;
```
https://github.com/llvm/llvm-project/pull/97761
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[clang] [FMV][AArch64] Do not emit ifunc resolver on use. (PR #97761)
@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (once we have seen the default definition).
+__attribute__((target_version("aes"))) void fmv(void) {}
+void caller(void) { fmv(); }
+__attribute__((target_version("default"))) void fmv(void) {}
tmatheson-arm wrote:
I think we want to test the observable behaviour, not whatever is happening
internally. The test doesn't actually check the internals anyway, besides that
it doesn't crash. i.e. I would expect the comment to be something like:
> Test that an ifunc is generated and used when `default` is defined after the
> first use of the function
If we want to check the other case you mentioned, and
`update_cc_test_checks.py` can't generate a test for it automatically, it
should still be tested but it will have to be manually written.
https://github.com/llvm/llvm-project/pull/97761
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