[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
tianqing marked an inline comment as done.
Closed by commit rG12fa608af44a: [X86] Add CRC32 feature. (authored by 
tianqing).

Changed prior to commit:
  https://reviews.llvm.org/D105462?vs=368795=370866#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105462/new/

https://reviews.llvm.org/D105462

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/crc32intrin.h
  clang/lib/Headers/ia32intrin.h
  clang/lib/Headers/smmintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-crc-builtins.c
  clang/test/CodeGen/attr-cpuspecific.c
  clang/test/CodeGen/attr-target-crc32-x86.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-mcrc32.c
  clang/test/Driver/x86-mgeneral-regs-only-crc32.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/crc32-target-feature.ll
  llvm/test/CodeGen/X86/function-subtarget-features.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/stack-folding-int-sse42.ll

Index: llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
===
--- llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
+++ llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+pclmul < %s | FileCheck %s
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+crc32,+pclmul < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
Index: llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
===
--- llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
+++ llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X86,SSE,X86-SSE
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX512
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X64,SSE,X64-SSE
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx 

[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing marked an inline comment as done.
tianqing added inline comments.



Comment at: clang/lib/Basic/Targets/X86.cpp:160
+  // enabled.
+  I = Features.find("sse4.2");
+  if (I != Features.end() && I->getValue() &&

craig.topper wrote:
> I guess I don't understand why this is coded differently than mmx, popcnt, 
> and xsave?
Well, I just found they're functionally equivalent.


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[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 368795.
tianqing marked an inline comment as done.
tianqing added a comment.

Use existing code in X86.cpp


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105462/new/

https://reviews.llvm.org/D105462

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/crc32intrin.h
  clang/lib/Headers/ia32intrin.h
  clang/lib/Headers/smmintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-crc-builtins.c
  clang/test/CodeGen/attr-cpuspecific.c
  clang/test/CodeGen/attr-target-crc32-x86.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-mcrc32.c
  clang/test/Driver/x86-mgeneral-regs-only-crc32.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/crc32-target-feature.ll
  llvm/test/CodeGen/X86/function-subtarget-features.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/stack-folding-int-sse42.ll

Index: llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
===
--- llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
+++ llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+pclmul < %s | FileCheck %s
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+crc32,+pclmul < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
Index: llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
===
--- llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
+++ llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X86,SSE,X86-SSE
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX512
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X64,SSE,X64-SSE
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | 

[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing marked an inline comment as done.
tianqing added inline comments.



Comment at: clang/lib/Basic/Targets/X86.cpp:158
 
+  // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly set.
+  I = Features.find("sse4.2");

craig.topper wrote:
> Why doesn't this say "not explicitly disabled" like the others above?
Actually what I mean was "not explicitly enabled or disabled".



Comment at: clang/lib/Headers/ia32intrin.h:19
 #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))
 #define __DEFAULT_FN_ATTRS_SSE42 __attribute__((__always_inline__, 
__nodebug__, __target__("sse4.2")))
+#define __DEFAULT_FN_ATTRS_CRC32 __attribute__((__always_inline__, 
__nodebug__, __target__("crc32")))

craig.topper wrote:
> Is __DEFAULT_FN_ATTRS_SSE42 dead now?
Yes.



Comment at: clang/lib/Headers/immintrin.h:518
+defined(__CRC32__)
+#include 
+#endif

pengfei wrote:
> Should it be better to move together with "include "?
I removed this block because it's already in x86gprintrin.h



Comment at: clang/lib/Headers/smmintrin.h:2358
-///operand \a __D.
-static __inline__ unsigned int __DEFAULT_FN_ATTRS
-_mm_crc32_u8(unsigned int __C, unsigned char __D)

craig.topper wrote:
> Was min vector width incorrectly being applied to these before?
I think so.


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[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 368793.
tianqing added a comment.

Address review comments.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/crc32intrin.h
  clang/lib/Headers/ia32intrin.h
  clang/lib/Headers/smmintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-crc-builtins.c
  clang/test/CodeGen/attr-cpuspecific.c
  clang/test/CodeGen/attr-target-crc32-x86.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-mcrc32.c
  clang/test/Driver/x86-mgeneral-regs-only-crc32.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/crc32-target-feature.ll
  llvm/test/CodeGen/X86/function-subtarget-features.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/stack-folding-int-sse42.ll

Index: llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
===
--- llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
+++ llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+pclmul < %s | FileCheck %s
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+crc32,+pclmul < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
Index: llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
===
--- llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
+++ llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X86,SSE,X86-SSE
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX512
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X64,SSE,X64-SSE
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX512
 

[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing added inline comments.



Comment at: llvm/lib/Support/X86TargetParser.cpp:531
 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;

pengfei wrote:
> hjl.tools wrote:
> > pengfei wrote:
> > > Can we let `ImpliedFeaturesSSE4_1 = FeatureSSSE3 | FeaturesCRC32` so that 
> > > we don't need to add `crc32` on sse4.1 and above?
> > SSE4.1 implies CRC32.  But CRC32 shouldn't imply SSE4.1.
> Yes. The constexpr here means `FeaturesSSE4_1` implies both `FeatureSSSE3` 
> and `FeaturesCRC32`.
CRC32 was added in SSE4.2.

In LLVM this implication relationship is bidirectional, that is:

* -msse4.2 implies -mcrc32
* -mcrc32 doesn't implies -msse4.2.
* -mno-sse4.2 doesn't implies -mno-crc32.
* But -mno-crc32 also implies -mno-sse4.2.


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[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing added inline comments.



Comment at: clang/lib/Basic/Targets/X86.cpp:159
+  // Enable CRC32 if SSE4.2 is enabled.
+  // NOTE: In conformance with GCC behavior, CRC32 is still available even if
+  // it's explicitly disabled.

pengfei wrote:
> hjl.tools wrote:
> > craig.topper wrote:
> > > hjl.tools wrote:
> > > > tianqing wrote:
> > > > > craig.topper wrote:
> > > > > > This doesn't seem to be true. It causes gcc to crash. 
> > > > > > https://godbolt.org/z/39rEbsejh
> > > > > Well I was using GCC 11.1, it compiles.
> > > > > 
> > > > > The way I see it, crash means a bug (not surprising since it's 
> > > > > trunk), and can be interpreted as incompletely defined behavior until 
> > > > > it's fixed.
> > > > > 
> > > > > Some tests on GCC trunk:
> > > > > 1. -msse4.2: Pass - sse4.2 enables crc32.
> > > > > 2. -mcrc32 -mno-sse4.2: Pass - no-sse4.2 doesn't disable crc32.
> > > > > 3. -msse4.2 -mno-sse4.2: Error - no-sse4.2 disables crc32.
> > > > > 4. -mno-crc32 -msse4.2: Crash - undefined behavior
> > > > > 5. -msse4.2 -mno-crc32: Crash - undefined behavior
> > > > > 
> > > > > 
> > > > > It's hard to extract some consistent underlying logic from the GCC 
> > > > > results.
> > > > I posted a patch: 
> > > > https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575741.html
> > > @hjl.tools does that turn the crash into making -mno-crc32 into making 
> > > crc32 instruction disabled?
> > Correct.  GCC issues an error now.
> So we don't align with GCC regarding "1. -msse4.2: Pass - sse4.2 enables 
> crc32."?
It's aligned, see clang/test/Driver/x86-mcrc32.c.


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[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing marked 2 inline comments as done.
tianqing added inline comments.



Comment at: clang/lib/Headers/crc32intrin.h:31
+static __inline__ unsigned int __DEFAULT_FN_ATTRS
+_mm_crc32_u8(unsigned int __C, unsigned char __D)
+{

pengfei wrote:
> ditto.
Not sure about this one. We've been consistently using this brace placement in 
intrinsic headers.


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[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 368589.
tianqing added a comment.

- Update behavior of -msse4.2 option.
- Add test for -msse4.2 and -mno-crc32.
- Fix some format error.


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/crc32intrin.h
  clang/lib/Headers/ia32intrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/smmintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-crc-builtins.c
  clang/test/CodeGen/attr-cpuspecific.c
  clang/test/CodeGen/attr-target-crc32-x86.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-mcrc32.c
  clang/test/Driver/x86-mgeneral-regs-only-crc32.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/crc32-target-feature.ll
  llvm/test/CodeGen/X86/function-subtarget-features.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/stack-folding-int-sse42.ll

Index: llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
===
--- llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
+++ llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+pclmul < %s | FileCheck %s
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+crc32,+pclmul < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
Index: llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
===
--- llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
+++ llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X86,SSE,X86-SSE
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX512
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X64,SSE,X64-SSE
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin 

[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing added inline comments.



Comment at: clang/lib/Basic/Targets/X86.cpp:159
+  // Enable CRC32 if SSE4.2 is enabled.
+  // NOTE: In conformance with GCC behavior, CRC32 is still available even if
+  // it's explicitly disabled.

craig.topper wrote:
> This doesn't seem to be true. It causes gcc to crash. 
> https://godbolt.org/z/39rEbsejh
Well I was using GCC 11.1, it compiles.

The way I see it, crash means a bug (not surprising since it's trunk), and can 
be interpreted as incompletely defined behavior until it's fixed.

Some tests on GCC trunk:
1. -msse4.2: Pass - sse4.2 enables crc32.
2. -mcrc32 -mno-sse4.2: Pass - no-sse4.2 doesn't disable crc32.
3. -msse4.2 -mno-sse4.2: Error - no-sse4.2 disables crc32.
4. -mno-crc32 -msse4.2: Crash - undefined behavior
5. -msse4.2 -mno-crc32: Crash - undefined behavior


It's hard to extract some consistent underlying logic from the GCC results.


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[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 360338.
tianqing added a comment.
Herald added a subscriber: jfb.

Instead of using ImpliedFeatures, manually enable CRC32 in presence of SSE4.2.

This should mimic GCC better.


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/crc32intrin.h
  clang/lib/Headers/ia32intrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/smmintrin.h
  clang/test/CodeGen/X86/x86-crc-builtins.c
  clang/test/CodeGen/attr-cpuspecific.c
  clang/test/CodeGen/attr-target-crc32-x86.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-mgeneral-regs-only-crc32.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/crc32-target-feature.ll
  llvm/test/CodeGen/X86/function-subtarget-features.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/stack-folding-int-sse42.ll

Index: llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
===
--- llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
+++ llvm/test/CodeGen/X86/stack-folding-int-sse42.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+pclmul < %s | FileCheck %s
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+sse4.2,+aes,+crc32,+pclmul < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-unknown"
Index: llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
===
--- llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
+++ llvm/test/CodeGen/X86/sse42-intrinsics-x86.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X86,SSE,X86-SSE
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X86,AVX,X86-AVX,X86-AVX512
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=X64,SSE,X64-SSE
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX1
-; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=X64,AVX,X64-AVX,X64-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X86-SSE
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X86-AVX,X86-AVX512
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.2,-crc32 -show-mc-encoding | FileCheck %s --check-prefixes=SSE,X64-SSE
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=AVX,X64-AVX,X64-AVX1
+; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin 

[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:84
   "Enable SSE 4.2 instructions",
-  [FeatureSSE41]>;
+  [FeatureSSE41, FeatureCRC32]>;
 // The MMX subtarget feature is separate from the rest of the SSE features

craig.topper wrote:
> Doesn't this make -mno-crc32 disable sse4.2? Is that what we want?
> 
> Or should we be doing this like popcnt where we loosely enable it at the end 
> of X86TargetInfo::initFeatureMap
It does. But it's not a big deal in this case. The scenario described in the 
commit message doesn't require crc32 capable to be disabled separately.


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[PATCH] D105462: [X86] Add CRC32 feature.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
Herald added subscribers: dexonsmith, dang, pengfei, hiraditya, mgorny.
tianqing requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

d8faf03807ac 
 
implemented general-regs-only for X86 by disabling all features
with vector instructions. But the CRC32 instruction in SSE4.2 ISA, which uses
only GPRs, also becomes unavailable. This patch adds a CRC32 feature for this
instruction and allows it to be used with general-regs-only.


Repository:
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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/crc32intrin.h
  clang/lib/Headers/ia32intrin.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/smmintrin.h
  clang/test/CodeGen/X86/x86-crc-builtins.c
  clang/test/CodeGen/attr-cpuspecific.c
  clang/test/CodeGen/attr-target-crc32-x86.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-mgeneral-regs-only-crc32.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
  llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
  llvm/test/CodeGen/X86/crc32-target-feature.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel-x86_64.ll
  llvm/test/CodeGen/X86/sse42-intrinsics-x86_64.ll

Index: llvm/test/CodeGen/X86/crc32-target-feature.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/crc32-target-feature.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+
+define i32 @test1(i32 %a, i8 %b) nounwind #0 {
+; CHECK-LABEL: test1:
+; CHECK: crc32b
+  %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
+  ret i32 %tmp
+}
+
+define i32 @test2(i32 %a, i8 %b) nounwind #1 {
+; CHECK-LABEL: test2:
+; CHECK: crc32b
+  %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
+  ret i32 %tmp
+}
+
+define i32 @test3(i32 %a, i8 %b) nounwind #2 {
+; CHECK-LABEL: test3:
+; CHECK: crc32b
+  %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
+  ret i32 %tmp
+}
+
+define i32 @test4(i32 %a, i8 %b) nounwind #3 {
+; CHECK-LABEL: test4:
+; CHECK: crc32b
+  %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
+  ret i32 %tmp
+}
+
+define i32 @test5(i32 %a, i8 %b) nounwind #4 {
+; CHECK-LABEL: test5:
+; CHECK: crc32b
+  %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
+  ret i32 %tmp
+}
+
+declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
+
+attributes #0 = { "target-features"="+sse,+sse2,+sse4.2" }
+attributes #1 = { "target-features"="+crc32" }
+attributes #2 = { "target-features"="+cx8,+fxsr,-3dnow,-3dnowa,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxvnni,-f16c,-fma,-fma4,-gfni,-kl,-mmx,-pclmul,-sha,-sse,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-x87,-xop,+crc32" }
+attributes #3 = { "target-features"="+crc32,+cx8,+fxsr,-3dnow,-3dnowa,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxvnni,-f16c,-fma,-fma4,-gfni,-kl,-mmx,-pclmul,-sha,-sse,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-x87,-xop" }
+attributes #4 = { "target-features"="+avx2" }
Index: llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
===
--- llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
+++ llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
@@ -1,4 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+crc32 -show-mc-encoding | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse4.2 -show-mc-encoding | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s

[PATCH] D103943: [X86] Add -mgeneral-regs-only support.

[Wang Tianqing via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd8faf03807ac: [X86] Add -mgeneral-regs-only support. 
(authored by tianqing).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Driver/ToolChains/Arch/X86.cpp
  clang/test/CodeGen/attr-target-general-regs-only-x86.c
  clang/test/Driver/x86-mgeneral-regs-only.c

Index: clang/test/Driver/x86-mgeneral-regs-only.c
===
--- /dev/null
+++ clang/test/Driver/x86-mgeneral-regs-only.c
@@ -0,0 +1,26 @@
+// Test the -mgeneral-regs-only option on x86
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
+// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
+
+// CMD-BEFORE: "-target-feature" "+avx2"
+// CMD: "-target-feature" "-x87"
+// CMD: "-target-feature" "-mmx"
+// CMD: "-target-feature" "-sse"
+// CMD-AFTER: "-target-feature" "+avx2"
+
+void foo() { }
+
+// IR-GPR: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
+// IR-AVX2: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"
Index: clang/test/CodeGen/attr-target-general-regs-only-x86.c
===
--- /dev/null
+++ clang/test/CodeGen/attr-target-general-regs-only-x86.c
@@ -0,0 +1,14 @@
+// Test general-regs-only target attribute on x86
+
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define{{.*}} void @f() [[GPR_ATTRS:#[0-9]+]]
+void __attribute__((target("general-regs-only"))) f() { }
+// CHECK: define{{.*}} void @f_before() [[GPR_ATTRS:#[0-9]+]]
+void __attribute__((target("avx2,general-regs-only"))) f_before() { }
+// CHECK: define{{.*}} void @f_after() [[AVX2_ATTRS:#[0-9]+]]
+void __attribute__((target("general-regs-only,avx2"))) f_after() { }
+
+// CHECK: attributes [[GPR_ATTRS]] = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
+// CHECK: attributes [[AVX2_ATTRS]] = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"
Index: clang/lib/Driver/ToolChains/Arch/X86.cpp
===
--- clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -213,5 +213,24 @@
 
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
-  handleTargetFeaturesGroup(Args, Features, options::OPT_m_x86_Features_Group);
+  for (const Arg *A : Args.filtered(options::OPT_m_x86_Features_Group,
+options::OPT_mgeneral_regs_only)) {
+StringRef Name = A->getOption().getName();
+A->claim();
+
+// Skip over "-m".
+assert(Name.startswith("m") && "Invalid feature name.");
+Name = Name.substr(1);
+
+// Replace -mgeneral-regs-only with -x87, -mmx, -sse
+if (A->getOption().getID() == options::OPT_mgeneral_regs_only) {
+  Features.insert(Features.end(), {"-x87", 

[PATCH] D103943: [X86] Add -mgeneral-regs-only support.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing marked an inline comment as done.
tianqing added inline comments.



Comment at: clang/include/clang/Driver/Options.td:3214
 
-def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, 
Group,
-  HelpText<"Generate code which only uses the general purpose registers 
(AArch64 only)">;
+def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group,
+  HelpText<"Generate code which only uses the general purpose registers 
(AArch64/x86 only)">;

pengfei wrote:
> Will this change affect AArch64 or other targets expect AArch64 and x86?
No, using this option on other targets gives "argument unused during 
compilation" warning.



Comment at: clang/lib/Basic/Targets/X86.cpp:120
 
-  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
+  std::vector UpdatedFeaturesVec;
+  for (const auto& Feature : FeaturesVec) {

pengfei wrote:
> Why do we need to expand it again after we handling in driver?
The driver handles command line options, and this handles "target" attributes.
Just adding "+general-regs-only" in the driver also works. But it's not in 
OPT_m_x86_Features_Group, and current handleTargetFeaturesGroup will ignore it 
so we still have to copy its code, not much of a difference.

(Note AArch64 only supports options)



Comment at: clang/lib/Basic/Targets/X86.cpp:136-158
   // Can't do this earlier because we need to be able to explicitly enable
   // or disable these features and the things that they depend upon.
 
   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
   auto I = Features.find("sse4.2");
   if (I != Features.end() && I->getValue() &&
+  llvm::find(UpdatedFeaturesVec, "-popcnt") == UpdatedFeaturesVec.end())

pengfei wrote:
> Shouldn't this be simply skipped under "general-regs-only"?
It's still about order of options. Seeing a "general-regs-only" doesn't mean 
the function is really GPR only, we have to apply all options in order and 
check the result.



Comment at: clang/lib/Driver/ToolChains/Arch/X86.cpp:216-235
+  for (const Arg *A : Args.filtered(options::OPT_m_x86_Features_Group,
+options::OPT_mgeneral_regs_only)) {
+StringRef Name = A->getOption().getName();
+A->claim();
+
+// Skip over "-m".
+assert(Name.startswith("m") && "Invalid feature name.");

pengfei wrote:
> Why we need copy the code here? Can it be simply use:
> ```
> if (Args.getLastArg(options::OPT_mgeneral_regs_only))
>   Features.insert(Features.end(), {"-x87", "-mmx", "-sse"});
> handleTargetFeaturesGroup(Args, Features, options::OPT_m_x86_Features_Group);
> ```
To make sure later options override earlier ones. This is how GCC behaves.

This is demonstrated in the "GPR" and "AVX2" check lines of the new tests.



Comment at: clang/test/CodeGen/attr-target-general-regs-only-x86.c:14
+// CHECK: attributes [[GPR_ATTRS]] = { {{.*}} 
"target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
+// CHECK: attributes [[AVX2_ATTRS]] = { {{.*}} 
"target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"

pengfei wrote:
> Why we have a `-avx512f` when enabling `avx2`?
See llvm::X86::updateImpliedFeatures(), enabling a feature will enable all 
features it depends on, disabling a feature also disables all features 
depending on it. This is "target feature inheritance" mentioned in Simon's 
comment.


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[PATCH] D103943: [X86] Add -mgeneral-regs-only support.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 353536.
tianqing added a comment.

Fix lint comment.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Driver/ToolChains/Arch/X86.cpp
  clang/test/CodeGen/attr-target-general-regs-only-x86.c
  clang/test/Driver/x86-mgeneral-regs-only.c

Index: clang/test/Driver/x86-mgeneral-regs-only.c
===
--- /dev/null
+++ clang/test/Driver/x86-mgeneral-regs-only.c
@@ -0,0 +1,26 @@
+// Test the -mgeneral-regs-only option on x86
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
+// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
+
+// CMD-BEFORE: "-target-feature" "+avx2"
+// CMD: "-target-feature" "-x87"
+// CMD: "-target-feature" "-mmx"
+// CMD: "-target-feature" "-sse"
+// CMD-AFTER: "-target-feature" "+avx2"
+
+void foo() { }
+
+// IR-GPR: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
+// IR-AVX2: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"
Index: clang/test/CodeGen/attr-target-general-regs-only-x86.c
===
--- /dev/null
+++ clang/test/CodeGen/attr-target-general-regs-only-x86.c
@@ -0,0 +1,14 @@
+// Test general-regs-only target attribute on x86
+
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define{{.*}} void @f() [[GPR_ATTRS:#[0-9]+]]
+void __attribute__((target("general-regs-only"))) f() { }
+// CHECK: define{{.*}} void @f_before() [[GPR_ATTRS:#[0-9]+]]
+void __attribute__((target("avx2,general-regs-only"))) f_before() { }
+// CHECK: define{{.*}} void @f_after() [[AVX2_ATTRS:#[0-9]+]]
+void __attribute__((target("general-regs-only,avx2"))) f_after() { }
+
+// CHECK: attributes [[GPR_ATTRS]] = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
+// CHECK: attributes [[AVX2_ATTRS]] = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"
Index: clang/lib/Driver/ToolChains/Arch/X86.cpp
===
--- clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -213,5 +213,24 @@
 
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
-  handleTargetFeaturesGroup(Args, Features, options::OPT_m_x86_Features_Group);
+  for (const Arg *A : Args.filtered(options::OPT_m_x86_Features_Group,
+options::OPT_mgeneral_regs_only)) {
+StringRef Name = A->getOption().getName();
+A->claim();
+
+// Skip over "-m".
+assert(Name.startswith("m") && "Invalid feature name.");
+Name = Name.substr(1);
+
+// Replace -mgeneral-regs-only with -x87, -mmx, -sse
+if (A->getOption().getID() == options::OPT_mgeneral_regs_only) {
+  Features.insert(Features.end(), {"-x87", "-mmx", "-sse"});
+  continue;
+}
+
+bool IsNegative = Name.startswith("no-");
+if (IsNegative)
+  Name = Name.substr(3);
+

[PATCH] D103943: [X86] Add -mgeneral-regs-only support.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing added a comment.

In D103943#2812638 , @RKSimon wrote:

> I don't know much about target feature inheritance - does this guarantee that 
> the entire sse/avx/avx512 level chain is correctly disabled?

setFeatureEnabled queries ImpliedFeatures to disable all dependent features.


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[PATCH] D103943: [X86] Add -mgeneral-regs-only support.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 352616.
tianqing added a comment.

Respect order of options.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Driver/ToolChains/Arch/X86.cpp
  clang/test/CodeGen/attr-target-general-regs-only-x86.c
  clang/test/Driver/x86-mgeneral-regs-only.c

Index: clang/test/Driver/x86-mgeneral-regs-only.c
===
--- /dev/null
+++ clang/test/Driver/x86-mgeneral-regs-only.c
@@ -0,0 +1,26 @@
+// Test the -mgeneral-regs-only option on x86
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefix=CMD %s
+// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-BEFORE %s
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 %s -### 2>&1 | FileCheck --check-prefixes=CMD,CMD-AFTER %s
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target i386-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mavx2 -mgeneral-regs-only -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-GPR %s
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only -mavx2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefix=IR-AVX2 %s
+
+// CMD-BEFORE: "-target-feature" "+avx2"
+// CMD: "-target-feature" "-x87"
+// CMD: "-target-feature" "-mmx"
+// CMD: "-target-feature" "-sse"
+// CMD-AFTER: "-target-feature" "+avx2"
+
+void foo() { }
+
+// IR-GPR: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
+// IR-AVX2: attributes {{.*}} = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"
Index: clang/test/CodeGen/attr-target-general-regs-only-x86.c
===
--- /dev/null
+++ clang/test/CodeGen/attr-target-general-regs-only-x86.c
@@ -0,0 +1,14 @@
+// Test general-regs-only target attribute on x86
+
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define{{.*}} void @f() [[GPR_ATTRS:#[0-9]+]]
+void __attribute__((target("general-regs-only"))) f() { }
+// CHECK: define{{.*}} void @f_before() [[GPR_ATTRS:#[0-9]+]]
+void __attribute__((target("avx2,general-regs-only"))) f_before() { }
+// CHECK: define{{.*}} void @f_after() [[AVX2_ATTRS:#[0-9]+]]
+void __attribute__((target("general-regs-only,avx2"))) f_after() { }
+
+// CHECK: attributes [[GPR_ATTRS]] = { {{.*}} "target-features"="{{.*}}-avx{{.*}}-avx2{{.*}}-avx512f{{.*}}-sse{{.*}}-sse2{{.*}}-ssse3{{.*}}-x87{{.*}}"
+// CHECK: attributes [[AVX2_ATTRS]] = { {{.*}} "target-features"="{{.*}}+avx{{.*}}+avx2{{.*}}+sse{{.*}}+sse2{{.*}}+ssse3{{.*}}-avx512f{{.*}}-x87{{.*}}"
Index: clang/lib/Driver/ToolChains/Arch/X86.cpp
===
--- clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -213,5 +213,24 @@
 
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
-  handleTargetFeaturesGroup(Args, Features, options::OPT_m_x86_Features_Group);
+  for (const Arg *A : Args.filtered(options::OPT_m_x86_Features_Group,
+options::OPT_mgeneral_regs_only)) {
+StringRef Name = A->getOption().getName();
+A->claim();
+
+// Skip over "-m".
+assert(Name.startswith("m") && "Invalid feature name.");
+Name = Name.substr(1);
+
+// Replace -mgeneral-regs-only with -x87, -mmx, -sse
+if (A->getOption().getID() == options::OPT_mgeneral_regs_only) {
+  Features.insert(Features.end(), {"-x87", "-mmx", "-sse"});
+  continue;
+}
+
+bool IsNegative = Name.startswith("no-");
+if (IsNegative)
+  Name = Name.substr(3);
+

[PATCH] D103943: [X86] Add -mgeneral-regs-only support.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
Herald added a subscriber: dang.
tianqing requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103943

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Driver/ToolChains/Arch/X86.cpp
  clang/test/CodeGen/attr-target-general-regs-only-x86.c
  clang/test/Driver/x86-mgeneral-regs-only.c


Index: clang/test/Driver/x86-mgeneral-regs-only.c
===
--- /dev/null
+++ clang/test/Driver/x86-mgeneral-regs-only.c
@@ -0,0 +1,8 @@
+// Test the -mgeneral-regs-only option on x86
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 
| FileCheck %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only %s -### 
2>&1 | FileCheck %s
+
+// CHECK: "-target-feature" "-x87"
+// CHECK: "-target-feature" "-mmx"
+// CHECK: "-target-feature" "-sse"
Index: clang/test/CodeGen/attr-target-general-regs-only-x86.c
===
--- /dev/null
+++ clang/test/CodeGen/attr-target-general-regs-only-x86.c
@@ -0,0 +1,8 @@
+// Test general-regs-only target attribute on x86
+
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm %s -o - | 
FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | 
FileCheck %s
+
+void __attribute__((target("general-regs-only"))) foo() { }
+
+// CHECK: "target-features"="{{.*}}-mmx{{.*}}-sse{{.*}}-x87{{.*}}"
Index: clang/lib/Driver/ToolChains/Arch/X86.cpp
===
--- clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -142,6 +142,12 @@
   Features.push_back("+ssse3");
   }
 
+  if (Args.getLastArg(options::OPT_mgeneral_regs_only)) {
+Features.push_back("-x87");
+Features.push_back("-mmx");
+Features.push_back("-sse");
+  }
+
   // Translate the high level `-mretpoline` flag to the specific target feature
   // flags. We also detect if the user asked for retpoline external thunks but
   // failed to ask for retpolines themselves (through any of the different
Index: clang/lib/Basic/Targets/X86.cpp
===
--- clang/lib/Basic/Targets/X86.cpp
+++ clang/lib/Basic/Targets/X86.cpp
@@ -142,6 +142,17 @@
   llvm::find(FeaturesVec, "-xsave") == FeaturesVec.end())
 Features["xsave"] = true;
 
+  I = Features.find("general-regs-only");
+  if (I != Features.end()) {
+bool HasGeneralRegsOnly = I->getValue();
+Features.erase(I);
+if (HasGeneralRegsOnly) {
+  setFeatureEnabled(Features, "x87", false);
+  setFeatureEnabled(Features, "mmx", false);
+  setFeatureEnabled(Features, "sse", false);
+}
+  }
+
   return true;
 }
 
@@ -865,6 +876,7 @@
   .Case("fma4", true)
   .Case("fsgsbase", true)
   .Case("fxsr", true)
+  .Case("general-regs-only", true)
   .Case("gfni", true)
   .Case("hreset", true)
   .Case("invpcid", true)
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3197,8 +3197,8 @@
 " volatile bit-field width is dictated by the field container 
type. (ARM only).">>,
   Group;
 
-def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, 
Group,
-  HelpText<"Generate code which only uses the general purpose registers 
(AArch64 only)">;
+def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group,
+  HelpText<"Generate code which only uses the general purpose registers 
(AArch64/x86 only)">;
 def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
   Group,
   HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;


Index: clang/test/Driver/x86-mgeneral-regs-only.c
===
--- /dev/null
+++ clang/test/Driver/x86-mgeneral-regs-only.c
@@ -0,0 +1,8 @@
+// Test the -mgeneral-regs-only option on x86
+
+// RUN: %clang -target i386-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck %s
+// RUN: %clang -target x86_64-unknown-linux-gnu -mgeneral-regs-only %s -### 2>&1 | FileCheck %s
+
+// CHECK: "-target-feature" "-x87"
+// CHECK: "-target-feature" "-mmx"
+// CHECK: "-target-feature" "-sse"
Index: clang/test/CodeGen/attr-target-general-regs-only-x86.c
===
--- /dev/null
+++ clang/test/CodeGen/attr-target-general-regs-only-x86.c
@@ -0,0 +1,8 @@
+// Test general-regs-only target attribute on x86
+
+// RUN: %clang_cc1 -triple i386-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+
+void 

[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing marked an inline comment as done.
tianqing added a comment.

Does anyone has further comments?


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[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 335980.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99708/new/

https://reviews.llvm.org/D99708

Files:
  clang/lib/Headers/uintrintrin.h
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll

Index: llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
@@ -0,0 +1,171 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp --no_x86_scrub_rip
+; RUN: llc < %s | FileCheck %s -check-prefixes=CHECK-USER
+; RUN: llc -O0 < %s | FileCheck %s -check-prefixes=CHECK0-USER
+; RUN: llc -code-model=kernel < %s | FileCheck %s -check-prefixes=CHECK-KERNEL
+; RUN: llc -O0 -code-model=kernel < %s | FileCheck %s -check-prefixes=CHECK0-KERNEL
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.__uintr_frame = type { i64, i64, i64 }
+
+; #include 
+;
+; void
+; __attribute__ ((interrupt))
+; test_uintr_isr_cc_empty(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+; }
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_empty(%struct.__uintr_frame* nocapture byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-USER-LABEL: test_uintr_isr_cc_empty:
+; CHECK-USER:   # %bb.0: # %entry
+; CHECK-USER-NEXT:pushq %rax
+; CHECK-USER-NEXT:cld
+; CHECK-USER-NEXT:addq $16, %rsp
+; CHECK-USER-NEXT:uiret
+;
+; CHECK0-USER-LABEL: test_uintr_isr_cc_empty:
+; CHECK0-USER:   # %bb.0: # %entry
+; CHECK0-USER-NEXT:pushq %rax
+; CHECK0-USER-NEXT:cld
+; CHECK0-USER-NEXT:addq $16, %rsp
+; CHECK0-USER-NEXT:uiret
+;
+; CHECK-KERNEL-LABEL: test_uintr_isr_cc_empty:
+; CHECK-KERNEL:   # %bb.0: # %entry
+; CHECK-KERNEL-NEXT:pushq %rax
+; CHECK-KERNEL-NEXT:cld
+; CHECK-KERNEL-NEXT:addq $16, %rsp
+; CHECK-KERNEL-NEXT:iretq
+;
+; CHECK0-KERNEL-LABEL: test_uintr_isr_cc_empty:
+; CHECK0-KERNEL:   # %bb.0: # %entry
+; CHECK0-KERNEL-NEXT:pushq %rax
+; CHECK0-KERNEL-NEXT:cld
+; CHECK0-KERNEL-NEXT:addq $16, %rsp
+; CHECK0-KERNEL-NEXT:iretq
+entry:
+  ret void
+}
+
+; unsigned long long g_rip;
+; unsigned long long g_rflags;
+; unsigned long long g_rsp;
+; unsigned long long g_uirrv;
+;
+; void
+; __attribute__((interrupt))
+; test_uintr_isr_cc_args(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+;   g_rip = frame->rip;
+;   g_rflags = frame->rflags;
+;   g_rsp = frame->rsp;
+;   g_uirrv = uirrv;
+; }
+@g_rip = dso_local local_unnamed_addr global i64 0, align 8
+@g_rflags = dso_local local_unnamed_addr global i64 0, align 8
+@g_rsp = dso_local local_unnamed_addr global i64 0, align 8
+@g_uirrv = dso_local local_unnamed_addr global i64 0, align 8
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_args(%struct.__uintr_frame* nocapture readonly byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-USER-LABEL: test_uintr_isr_cc_args:
+; CHECK-USER:   # %bb.0: # %entry
+; CHECK-USER-NEXT:pushq %rax
+; CHECK-USER-NEXT:pushq %rax
+; CHECK-USER-NEXT:pushq %rdx
+; CHECK-USER-NEXT:pushq %rcx
+; CHECK-USER-NEXT:cld
+; CHECK-USER-NEXT:movq 32(%rsp), %rax
+; CHECK-USER-NEXT:movq 40(%rsp), %rcx
+; CHECK-USER-NEXT:movq 48(%rsp), %rdx
+; CHECK-USER-NEXT:movq %rcx, g_rip(%rip)
+; CHECK-USER-NEXT:movq %rdx, g_rflags(%rip)
+; CHECK-USER-NEXT:movq 56(%rsp), %rcx
+; CHECK-USER-NEXT:movq %rcx, g_rsp(%rip)
+; CHECK-USER-NEXT:movq %rax, g_uirrv(%rip)
+; CHECK-USER-NEXT:popq %rcx
+; CHECK-USER-NEXT:popq %rdx
+; CHECK-USER-NEXT:popq %rax
+; CHECK-USER-NEXT:addq $16, %rsp
+; CHECK-USER-NEXT:uiret
+;
+; CHECK0-USER-LABEL: test_uintr_isr_cc_args:
+; CHECK0-USER:   # %bb.0: # %entry
+; CHECK0-USER-NEXT:pushq %rax
+; CHECK0-USER-NEXT:pushq %rax
+; CHECK0-USER-NEXT:pushq %rdx
+; CHECK0-USER-NEXT:pushq %rcx
+; CHECK0-USER-NEXT:cld
+; CHECK0-USER-NEXT:movq 32(%rsp), %rax
+; CHECK0-USER-NEXT:leaq 40(%rsp), %rcx
+; CHECK0-USER-NEXT:movq (%rcx), %rdx
+; CHECK0-USER-NEXT:movq %rdx, g_rip(%rip)
+; CHECK0-USER-NEXT:movq 8(%rcx), %rdx
+; CHECK0-USER-NEXT:movq %rdx, g_rflags(%rip)
+; CHECK0-USER-NEXT:movq 16(%rcx), %rcx
+; CHECK0-USER-NEXT:movq %rcx, g_rsp(%rip)
+; CHECK0-USER-NEXT:movq %rax, g_uirrv(%rip)
+; CHECK0-USER-NEXT:popq %rcx
+; CHECK0-USER-NEXT:popq %rdx
+; CHECK0-USER-NEXT:popq %rax
+; CHECK0-USER-NEXT:addq $16, %rsp
+; CHECK0-USER-NEXT:uiret
+;
+; CHECK-KERNEL-LABEL: test_uintr_isr_cc_args:
+; CHECK-KERNEL:   # %bb.0: # %entry
+; CHECK-KERNEL-NEXT:pushq %rax
+; CHECK-KERNEL-NEXT:pushq %rax
+; CHECK-KERNEL-NEXT:pushq %rdx
+; CHECK-KERNEL-NEXT:pushq %rcx
+; CHECK-KERNEL-NEXT:cld
+; CHECK-KERNEL-NEXT:movq 32(%rsp), %rax
+; 

[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 335426.
tianqing added a comment.

Update handling of -mcmodel=kernel.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D99708/new/

https://reviews.llvm.org/D99708

Files:
  clang/lib/Headers/uintrintrin.h
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll

Index: llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s | FileCheck %s -check-prefixes=CHECK,CHECK-USER
+; RUN: llc -O0 < %s | FileCheck %s -check-prefixes=CHECK0,CHECK0-USER
+; RUN: llc -code-model=kernel < %s | FileCheck %s -check-prefixes=CHECK,CHECK-KERNEL
+; RUN: llc -O0 -code-model=kernel < %s | FileCheck %s -check-prefixes=CHECK0,CHECK0-KERNEL
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.__uintr_frame = type { i64, i64, i64 }
+
+; #include 
+;
+; void
+; __attribute__ ((interrupt))
+; test_uintr_isr_cc_empty(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+; }
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_empty(%struct.__uintr_frame* nocapture byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-LABEL: test_uintr_isr_cc_empty:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:cld
+; CHECK-NEXT:addq $16, %rsp
+; CHECK-USER:uiret
+; CHECK-KERNEL:  iretq
+;
+; CHECK0-LABEL: test_uintr_isr_cc_empty:
+; CHECK0:   # %bb.0: # %entry
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:cld
+; CHECK0-NEXT:addq $16, %rsp
+; CHECK0-USER:uiret
+; CHECK0-KERNEL:  iretq
+entry:
+  ret void
+}
+
+; unsigned long long g_rip;
+; unsigned long long g_rflags;
+; unsigned long long g_rsp;
+; unsigned long long g_uirrv;
+;
+; void
+; __attribute__((interrupt))
+; test_uintr_isr_cc_args(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+;   g_rip = frame->rip;
+;   g_rflags = frame->rflags;
+;   g_rsp = frame->rsp;
+;   g_uirrv = uirrv;
+; }
+@g_rip = dso_local local_unnamed_addr global i64 0, align 8
+@g_rflags = dso_local local_unnamed_addr global i64 0, align 8
+@g_rsp = dso_local local_unnamed_addr global i64 0, align 8
+@g_uirrv = dso_local local_unnamed_addr global i64 0, align 8
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_args(%struct.__uintr_frame* nocapture readonly byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-LABEL: test_uintr_isr_cc_args:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:pushq %rdx
+; CHECK-NEXT:pushq %rcx
+; CHECK-NEXT:cld
+; CHECK-NEXT:movq 32(%rsp), %rax
+; CHECK-NEXT:movq 40(%rsp), %rcx
+; CHECK-NEXT:movq 48(%rsp), %rdx
+; CHECK-NEXT:movq %rcx, g_rip(%rip)
+; CHECK-NEXT:movq %rdx, g_rflags(%rip)
+; CHECK-NEXT:movq 56(%rsp), %rcx
+; CHECK-NEXT:movq %rcx, g_rsp(%rip)
+; CHECK-NEXT:movq %rax, g_uirrv(%rip)
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:popq %rdx
+; CHECK-NEXT:popq %rax
+; CHECK-NEXT:addq $16, %rsp
+; CHECK-USER:uiret
+; CHECK-KERNEL:  iretq
+;
+; CHECK0-LABEL: test_uintr_isr_cc_args:
+; CHECK0:   # %bb.0: # %entry
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:pushq %rdx
+; CHECK0-NEXT:pushq %rcx
+; CHECK0-NEXT:cld
+; CHECK0-NEXT:movq 32(%rsp), %rax
+; CHECK0-NEXT:leaq 40(%rsp), %rcx
+; CHECK0-NEXT:movq (%rcx), %rdx
+; CHECK0-NEXT:movq %rdx, g_rip(%rip)
+; CHECK0-NEXT:movq 8(%rcx), %rdx
+; CHECK0-NEXT:movq %rdx, g_rflags(%rip)
+; CHECK0-NEXT:movq 16(%rcx), %rcx
+; CHECK0-NEXT:movq %rcx, g_rsp(%rip)
+; CHECK0-NEXT:movq %rax, g_uirrv(%rip)
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:popq %rdx
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:addq $16, %rsp
+; CHECK0-USER:uiret
+; CHECK0-KERNEL:  iretq
+entry:
+  %rip = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 0
+  %0 = load i64, i64* %rip, align 8
+  store i64 %0, i64* @g_rip, align 8
+  %rflags = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 1
+  %1 = load i64, i64* %rflags, align 8
+  store i64 %1, i64* @g_rflags, align 8
+  %rsp = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 2
+  %2 = load i64, i64* %rsp, align 8
+  store i64 %2, i64* @g_rsp, align 8
+  store i64 %uirrv, i64* @g_uirrv, align 8
+  ret void
+}
+
+attributes #0 = { nofree norecurse nounwind willreturn "disable-tail-calls"="true" "frame-pointer"="none" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+uintr" "tune-cpu"="generic" }
Index: llvm/lib/Target/X86/X86ExpandPseudo.cpp
===
--- llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ 

[PATCH] D99708: [X86] Enable compilation of user interrupt handlers.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
tianqing added reviewers: pengfei, LuoYuanke, craig.topper.
Herald added a subscriber: hiraditya.
tianqing requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Add __uintr_frame structure and use UIRET instruction for functions with
x86 interrupt calling convention when UINTR is present.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D99708

Files:
  clang/lib/Headers/uintrintrin.h
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll

Index: llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
@@ -0,0 +1,111 @@
+; RUN: llc < %s | FileCheck %s
+; RUN: llc -O0 < %s | FileCheck %s -check-prefix=CHECK0
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.__uintr_frame = type { i64, i64, i64 }
+
+; #include 
+;
+; void
+; __attribute__ ((interrupt))
+; test_uintr_isr_cc_empty(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+; }
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_empty(%struct.__uintr_frame* nocapture byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-LABEL: test_uintr_isr_cc_empty:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:cld
+; CHECK-NEXT:addq $16, %rsp
+; CHECK-NEXT:uiret
+;
+; CHECK0-LABEL: test_uintr_isr_cc_empty:
+; CHECK0:   # %bb.0: # %entry
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:cld
+; CHECK0-NEXT:addq $16, %rsp
+; CHECK0-NEXT:uiret
+entry:
+  ret void
+}
+
+; unsigned long long g_rip;
+; unsigned long long g_rflags;
+; unsigned long long g_rsp;
+; unsigned long long g_uirrv;
+;
+; void
+; __attribute__((interrupt))
+; test_uintr_isr_cc_args(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+;   g_rip = frame->rip;
+;   g_rflags = frame->rflags;
+;   g_rsp = frame->rsp;
+;   g_uirrv = uirrv;
+; }
+@g_rip = dso_local local_unnamed_addr global i64 0, align 8
+@g_rflags = dso_local local_unnamed_addr global i64 0, align 8
+@g_rsp = dso_local local_unnamed_addr global i64 0, align 8
+@g_uirrv = dso_local local_unnamed_addr global i64 0, align 8
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_args(%struct.__uintr_frame* nocapture readonly byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-LABEL: test_uintr_isr_cc_args:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:pushq %rdx
+; CHECK-NEXT:pushq %rcx
+; CHECK-NEXT:cld
+; CHECK-NEXT:movq 32(%rsp), %rax
+; CHECK-NEXT:movq 40(%rsp), %rcx
+; CHECK-NEXT:movq 48(%rsp), %rdx
+; CHECK-NEXT:movq %rcx, g_rip(%rip)
+; CHECK-NEXT:movq %rdx, g_rflags(%rip)
+; CHECK-NEXT:movq 56(%rsp), %rcx
+; CHECK-NEXT:movq %rcx, g_rsp(%rip)
+; CHECK-NEXT:movq %rax, g_uirrv(%rip)
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:popq %rdx
+; CHECK-NEXT:popq %rax
+; CHECK-NEXT:addq $16, %rsp
+; CHECK-NEXT:uiret
+;
+; CHECK0-LABEL: test_uintr_isr_cc_args:
+; CHECK0:   # %bb.0: # %entry
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:pushq %rax
+; CHECK0-NEXT:pushq %rdx
+; CHECK0-NEXT:pushq %rcx
+; CHECK0-NEXT:cld
+; CHECK0-NEXT:movq 32(%rsp), %rax
+; CHECK0-NEXT:leaq 40(%rsp), %rcx
+; CHECK0-NEXT:movq (%rcx), %rdx
+; CHECK0-NEXT:movq %rdx, g_rip(%rip)
+; CHECK0-NEXT:movq 8(%rcx), %rdx
+; CHECK0-NEXT:movq %rdx, g_rflags(%rip)
+; CHECK0-NEXT:movq 16(%rcx), %rcx
+; CHECK0-NEXT:movq %rcx, g_rsp(%rip)
+; CHECK0-NEXT:movq %rax, g_uirrv(%rip)
+; CHECK0-NEXT:popq %rcx
+; CHECK0-NEXT:popq %rdx
+; CHECK0-NEXT:popq %rax
+; CHECK0-NEXT:addq $16, %rsp
+; CHECK0-NEXT:uiret
+entry:
+  %rip = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 0
+  %0 = load i64, i64* %rip, align 8
+  store i64 %0, i64* @g_rip, align 8
+  %rflags = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 1
+  %1 = load i64, i64* %rflags, align 8
+  store i64 %1, i64* @g_rflags, align 8
+  %rsp = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 2
+  %2 = load i64, i64* %rsp, align 8
+  store i64 %2, i64* @g_rsp, align 8
+  store i64 %uirrv, i64* @g_uirrv, align 8
+  ret void
+}
+
+attributes #0 = { nofree norecurse nounwind willreturn "disable-tail-calls"="true" "frame-pointer"="none" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+uintr" "tune-cpu"="generic" }
Index: llvm/lib/Target/X86/X86ExpandPseudo.cpp
===
--- llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -316,7 +316,9 @@
 

[PATCH] D89301: [X86] Add user-level interrupt instructions

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 299317.
tianqing added a comment.
Herald added a subscriber: dexonsmith.

Address review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89301/new/

https://reviews.llvm.org/D89301

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/uintrintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-uintr-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/predefined-arch-macros.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/uintr-intrinsics.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -2018,3 +2018,35 @@
 // CHECK: hreset
 // CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
 hreset $1
+
+// CHECK: uiret
+// CHECK: encoding: [0xf3,0x0f,0x01,0xec]
+uiret
+
+// CHECK: clui
+// CHECK: encoding: [0xf3,0x0f,0x01,0xee]
+clui
+
+// CHECK: stui
+// CHECK: encoding: [0xf3,0x0f,0x01,0xef]
+stui
+
+// CHECK: testui
+// CHECK: encoding: [0xf3,0x0f,0x01,0xed]
+testui
+
+// CHECK: senduipi %rax
+// CHECK: encoding: [0xf3,0x0f,0xc7,0xf0]
+senduipi %rax
+
+// CHECK: senduipi %rdx
+// CHECK: encoding: [0xf3,0x0f,0xc7,0xf2]
+senduipi %rdx
+
+// CHECK: senduipi %r8
+// CHECK: encoding: [0xf3,0x41,0x0f,0xc7,0xf0]
+senduipi %r8
+
+// CHECK: senduipi %r13
+// CHECK: encoding: [0xf3,0x41,0x0f,0xc7,0xf5]
+senduipi %r13
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -715,3 +715,27 @@
 
 # CHECK: hreset $1
 0xf3 0x0f 0x3a 0xf0 0xc0 0x01
+
+# CHECK: uiret
+0xf3,0x0f,0x01,0xec
+
+# CHECK: clui
+0xf3,0x0f,0x01,0xee
+
+# CHECK: stui
+0xf3,0x0f,0x01,0xef
+
+# CHECK: testui
+0xf3,0x0f,0x01,0xed
+
+# CHECK: senduipi %rax
+0xf3,0x0f,0xc7,0xf0
+
+# CHECK: senduipi %rdx
+0xf3,0x0f,0xc7,0xf2
+
+# CHECK: senduipi %r8
+0xf3,0x41,0x0f,0xc7,0xf0
+
+# CHECK: senduipi %r13
+0xf3,0x41,0x0f,0xc7,0xf5
Index: llvm/test/CodeGen/X86/uintr-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/uintr-intrinsics.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+uintr | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+uintr | FileCheck %s --check-prefix=X32
+
+define i8 @test_uintr(i64 %arg) {
+; X64-LABEL: test_uintr:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:clui
+; X64-NEXT:stui
+; X64-NEXT:senduipi %rdi
+; X64-NEXT:testui
+; X64-NEXT:setb %al
+; X64-NEXT:retq
+
+; X32-LABEL: test_uintr:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:clui
+; X32-NEXT:stui
+; X32-NEXT:senduipi %rdi
+; X32-NEXT:testui
+; X32-NEXT:setb %al
+; X32-NEXT:retq
+entry:
+  call void @llvm.x86.clui()
+  call void @llvm.x86.stui()
+  call void @llvm.x86.senduipi(i64 %arg)
+  %0 = call i8 @llvm.x86.testui()
+  ret i8 %0
+}
+
+declare void @llvm.x86.clui()
+declare void @llvm.x86.stui()
+declare i8 @llvm.x86.testui()
+declare void @llvm.x86.senduipi(i64 %arg)
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -415,6 +415,9 @@
   bool HasAMXBF16 = false;
   bool HasAMXINT8 = false;
 
+  /// Processor supports User Level Interrupt instructions
+  bool HasUINTR = false;
+
   /// Processor has a single uop BEXTR implementation.
   bool HasFastBEXTR = false;
 
@@ -742,6 +745,7 @@
   bool hasHRESET() const { return HasHRESET; }
   bool hasSERIALIZE() const { return HasSERIALIZE; }
   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
+  bool hasUINTR() const { return HasUINTR; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
   bool useRetpolineIndirectBranches() const {
 return UseRetpolineIndirectBranches;
Index: llvm/lib/Target/X86/X86InstrInfo.td
===
--- 

[PATCH] D89301: [X86] Add user-level interrupt instructions

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
Herald added subscribers: llvm-commits, cfe-commits, dang, hiraditya, mgorny.
Herald added projects: clang, LLVM.
tianqing requested review of this revision.

For more details about these instructions, please refer to the latest
ISE document:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89301

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86_64.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/uintrintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/x86-uintr-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/uintr-intrinsics.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -2018,3 +2018,35 @@
 // CHECK: hreset
 // CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
 hreset $1
+
+// CHECK: uiret
+// CHECK: encoding: [0xf3,0x0f,0x01,0xec]
+uiret
+
+// CHECK: clui
+// CHECK: encoding: [0xf3,0x0f,0x01,0xee]
+clui
+
+// CHECK: stui
+// CHECK: encoding: [0xf3,0x0f,0x01,0xef]
+stui
+
+// CHECK: testui
+// CHECK: encoding: [0xf3,0x0f,0x01,0xed]
+testui
+
+// CHECK: senduipi %rax
+// CHECK: encoding: [0xf3,0x0f,0xc7,0xf0]
+senduipi %rax
+
+// CHECK: senduipi %rdx
+// CHECK: encoding: [0xf3,0x0f,0xc7,0xf2]
+senduipi %rdx
+
+// CHECK: senduipi %r8
+// CHECK: encoding: [0xf3,0x41,0x0f,0xc7,0xf0]
+senduipi %r8
+
+// CHECK: senduipi %r13
+// CHECK: encoding: [0xf3,0x41,0x0f,0xc7,0xf5]
+senduipi %r13
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -715,3 +715,27 @@
 
 # CHECK: hreset $1
 0xf3 0x0f 0x3a 0xf0 0xc0 0x01
+
+# CHECK: uiret
+0xf3,0x0f,0x01,0xec
+
+# CHECK: clui
+0xf3,0x0f,0x01,0xee
+
+# CHECK: stui
+0xf3,0x0f,0x01,0xef
+
+# CHECK: testui
+0xf3,0x0f,0x01,0xed
+
+# CHECK: senduipi %rax
+0xf3,0x0f,0xc7,0xf0
+
+# CHECK: senduipi %rdx
+0xf3,0x0f,0xc7,0xf2
+
+# CHECK: senduipi %r8
+0xf3,0x41,0x0f,0xc7,0xf0
+
+# CHECK: senduipi %r13
+0xf3,0x41,0x0f,0xc7,0xf5
Index: llvm/test/CodeGen/X86/uintr-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/uintr-intrinsics.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+uintr | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+uintr | FileCheck %s --check-prefix=X32
+
+define i8 @test_uintr(i64 %arg) {
+; X64-LABEL: test_uintr:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:clui
+; X64-NEXT:stui
+; X64-NEXT:senduipi %rdi
+; X64-NEXT:testui
+; X64-NEXT:setb %al
+; X64-NEXT:retq
+
+; X32-LABEL: test_uintr:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:clui
+; X32-NEXT:stui
+; X32-NEXT:senduipi %rdi
+; X32-NEXT:testui
+; X32-NEXT:setb %al
+; X32-NEXT:retq
+entry:
+  call void @llvm.x86.clui()
+  call void @llvm.x86.stui()
+  call void @llvm.x86.senduipi(i64 %arg)
+  %0 = call i8 @llvm.x86.testui()
+  ret i8 %0
+}
+
+declare void @llvm.x86.clui()
+declare void @llvm.x86.stui()
+declare i8 @llvm.x86.testui()
+declare void @llvm.x86.senduipi(i64 %arg)
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -415,6 +415,9 @@
   bool HasAMXBF16 = false;
   bool HasAMXINT8 = false;
 
+  /// Processor supports User Level Interrupt instructions
+  bool HasUINTR = false;
+
   /// Processor has a single uop BEXTR implementation.
   bool HasFastBEXTR = false;
 
@@ -742,6 +745,7 @@
   bool hasHRESET() const { return HasHRESET; }
   bool hasSERIALIZE() const { return HasSERIALIZE; }
   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
+  bool hasUINTR() const { return HasUINTR; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
   bool useRetpolineIndirectBranches() const {
 return UseRetpolineIndirectBranches;
Index: 

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 256170.
tianqing added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
+
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -400,6 +400,9 @@
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
+  /// Processor supports TSXLDTRK instruction
+  bool HasTSXLDTRK = false;
+
   /// 

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing added a comment.

Can I just check it in after the rebase?


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[PATCH] D77205: [X86] Add TSXLDTRK instructions.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 254693.
tianqing added a comment.

Updated to resolve conflicts with https://reviews.llvm.org/D77193.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -400,6 +400,9 @@
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
+  /// Processor supports TSXLDTRK instruction
+  bool HasTSXLDTRK = 

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 254694.
tianqing added a comment.

Removed extra "//".


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77205/new/

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1881,3 +1881,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10880,3 +10880,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1033,3 +1033,11 @@
 // CHECK: serialize
 // CHECK: encoding: [0x0f,0x01,0xe8]
 serialize
+
+// CHECK: xsusldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: xresldtrk
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -694,3 +694,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -946,3 +946,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -839,3 +839,9 @@
 
 # CHECK: serialize
 0x0f 0x01 0xe8
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
+
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -400,6 +400,9 @@
   /// Processor supports SERIALIZE instruction
   bool HasSERIALIZE = false;
 
+  /// Processor supports TSXLDTRK instruction
+  bool HasTSXLDTRK = false;
+
   /// Processor has a single uop BEXTR 

[PATCH] D77205: [X86] Add TSXLDTRK instructions.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
tianqing added reviewers: craig.topper, RKSimon, LuoYuanke.
Herald added subscribers: cfe-commits, hiraditya, mgorny.
Herald added a project: clang.

For more details about these instructions, please refer to the latest ISE 
document: 
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77205

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/tsxldtrkintrin.h
  clang/test/CodeGen/x86-tsxldtrk-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1877,3 +1877,9 @@
 // CHECK: enqcmds 485498096, %rax
 // CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
 enqcmds 485498096, %rax
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10876,3 +10876,9 @@
 // CHECK: enqcmds 8128(%bx,%di), %ax
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
 enqcmds 8128(%bx,%di), %ax
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1029,3 +1029,9 @@
 // CHECK: enqcmds (%edi), %edi
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x3f]
 enqcmds (%edi), %edi
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe8]
+xsusldtrk
+
+// CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
+xresldtrk
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -691,3 +691,9 @@
 
 # CHECK: enqcmds 485498096, %rax
 0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -943,3 +943,9 @@
 
 # CHECK: enqcmds 8128(%bx,%di), %ax
 0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -836,3 +836,9 @@
 
 # CHECK: enqcmds (%edi), %edi
 0x67,0xf3,0x0f,0x38,0xf8,0x3f
+
+# CHECK: xsusldtrk
+0xf2 0x0f 0x01 0xe8
+
+# CHECK: xresldtrk
+0xf2 0x0f 0x01 0xe9
Index: llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/tsxldtrk-intrinsic.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+tsxldtrk | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+tsxldtrk | FileCheck %s --check-prefix=X32
+
+define void @test_tsxldtrk() {
+; X64-LABEL: test_tsxldtrk:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:xsusldtrk
+; X64-NEXT:xresldtrk
+; X64-NEXT:retq
+;
+; X86-LABEL: test_tsxldtrk:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:xsusldtrk
+; X86-NEXT:xresldtrk
+; X86-NEXT:retl
+;
+; X32-LABEL: test_tsxldtrk:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:xsusldtrk
+; X32-NEXT:xresldtrk
+; X32-NEXT:retq
+entry:
+   call void @llvm.x86.xsusldtrk()
+   call void @llvm.x86.xresldtrk()
+   ret void
+}
+
+declare void @llvm.x86.xsusldtrk()
+declare void @llvm.x86.xresldtrk()
\ No 

[PATCH] D77193: [X86] Add SERIALIZE instruction.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 254114.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77193/new/

https://reviews.llvm.org/D77193

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/serializeintrin.h
  clang/test/CodeGen/x86-serialize-intrin.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/serialize-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1877,3 +1877,7 @@
 // CHECK: enqcmds 485498096, %rax
 // CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
 enqcmds 485498096, %rax
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10876,3 +10876,7 @@
 // CHECK: enqcmds 8128(%bx,%di), %ax
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
 enqcmds 8128(%bx,%di), %ax
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1029,3 +1029,7 @@
 // CHECK: enqcmds (%edi), %edi
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x3f]
 enqcmds (%edi), %edi
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -691,3 +691,6 @@
 
 # CHECK: enqcmds 485498096, %rax
 0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -943,3 +943,6 @@
 
 # CHECK: enqcmds 8128(%bx,%di), %ax
 0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -836,3 +836,6 @@
 
 # CHECK: enqcmds (%edi), %edi
 0x67,0xf3,0x0f,0x38,0xf8,0x3f
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/CodeGen/X86/serialize-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/serialize-intrinsic.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86_64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+serialize | FileCheck %s --check-prefix=X32
+
+define void @test_serialize() {
+; X86_64-LABEL: test_serialize:
+; X86_64:   # %bb.0: # %entry
+; X86_64-NEXT:serialize
+; X86_64-NEXT:retq
+;
+; X86-LABEL: test_serialize:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:serialize
+; X86-NEXT:retl
+;
+; X32-LABEL: test_serialize:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:serialize
+; X32-NEXT:retq
+entry:
+  call void @llvm.x86.serialize()
+  ret void
+}
+
+declare void @llvm.x86.serialize()
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -397,6 +397,9 @@
   /// Processor supports PCONFIG instruction
   bool HasPCONFIG = false;
 
+  /// Processor supports SERIALIZE instruction
+  bool HasSERIALIZE = false;
+
   /// Processor has a single uop BEXTR implementation.
   bool HasFastBEXTR = false;
 
@@ -706,6 +709,7 @@
   bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
   bool hasINVPCID() const { return HasINVPCID; }
   bool hasENQCMD() const { return HasENQCMD; }
+  bool hasSERIALIZE() const { return HasSERIALIZE; 

[PATCH] D77193: [X86] Add SERIALIZE instruction.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
tianqing added reviewers: craig.topper, RKSimon, LuoYuanke.
Herald added subscribers: cfe-commits, hiraditya, mgorny.
Herald added a project: clang.

For more details about this instruction, please refer to the latest ISE 
document: 
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77193

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/serializeintrin.h
  clang/test/CodeGen/x86-serialize-intrin.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/serialize-intrinsic.ll
  llvm/test/MC/Disassembler/X86/x86-16.txt
  llvm/test/MC/Disassembler/X86/x86-32.txt
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/x86-16.s
  llvm/test/MC/X86/x86-32-coverage.s
  llvm/test/MC/X86/x86-64.s

Index: llvm/test/MC/X86/x86-64.s
===
--- llvm/test/MC/X86/x86-64.s
+++ llvm/test/MC/X86/x86-64.s
@@ -1877,3 +1877,7 @@
 // CHECK: enqcmds 485498096, %rax
 // CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
 enqcmds 485498096, %rax
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/X86/x86-32-coverage.s
===
--- llvm/test/MC/X86/x86-32-coverage.s
+++ llvm/test/MC/X86/x86-32-coverage.s
@@ -10876,3 +10876,7 @@
 // CHECK: enqcmds 8128(%bx,%di), %ax
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
 enqcmds 8128(%bx,%di), %ax
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/X86/x86-16.s
===
--- llvm/test/MC/X86/x86-16.s
+++ llvm/test/MC/X86/x86-16.s
@@ -1029,3 +1029,7 @@
 // CHECK: enqcmds (%edi), %edi
 // CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x3f]
 enqcmds (%edi), %edi
+
+// CHECK: serialize
+// CHECK: encoding: [0x0f,0x01,0xe8]
+serialize
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -691,3 +691,6 @@
 
 # CHECK: enqcmds 485498096, %rax
 0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/MC/Disassembler/X86/x86-32.txt
===
--- llvm/test/MC/Disassembler/X86/x86-32.txt
+++ llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -943,3 +943,6 @@
 
 # CHECK: enqcmds 8128(%bx,%di), %ax
 0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/MC/Disassembler/X86/x86-16.txt
===
--- llvm/test/MC/Disassembler/X86/x86-16.txt
+++ llvm/test/MC/Disassembler/X86/x86-16.txt
@@ -836,3 +836,6 @@
 
 # CHECK: enqcmds (%edi), %edi
 0x67,0xf3,0x0f,0x38,0xf8,0x3f
+
+# CHECK: serialize
+0x0f 0x01 0xe8
Index: llvm/test/CodeGen/X86/serialize-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/serialize-intrinsic.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86_64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+serialize | FileCheck %s --check-prefix=X32
+
+define void @test_serialize() {
+; X86_64-LABEL: test_serialize:
+; X86_64:   # %bb.0: # %entry
+; X86_64-NEXT:serialize
+; X86_64-NEXT:retq
+;
+; X86-LABEL: test_serialize:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:serialize
+; X86-NEXT:retl
+;
+; X32-LABEL: test_serialize:
+; X32:   # %bb.0: # %entry
+; X32-NEXT:serialize
+; X32-NEXT:retq
+entry:
+  call void @llvm.x86.serialize()
+  ret void
+}
+
+declare void @llvm.x86.serialize()
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -397,6 +397,9 @@
   /// Processor supports PCONFIG instruction
   bool HasPCONFIG = false;
 
+  /// Processor supports SERIALIZE instruction
+  bool HasSERIALIZE = false;
+
   /// Processor has a single uop 

[PATCH] D71884: [OpenMP] Fix formatting of OpenMP error message.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing added a comment.

Could someone help commit this patch? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71884/new/

https://reviews.llvm.org/D71884



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[PATCH] D71884: [OpenMP] Fix formatting of OpenMP error message.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
Herald added subscribers: cfe-commits, guansong.
Herald added a reviewer: jdoerfert.
Herald added a project: clang.
tianqing added a reviewer: ABataev.

`getListOfPossibleValues()` formatted incorrectly when there is only one value, 
emitting something like `expected 'conditional' or  in OpenMP clause 
'lastprivate'`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71884

Files:
  clang/lib/Sema/SemaOpenMP.cpp
  clang/test/OpenMP/for_lastprivate_messages.cpp
  clang/test/OpenMP/for_simd_lastprivate_messages.cpp
  clang/test/OpenMP/parallel_for_lastprivate_messages.cpp
  clang/test/OpenMP/parallel_for_simd_lastprivate_messages.cpp
  clang/test/OpenMP/parallel_sections_lastprivate_messages.cpp
  clang/test/OpenMP/sections_lastprivate_messages.cpp
  clang/test/OpenMP/simd_lastprivate_messages.cpp
  clang/test/OpenMP/target_parallel_for_lastprivate_messages.cpp
  clang/test/OpenMP/target_parallel_for_simd_lastprivate_messages.cpp
  clang/test/OpenMP/target_simd_lastprivate_messages.cpp

Index: clang/test/OpenMP/target_simd_lastprivate_messages.cpp
===
--- clang/test/OpenMP/target_simd_lastprivate_messages.cpp
+++ clang/test/OpenMP/target_simd_lastprivate_messages.cpp
@@ -107,6 +107,9 @@
 #pragma omp target simd lastprivate(conditional: s,argc) lastprivate(conditional: // omp45-error 2 {{use of undeclared identifier 'conditional'}} omp50-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp50-error {{expected list item of scalar type in 'lastprivate' clause with 'conditional' modifier}}
   for (int k = 0; k < argc; ++k)
 ++k;
+#pragma omp target simd lastprivate(foo:argc) // omp50-error {{expected 'conditional' in OpenMP clause 'lastprivate'}} omp45-error {{expected ',' or ')' in 'lastprivate' clause}} omp45-error {{expected ')'}} omp45-error {{expected variable name}} omp45-note {{to match this '('}}
+  for (int k = 0; k < argc; ++k)
+++k;
 #pragma omp target simd lastprivate(S1) // expected-error {{'S1' does not refer to a value}}
   for (int k = 0; k < argc; ++k)
 ++k;
Index: clang/test/OpenMP/target_parallel_for_simd_lastprivate_messages.cpp
===
--- clang/test/OpenMP/target_parallel_for_simd_lastprivate_messages.cpp
+++ clang/test/OpenMP/target_parallel_for_simd_lastprivate_messages.cpp
@@ -107,6 +107,9 @@
 #pragma omp target parallel for simd lastprivate(conditional: argc,s) lastprivate(conditional: // omp50-error {{expected expression}} omp45-error 2 {{use of undeclared identifier 'conditional'}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp45-error 2 {{calling a private constructor of class 'S6'}} omp50-error {{expected list item of scalar type in 'lastprivate' clause with 'conditional' modifier}}
   for (int k = 0; k < argc; ++k)
 ++k;
+#pragma omp target parallel for simd lastprivate(foo:argc) // omp50-error {{expected 'conditional' in OpenMP clause 'lastprivate'}} omp45-error {{expected ',' or ')' in 'lastprivate' clause}} omp45-error {{expected ')'}} omp45-error {{expected variable name}} omp45-note {{to match this '('}}
+  for (int k = 0; k < argc; ++k)
+++k;
 #pragma omp target parallel for simd lastprivate(S1) // expected-error {{'S1' does not refer to a value}}
   for (int k = 0; k < argc; ++k)
 ++k;
Index: clang/test/OpenMP/target_parallel_for_lastprivate_messages.cpp
===
--- clang/test/OpenMP/target_parallel_for_lastprivate_messages.cpp
+++ clang/test/OpenMP/target_parallel_for_lastprivate_messages.cpp
@@ -107,6 +107,9 @@
 #pragma omp target parallel for lastprivate(conditional: s,argc) lastprivate(conditional: // omp50-error {{expected expression}} omp45-error 2 {{use of undeclared identifier 'conditional'}} expected-error {{expected ')'}} expected-note {{to match this '('}} omp50-error {{expected list item of scalar type in 'lastprivate' clause with 'conditional' modifier}}
   for (int k = 0; k < argc; ++k)
 ++k;
+#pragma omp target parallel for lastprivate(foo:argc) // omp50-error {{expected 'conditional' in OpenMP clause 'lastprivate'}} omp45-error {{expected ',' or ')' in 'lastprivate' clause}} omp45-error {{expected ')'}} omp45-error {{expected variable name}} omp45-note {{to match this '('}}
+  for (int k = 0; k < argc; ++k)
+++k;
 #pragma omp target parallel for lastprivate(S1) // expected-error {{'S1' does not refer to a value}}
   for (int k = 0; k < argc; ++k)
 ++k;
Index: clang/test/OpenMP/simd_lastprivate_messages.cpp
===
--- clang/test/OpenMP/simd_lastprivate_messages.cpp
+++ clang/test/OpenMP/simd_lastprivate_messages.cpp
@@ -96,6 +96,9 @@
 #pragma omp simd lastprivate(conditional: argc,g) lastprivate(conditional: // omp50-error {{expected expression}} omp45-error 2 

[PATCH] D69792: [NFC] Supress GCC "Bitfield too small to hold all values of enum" warning.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

974c8b7e2fd introduced a warning for GCC:

llvm-project/clang/include/clang/Sema/Overload.h:835:48: warning: 
‘clang::OverloadCandidate::RewriteKind’ is too small to hold all values of 
‘enum clang::OverloadCandidateRewriteKind’

  OverloadCandidateRewriteKind RewriteKind : 2;


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D69792

Files:
  clang/include/clang/Sema/Overload.h
  clang/lib/Sema/SemaOverload.cpp


Index: clang/lib/Sema/SemaOverload.cpp
===
--- clang/lib/Sema/SemaOverload.cpp
+++ clang/lib/Sema/SemaOverload.cpp
@@ -9932,7 +9932,7 @@
 
   std::string FnDesc;
   std::pair FnKindPair =
-  ClassifyOverloadCandidate(S, Cand->FoundDecl, Fn, Cand->RewriteKind,
+  ClassifyOverloadCandidate(S, Cand->FoundDecl, Fn, Cand->getRewriteKind(),
 FnDesc);
 
   Expr *FromExpr = Conv.Bad.FromExpr;
@@ -10502,8 +10502,8 @@
 
   std::string FnDesc;
   std::pair FnKindPair =
-  ClassifyOverloadCandidate(S, Cand->FoundDecl, Callee, Cand->RewriteKind,
-FnDesc);
+  ClassifyOverloadCandidate(S, Cand->FoundDecl, Callee,
+Cand->getRewriteKind(), FnDesc);
 
   S.Diag(Callee->getLocation(), diag::note_ovl_candidate_bad_target)
   << (unsigned)FnKindPair.first << (unsigned)ocs_non_template
@@ -10621,8 +10621,8 @@
 if (Fn->isDeleted()) {
   std::string FnDesc;
   std::pair FnKindPair =
-  ClassifyOverloadCandidate(S, Cand->FoundDecl, Fn, Cand->RewriteKind,
-FnDesc);
+  ClassifyOverloadCandidate(S, Cand->FoundDecl, Fn,
+Cand->getRewriteKind(), FnDesc);
 
   S.Diag(Fn->getLocation(), diag::note_ovl_candidate_deleted)
   << (unsigned)FnKindPair.first << (unsigned)FnKindPair.second << 
FnDesc
@@ -10632,7 +10632,7 @@
 }
 
 // We don't really have anything else to say about viable candidates.
-S.NoteOverloadCandidate(Cand->FoundDecl, Fn, Cand->RewriteKind);
+S.NoteOverloadCandidate(Cand->FoundDecl, Fn, Cand->getRewriteKind());
 return;
   }
 
@@ -10665,7 +10665,7 @@
   case ovl_fail_trivial_conversion:
   case ovl_fail_bad_final_conversion:
   case ovl_fail_final_conversion_not_exact:
-return S.NoteOverloadCandidate(Cand->FoundDecl, Fn, Cand->RewriteKind);
+return S.NoteOverloadCandidate(Cand->FoundDecl, Fn, 
Cand->getRewriteKind());
 
   case ovl_fail_bad_conversion: {
 unsigned I = (Cand->IgnoreObjectArgument ? 1 : 0);
@@ -10676,7 +10676,7 @@
 // FIXME: this currently happens when we're called from SemaInit
 // when user-conversion overload fails.  Figure out how to handle
 // those conditions and diagnose them well.
-return S.NoteOverloadCandidate(Cand->FoundDecl, Fn, Cand->RewriteKind);
+return S.NoteOverloadCandidate(Cand->FoundDecl, Fn, 
Cand->getRewriteKind());
   }
 
   case ovl_fail_bad_target:
Index: clang/include/clang/Sema/Overload.h
===
--- clang/include/clang/Sema/Overload.h
+++ clang/include/clang/Sema/Overload.h
@@ -821,7 +821,7 @@
 CallExpr::ADLCallKind IsADLCandidate : 1;
 
 /// Whether this is a rewritten candidate, and if so, of what kind?
-OverloadCandidateRewriteKind RewriteKind : 2;
+unsigned RewriteKind : 2;
 
 /// FailureKind - The reason why this candidate is not viable.
 /// Actually an OverloadFailureKind.
@@ -841,6 +841,12 @@
   StandardConversionSequence FinalConversion;
 };
 
+/// Get RewriteKind value in OverloadCandidateRewriteKind type (This
+/// function is to workaround the spurious GCC bitfield enum warning)
+OverloadCandidateRewriteKind getRewriteKind() const {
+  return static_cast(RewriteKind);
+}
+
 /// hasAmbiguousConversion - Returns whether this overload
 /// candidate requires an ambiguous conversion or not.
 bool hasAmbiguousConversion() const {


Index: clang/lib/Sema/SemaOverload.cpp
===
--- clang/lib/Sema/SemaOverload.cpp
+++ clang/lib/Sema/SemaOverload.cpp
@@ -9932,7 +9932,7 @@
 
   std::string FnDesc;
   std::pair FnKindPair =
-  ClassifyOverloadCandidate(S, Cand->FoundDecl, Fn, Cand->RewriteKind,
+  ClassifyOverloadCandidate(S, Cand->FoundDecl, Fn, Cand->getRewriteKind(),
 FnDesc);
 
   Expr *FromExpr = Conv.Bad.FromExpr;
@@ -10502,8 +10502,8 @@
 
   std::string FnDesc;
   std::pair FnKindPair =
-  ClassifyOverloadCandidate(S, Cand->FoundDecl, Callee, Cand->RewriteKind,
-FnDesc);
+  ClassifyOverloadCandidate(S, Cand->FoundDecl, Callee,
+Cand->getRewriteKind(), FnDesc);
 
   S.Diag(Callee->getLocation(), 

[PATCH] D62282: [X86] Add ENQCMD intrinsics.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing updated this revision to Diff 202856.
tianqing added a comment.

Added doxygen comments of intrinsics in enqcmdintrin.h.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62282/new/

https://reviews.llvm.org/D62282

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/cpuid.h
  lib/Headers/enqcmdintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/x86-enqcmd-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -468,3 +468,10 @@
 
 // NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1
 
+// RUN: %clang -target i386-unknown-unknown -march=atom -menqcmd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=ENQCMD %s
+
+// ENQCMD: #define __ENQCMD__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mno-enqcmd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOENQCMD %s
+
+// NOENQCMD-NOT: #define __ENQCMD__ 1
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -188,3 +188,8 @@
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512bf16 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-AVX512BF16 %s
 // AVX512BF16: "-target-feature" "+avx512bf16"
 // NO-AVX512BF16: "-target-feature" "-avx512bf16"
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -menqcmd %s -### -o %t.o 2>&1 | FileCheck --check-prefix=ENQCMD %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-enqcmd %s -### -o %t.o 2>&1 | FileCheck --check-prefix=NO-ENQCMD %s
+// ENQCMD: "-target-feature" "+enqcmd"
+// NO-ENQCMD: "-target-feature" "-enqcmd"
Index: test/CodeGen/x86-enqcmd-builtins.c
===
--- /dev/null
+++ test/CodeGen/x86-enqcmd-builtins.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple i386-unknown-unknown -target-feature +enqcmd -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple x86_64-unknown-unknown -target-feature +enqcmd -emit-llvm -o - | FileCheck %s
+
+#include 
+
+int test_enqcmd(void *dst, const void *src) {
+// CHECK-LABEL: @test_enqcmd
+// CHECK: %[[TMP0:.+]] = call i8 @llvm.x86.enqcmd(i8* %{{.+}}, i8* %{{.+}})
+// CHECK: %[[RET:.+]] = zext i8 %[[TMP0]] to i32
+// CHECK: ret i32 %[[RET]]
+return _enqcmd(dst, src);
+}
+
+int test_enqcmds(void *dst, const void *src) {
+// CHECK-LABEL: @test_enqcmds
+// CHECK: %[[TMP0:.+]] = call i8 @llvm.x86.enqcmds(i8* %{{.+}}, i8* %{{.+}})
+// CHECK: %[[RET:.+]] = zext i8 %[[TMP0]] to i32
+// CHECK: ret i32 %[[RET]]
+return _enqcmds(dst, src);
+}
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -431,6 +431,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__ENQCMD__)
+#include 
+#endif
+
 #if defined(_MSC_VER) && __has_extension(gnu_asm)
 /* Define the default attributes for these intrinsics */
 #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))
Index: lib/Headers/enqcmdintrin.h
===
--- /dev/null
+++ lib/Headers/enqcmdintrin.h
@@ -0,0 +1,63 @@
+/*===-- enqcmdintrin.h - enqcmd intrinsics -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __ENQCMDINTRIN_H
+#define __ENQCMDINTRIN_H
+
+/* Define the default attributes for the functions in this file */
+#define _DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __nodebug__, __target__("enqcmd")))
+
+/// Reads 64-byte command pointed by \a __src, formats 64-byte enqueue store
+///data, and performs 64-byte enqueue store to memory pointed by \a __dst.
+///This intrinsics may only be used in User mode.
+///
+/// \headerfile 
+///
+/// This intrinsics corresponds to the  ENQCMD  instruction.
+///
+/// \param __dst
+///Pointer to the destination of the enqueue store.
+/// \param __src
+///Pointer to 64-byte command data.
+/// \returns If the command data is successfully written to \a __dst then 0 is
+///returned. Otherwise 1 is returned.
+static __inline__ int _DEFAULT_FN_ATTRS
+_enqcmd (void *__dst, 

[PATCH] D62282: [X86] Add ENQCMD intrinsics.

[Wang Tianqing via Phabricator via cfe-commits]

tianqing created this revision.
tianqing added reviewers: craig.topper, RKSimon, LuoYuanke, spatel.
Herald added subscribers: cfe-commits, mgorny.
Herald added a project: clang.

For more details about these instructions, please refer to the latest ISE 
document: 
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.


Repository:
  rC Clang

https://reviews.llvm.org/D62282

Files:
  docs/ClangCommandLineReference.rst
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/cpuid.h
  lib/Headers/enqcmdintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/x86-enqcmd-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/x86_target_features.c

Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -458,3 +458,10 @@
 
 // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1
 
+// RUN: %clang -target i386-unknown-unknown -march=atom -menqcmd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=ENQCMD %s
+
+// ENQCMD: #define __ENQCMD__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mno-enqcmd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOENQCMD %s
+
+// NOENQCMD-NOT: #define __ENQCMD__ 1
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -183,3 +183,8 @@
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512bf16 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-AVX512BF16 %s
 // AVX512BF16: "-target-feature" "+avx512bf16"
 // NO-AVX512BF16: "-target-feature" "-avx512bf16"
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -menqcmd %s -### -o %t.o 2>&1 | FileCheck --check-prefix=ENQCMD %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-enqcmd %s -### -o %t.o 2>&1 | FileCheck --check-prefix=NO-ENQCMD %s
+// ENQCMD: "-target-feature" "+enqcmd"
+// NO-ENQCMD: "-target-feature" "-enqcmd"
Index: test/CodeGen/x86-enqcmd-builtins.c
===
--- /dev/null
+++ test/CodeGen/x86-enqcmd-builtins.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple i386-unknown-unknown -target-feature +enqcmd -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple x86_64-unknown-unknown -target-feature +enqcmd -emit-llvm -o - | FileCheck %s
+
+#include 
+
+int test_enqcmd(void *dst, const void *src) {
+// CHECK-LABEL: @test_enqcmd
+// CHECK: %[[TMP0:.+]] = call i8 @llvm.x86.enqcmd(i8* %{{.+}}, i8* %{{.+}})
+// CHECK: %[[RET:.+]] = zext i8 %[[TMP0]] to i32
+// CHECK: ret i32 %[[RET]]
+return _enqcmd(dst, src);
+}
+
+int test_enqcmds(void *dst, const void *src) {
+// CHECK-LABEL: @test_enqcmds
+// CHECK: %[[TMP0:.+]] = call i8 @llvm.x86.enqcmds(i8* %{{.+}}, i8* %{{.+}})
+// CHECK: %[[RET:.+]] = zext i8 %[[TMP0]] to i32
+// CHECK: ret i32 %[[RET]]
+return _enqcmds(dst, src);
+}
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -421,6 +421,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__ENQCMD__)
+#include 
+#endif
+
 #if defined(_MSC_VER) && __has_extension(gnu_asm)
 /* Define the default attributes for these intrinsics */
 #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))
Index: lib/Headers/enqcmdintrin.h
===
--- /dev/null
+++ lib/Headers/enqcmdintrin.h
@@ -0,0 +1,35 @@
+/*===-- enqcmdintrin.h - enqcmd intrinsics -===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===---===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __ENQCMDINTRIN_H
+#define __ENQCMDINTRIN_H
+
+/* Define the default attributes for the functions in this file */
+#define _DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __nodebug__, __target__("enqcmd")))
+
+static __inline__ int _DEFAULT_FN_ATTRS
+_enqcmd (void *__dst, const void *__src)
+{
+  return __builtin_ia32_enqcmd(__dst, __src);
+}
+
+static __inline__ int _DEFAULT_FN_ATTRS
+_enqcmds (void *__dst, const void *__src)
+{
+  return __builtin_ia32_enqcmds(__dst, __src);
+}
+
+#undef _DEFAULT_FN_ATTRS
+
+#endif /* __ENQCMDINTRIN_H */
Index: lib/Headers/cpuid.h
===