[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

2021-04-30 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

2021-04-26 Thread LevyHsu via Phabricator via cfe-commits 
LevyHsu updated this revision to Diff 340705.
LevyHsu added a comment.

1. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
  - All test cases renamed


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBM
+
+declare i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+
+define i64 @bmator64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmator64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmator a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmator64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmator a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+
+define i64 @bmatxor64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmatxor64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatxor a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatxor64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatxor a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatflip.i64(i64 %a)
+
+define i64 @bmatflip64(i64 %a) nounwind {
+; RV64IB-LABEL: bmatflip64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatflip a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatflip64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatflip a0, a0
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatflip.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -934,6 +934,12 @@
 def : PatGprGpr;
 } // Predicates = [HasStdExtZbc]
 
+let Predicates = [HasStdExtZbm, IsRV64] in {
+def : PatGprGpr;
+def : PatGprGpr;
+def : PatGpr;
+} // Predicates = [HasStdExtZbm, IsRV64]
+
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr;
 def : PatGpr;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -89,6 +89,11 @@
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
+  // Zbm
+  def int_riscv_bmator   : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatxor  : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatflip : BitManipGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
@@ -0,0 +1,45 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbm -emit-llvm %s -o - \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBM
+
+// RV64ZBM-LABEL: @bmator(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP2:%.*]] = call i64 @llvm.riscv.bmator.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBM-NEXT:ret i64 [[TMP2]]
+//
+long bmator(long a, long b) {
+  return __builtin_riscv_bmator(a, b);
+}
+
+// RV64ZBM-LABEL: @bmatxor(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+//

[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

2021-04-25 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c:16
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_bmator(a, b);

clmul?


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[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

2021-04-25 Thread LevyHsu via Phabricator via cfe-commits 
LevyHsu created this revision.
LevyHsu added reviewers: craig.topper, kito-cheng, jrtc27, asb, Jim.
LevyHsu added projects: clang, LLVM.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, sabuasal, 
simoncook, johnrusso, rbar, hiraditya.
LevyHsu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.

RV64 ONLY:

  bmator
  bmatxor
  bmatflip


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101248

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbm-intrinsic.ll
@@ -0,0 +1,53 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBM
+
+declare i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+
+define i64 @bmator64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmator64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmator a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmator64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmator a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmator.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+
+define i64 @bmatxor64(i64 %a, i64 %b) nounwind {
+; RV64IB-LABEL: bmatxor64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatxor a0, a0, a1
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatxor64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatxor a0, a0, a1
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatxor.i64(i64 %a, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.bmatflip.i64(i64 %a)
+
+define i64 @bmatflip64(i64 %a) nounwind {
+; RV64IB-LABEL: bmatflip64:
+; RV64IB:   # %bb.0:
+; RV64IB-NEXT:bmatflip a0, a0
+; RV64IB-NEXT:ret
+;
+; RV64IBM-LABEL: bmatflip64:
+; RV64IBM:   # %bb.0:
+; RV64IBM-NEXT:bmatflip a0, a0
+; RV64IBM-NEXT:ret
+  %tmp = call i64 @llvm.riscv.bmatflip.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -934,6 +934,12 @@
 def : PatGprGpr;
 } // Predicates = [HasStdExtZbc]
 
+let Predicates = [HasStdExtZbm, IsRV64] in {
+def : PatGprGpr;
+def : PatGprGpr;
+def : PatGpr;
+} // Predicates = [HasStdExtZbm, IsRV64]
+
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr;
 def : PatGpr;
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -89,6 +89,11 @@
   def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
   def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
 
+  // Zbm
+  def int_riscv_bmator   : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatxor  : BitManipGPRGPRIntrinsics;
+  def int_riscv_bmatflip : BitManipGPRIntrinsics;
+
   // Zbp
   def int_riscv_grev  : BitManipGPRGPRIntrinsics;
   def int_riscv_gorc  : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c
@@ -0,0 +1,45 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbm -emit-llvm %s -o - \
+// RUN: | FileCheck %s  -check-prefix=RV64ZBM
+
+// RV64ZBM-LABEL: @clmul(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:[[B_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBM-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
+// RV64ZBM-NEXT:[[TMP2:%.*]] = call i64 @llvm.riscv.bmator.i64(i64 [[TMP0]], i64 [[TMP1]])
+// RV64ZBM-NEXT:ret i64 [[TMP2]]
+//
+long clmul(long a, long b) {
+  return __builtin_riscv_bmator(a, b);
+}
+
+// RV64ZBM-LABEL: @clmulh(
+// RV64ZBM-NEXT:  entry:
+// RV64ZBM-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+//