[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd40e8091bd1f: [PowerPC] Add PowerPC rotate related builtins
and emit target independent code… (authored by NeHuang).
Changed prior to commit:
https://reviews.llvm.org/D104744?vs=358761&id=358986#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D104744/new/
https://reviews.llvm.org/D104744
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+ // CHECK-LABEL: test_builtin_ppc_rldimi
+ // CHECK: %res = alloca i64, align 8
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+ // CHECK-NEXT: store i64 [[RF]], i64* %res, align 8
+ // CHECK-NEXT: ret void
+
+ /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+ // CHECK-LABEL: test_builtin_ppc_rlwimi
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+ // CHECK-NEXT: store i32 [[RF]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+ // CHECK-LABEL: test_builtin_ppc_rlwnm
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RC:%[0-9]+]] = and i32 [[RB]], 511
+ // CHECK-NEXT: store i32 [[RC]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x1FF = 511*/
+ unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -10,6 +10,8 @@
extern long long lla, llb;
extern int ia, ib;
+extern unsigned int ui;
+extern unsigned long long ull;
void test_trap(void) {
#ifdef __PPC64__
@@ -17,3 +19,27 @@
#endif
__tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
}
+
+void test_builtin_ppc_rldimi() {
+ unsigned int shift;
+ unsigned long long mask;
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
+ res = __bu
[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.
LGTM other than a couple of nits.
Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15064
}
+ case PPC::BI__builtin_ppc_rldimi:
+ case PPC::BI__builtin_ppc_rlwimi: {
Please add a comment describing the emitted code. Something like:
```
// Rotate and insert under mask operation.
// __rlwimi(rs, is, shift, mask)
// rotl(rs, shift) & mask) | (is & ~mask)
```
Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15070
+ Ops[2] = Builder.CreateZExt(Ops[2], Int64Ty);
+Value *shift = Builder.CreateCall(F, {Ops[0], Ops[0], Ops[2]});
+Value *X = Builder.CreateAnd(shift, Ops[3]);
Nit: `s/shift/Shift` to conform to variable naming conventions. Here and
elsewhere.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D104744/new/
https://reviews.llvm.org/D104744
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[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
NeHuang updated this revision to Diff 358761.
NeHuang marked 4 inline comments as done.
NeHuang added a comment.
Address review comments from Nemanja.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D104744/new/
https://reviews.llvm.org/D104744
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+ // CHECK-LABEL: test_builtin_ppc_rldimi
+ // CHECK: %res = alloca i64, align 8
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+ // CHECK-NEXT: store i64 [[RF]], i64* %res, align 8
+ // CHECK-NEXT: ret void
+
+ /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+ // CHECK-LABEL: test_builtin_ppc_rlwimi
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+ // CHECK-NEXT: store i32 [[RF]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+ // CHECK-LABEL: test_builtin_ppc_rlwnm
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RC:%[0-9]+]] = and i32 [[RB]], 511
+ // CHECK-NEXT: store i32 [[RC]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x1FF = 511*/
+ unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -0,0 +1,37 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+ unsigned int shift;
+ unsigned long long mask;
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
+ res = __
[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
nemanjai requested changes to this revision. nemanjai added inline comments. This revision now requires changes to proceed. Comment at: clang/include/clang/Sema/Sema.h:12559 bool SemaBuiltinOSLogFormat(CallExpr *TheCall); + bool CheckPPCisRunOfOnes(CallExpr *TheCall, unsigned ArgNum); + bool CheckPPC64isRunOfOnes(CallExpr *TheCall, unsigned ArgNum); I don't think these names adequately describe what the check is. We are not checking if `PPC/PPC64` is a run of ones. In fact, the concept of a contiguous mask is in no way specific to PPC so we don't really need to differentiate this as a PPC-specific check. Also, the convention seems to be to prefix all names with `Sema`. Let's not part with that convention. Perhaps `SemaValueIsRunOfOnes()` or `SemaArgIsRunOfOnes()`. Comment at: clang/lib/Sema/SemaChecking.cpp:3299 + unsigned Val = Result.getExtValue(); + if (!Val) +return Diag(TheCall->getBeginLoc(), Isn't a zero technically a contiguous run of ones (of length zero)? Comment at: clang/lib/Sema/SemaChecking.cpp:3429 SemaBuiltinConstantArgRange(TheCall, 0, 0, 1); + case PPC::BI__builtin_ppc_rlwnm: +return SemaBuiltinConstantArg(TheCall, 1, Result) || Please describe in a comment why we need to ensure that the argument is a contiguous mask. Comment at: clang/lib/Sema/SemaChecking.cpp:3430 + case PPC::BI__builtin_ppc_rlwnm: +return SemaBuiltinConstantArg(TheCall, 1, Result) || + CheckPPCisRunOfOnes(TheCall, 2); We seem to populate the `Result` here. If we already have the `Result` (i.e. the constant value) can't we just simply check if that is a run of ones? Then we can greatly simplify `CheckPPCisRunOfOnes()` and `CheckPPC64isRunOfOnes()` (and we may not actually need two functions since `Result` will be an `APSInt` that knows how wide it is. We could presumably just have: `bool SemaValueIsRunOfOnes(const APSInt &Val, unsigned Width);` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104744/new/ https://reviews.llvm.org/D104744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
NeHuang added a comment. gentle ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104744/new/ https://reviews.llvm.org/D104744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
NeHuang updated this revision to Diff 354082.
NeHuang added a comment.
- Rebased the patch with ToT and the patch https://reviews.llvm.org/D102875
- Create the patch with all contexts. (Thanks @qiucf)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D104744/new/
https://reviews.llvm.org/D104744
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+ // CHECK-LABEL: test_builtin_ppc_rldimi
+ // CHECK: %res = alloca i64, align 8
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+ // CHECK-NEXT: store i64 [[RF]], i64* %res, align 8
+ // CHECK-NEXT: ret void
+
+ /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+ // CHECK-LABEL: test_builtin_ppc_rlwimi
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+ // CHECK-NEXT: store i32 [[RF]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+ // CHECK-LABEL: test_builtin_ppc_rlwnm
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RC:%[0-9]+]] = and i32 [[RB]], 511
+ // CHECK-NEXT: store i32 [[RC]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x1FF = 511*/
+ unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -0,0 +1,37 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+ unsigned int shift;
+ unsigned long long mask;
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_pp
[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
qiucf added a comment. Please provide context of the patch (`git diff -U999`) :-) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104744/new/ https://reviews.llvm.org/D104744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D104744: [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility
NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added projects: LLVM, clang.
Herald added subscribers: shchenz, kbarton.
NeHuang requested review of this revision.
Herald added a subscriber: cfe-commits.
This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and emit target independent
code for rotate related operations.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D104744
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -0,0 +1,56 @@
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern unsigned int ui;
+extern unsigned long long ull;
+
+void test_builtin_ppc_rldimi() {
+ // CHECK-LABEL: test_builtin_ppc_rldimi
+ // CHECK: %res = alloca i64, align 8
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i64, i64* @ull, align 8
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i64 @llvm.fshl.i64(i64 [[RA]], i64 [[RA]], i64 63)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i64 [[RC]], 72057593769492480
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i64 [[RB]], -72057593769492481
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i64 [[RD]], [[RE]]
+ // CHECK-NEXT: store i64 [[RF]], i64* %res, align 8
+ // CHECK-NEXT: ret void
+
+ /*shift = 63, mask = 0x00FFF000 = 72057593769492480, ~mask = 0xFF000FFF = -72057593769492481*/
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, 63, 0x00FFF000);
+}
+
+void test_builtin_ppc_rlwimi() {
+ // CHECK-LABEL: test_builtin_ppc_rlwimi
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RD:%[0-9]+]] = and i32 [[RC]], 16776960
+ // CHECK-NEXT: [[RE:%[0-9]+]] = and i32 [[RB]], -16776961
+ // CHECK-NEXT: [[RF:%[0-9]+]] = or i32 [[RD]], [[RE]]
+ // CHECK-NEXT: store i32 [[RF]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x00 = 16776960, ~mask = 0xFFFF = -16776961*/
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, 31, 0x00);
+}
+
+void test_builtin_ppc_rlwnm() {
+ // CHECK-LABEL: test_builtin_ppc_rlwnm
+ // CHECK: %res = alloca i32, align 4
+ // CHECK-NEXT: [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+ // CHECK-NEXT: [[RB:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 31)
+ // CHECK-NEXT: [[RC:%[0-9]+]] = and i32 [[RB]], 511
+ // CHECK-NEXT: store i32 [[RC]], i32* %res, align 4
+ // CHECK-NEXT: ret void
+
+ /*shift = 31, mask = 0x1FF = 511*/
+ unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -10,9 +10,32 @@
// RUN: -Wall -Werror -verify %s
extern unsigned int ui;
+extern unsigned long long ull;
void test_builtin_ppc_cmprb() {
int res = __builtin_ppc_cmprb(3, ui, ui); //expected-error {{argument value 3 is outside the valid range [0, 1]}}
}
+void test_builtin_ppc_rldimi() {
+ unsigned int shift;
+ unsigned long long mask;
+ unsigned long long res = __builtin_ppc_rldimi(ull, ull, shift, 7); // expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, mask);// expected-error {{argument to '__builtin_ppc_rldimi' must be a constant integer}}
+ res = __builtin_ppc_rldimi(ull, ull, 63, 0x0F00); // expected-error {{argument 3 value should represent a contiguous bit field}}
+}
+
+void test_builtin_ppc_rlwimi() {
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
+ res = __buil
