[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-19 Thread Albion Fung via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9d4faa8ac3e7: [PowerPC] Implement cmplxl builtins (authored 
by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D107138?vs=365596=367695#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
@@ -226,3 +226,115 @@
 float _Complex testcmplxf(float real, float imag) {
   return __cmplxf(real, imag);
 }
+
+// 64BIT-LABEL: @test_xl_cmplxl(
+// 64BIT-NEXT:  entry:
+// 64BIT-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BIT-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BIT-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BIT-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BIT-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITLE-LABEL: @test_xl_cmplxl(
+// 64BITLE-NEXT:  entry:
+// 64BITLE-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BITLE-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BITLE-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BITLE-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BITLE-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BITLE-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITAIX-LABEL: @test_xl_cmplxl(
+// 64BITAIX-NEXT:  entry:
+// 64BITAIX-NEXT:[[RETVAL:%.*]] = alloca { double, double }, align 4
+// 64BITAIX-NEXT:[[LDA_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:[[LDB_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:store double [[LDA:%.*]], double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:store double [[LDB:%.*]], double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP0:%.*]] = load double, double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP1:%.*]] = load double, double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 0
+// 64BITAIX-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 1
+// 64BITAIX-NEXT:store double [[TMP0]], double* [[RETVAL_REALP]], align 4
+// 64BITAIX-NEXT:store double [[TMP1]], double* [[RETVAL_IMAGP]], align 4
+// 64BITAIX-NEXT:[[TMP2:%.*]] = load { double, double }, { double, double }* [[RETVAL]], align 4
+// 64BITAIX-NEXT:ret { double, double } [[TMP2]]
+//
+// 32BIT-LABEL: @test_xl_cmplxl(
+// 32BIT-NEXT:  entry:
+// 32BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 32BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:[[TMP1:%.*]] = load

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-11 Thread Victor Huang via Phabricator via cfe-commits 
NeHuang accepted this revision.
NeHuang added a comment.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-10 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-10 Thread Albion Fung via Phabricator via cfe-commits 
Conanap updated this revision to Diff 365596.
Conanap added a comment.

Removed unintended change


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
@@ -226,3 +226,115 @@
 float _Complex testcmplxf(float real, float imag) {
   return __cmplxf(real, imag);
 }
+
+// 64BIT-LABEL: @test_xl_cmplxl(
+// 64BIT-NEXT:  entry:
+// 64BIT-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BIT-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BIT-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BIT-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BIT-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITLE-LABEL: @test_xl_cmplxl(
+// 64BITLE-NEXT:  entry:
+// 64BITLE-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BITLE-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BITLE-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BITLE-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BITLE-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BITLE-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITAIX-LABEL: @test_xl_cmplxl(
+// 64BITAIX-NEXT:  entry:
+// 64BITAIX-NEXT:[[RETVAL:%.*]] = alloca { double, double }, align 4
+// 64BITAIX-NEXT:[[LDA_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:[[LDB_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:store double [[LDA:%.*]], double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:store double [[LDB:%.*]], double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP0:%.*]] = load double, double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP1:%.*]] = load double, double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 0
+// 64BITAIX-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 1
+// 64BITAIX-NEXT:store double [[TMP0]], double* [[RETVAL_REALP]], align 4
+// 64BITAIX-NEXT:store double [[TMP1]], double* [[RETVAL_IMAGP]], align 4
+// 64BITAIX-NEXT:[[TMP2:%.*]] = load { double, double }, { double, double }* [[RETVAL]], align 4
+// 64BITAIX-NEXT:ret { double, double } [[TMP2]]
+//
+// 32BIT-LABEL: @test_xl_cmplxl(
+// 32BIT-NEXT:  entry:
+// 32BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 32BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 32BIT-NEXT:[[AGG_RESULT_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[AGG_RESULT:%.*]], i32 0, i32 0
+//

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-09 Thread Albion Fung via Phabricator via cfe-commits 
Conanap updated this revision to Diff 365289.
Conanap marked 3 inline comments as done.
Conanap added a comment.

Merged the test case into the existing cmplx test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
@@ -1,5 +1,5 @@
-// REQUIRES: powerpc-registered-target
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:-emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s --check-prefix=64BIT
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
@@ -226,3 +226,115 @@
 float _Complex testcmplxf(float real, float imag) {
   return __cmplxf(real, imag);
 }
+
+// 64BIT-LABEL: @test_xl_cmplxl(
+// 64BIT-NEXT:  entry:
+// 64BIT-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BIT-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BIT-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BIT-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BIT-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITLE-LABEL: @test_xl_cmplxl(
+// 64BITLE-NEXT:  entry:
+// 64BITLE-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BITLE-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BITLE-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BITLE-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BITLE-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BITLE-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITAIX-LABEL: @test_xl_cmplxl(
+// 64BITAIX-NEXT:  entry:
+// 64BITAIX-NEXT:[[RETVAL:%.*]] = alloca { double, double }, align 4
+// 64BITAIX-NEXT:[[LDA_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:[[LDB_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:store double [[LDA:%.*]], double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:store double [[LDB:%.*]], double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP0:%.*]] = load double, double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP1:%.*]] = load double, double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 0
+// 64BITAIX-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 1
+// 64BITAIX-NEXT:store double [[TMP0]], double* [[RETVAL_REALP]], align 4
+// 64BITAIX-NEXT:store double [[TMP1]], double* [[RETVAL_IMAGP]], align 4
+// 64BITAIX-NEXT:[[TMP2:%.*]] = load { double, double }, { double, double }* [[RETVAL]], align 4
+// 64BITAIX-NEXT:ret { double, double } [[TMP2]]
+//
+// 32BIT-LABEL: @test_xl_cmplxl(
+// 32BIT-NEXT:  entry:
+// 32BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDA:%.*]],

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-07 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

Conanap wrote:
> NeHuang wrote:
> > NeHuang wrote:
> > > `// REQUIRES: powerpc-registered-target`
> > Question: why do we need `-O2` for this builtin?
> > 
> it's not required, but removes a lot of the extra load and stores that make 
> the test cases longer unnecessarily. I can change it to O1 if preferred.
I prefer that front end tests should test what the front end does. The front 
end does not perform optimizations, the optimizer does. So the front end tests 
should not include optimization options (even though I do realize that adding 
-O reduces the size of the produced code).
There is no need to add unnecessary churn in front end tests if the optimizer 
changes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-06 Thread Victor Huang via Phabricator via cfe-commits 
NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:45
+  // CHECK-AIX-NEXT: ret { double, double } %.fca.1.insert
+  return __cmplxl(lda, ldb);
+}

nemanjai wrote:
> We really only need this test case and we should be able to just add it to 
> one of the existing XL-compat clang test cases.
As suggest above, can we add the test case `__cmplxl` to one of the existing 
clang test file `builtins-ppc-xlcompat-cmplx.c`? You can auto generate the 
`CHECKS` using `utils/update_cc_test_checks.py` to avoid hardcoding the 
variable names. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-04 Thread Albion Fung via Phabricator via cfe-commits 
Conanap marked an inline comment as done.
Conanap added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

NeHuang wrote:
> NeHuang wrote:
> > `// REQUIRES: powerpc-registered-target`
> Question: why do we need `-O2` for this builtin?
> 
it's not required, but removes a lot of the extra load and stores that make the 
test cases longer unnecessarily. I can change it to O1 if preferred.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-04 Thread Albion Fung via Phabricator via cfe-commits 
Conanap updated this revision to Diff 364223.
Conanap marked 6 inline comments as done.
Conanap added a comment.

Removed backend tests, removed some uneeded definitions,
updated frontend test with regex for variable names.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-complex.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
@@ -0,0 +1,30 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s \
+// RUN:   --check-prefix=CHECK-AIX
+
+extern long double lda, ldb;
+
+long double _Complex test_xl_cmplxl() {
+  // CHECK-LABEL: test_xl_cmplxl
+  // CHECK: %0 = load ppc_fp128, ppc_fp128* @lda
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: [[VAR1:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } undef, 
ppc_fp128 %0, 0
+  // CHECK-NEXT: [[VAR2:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } [[VAR1]], 
ppc_fp128 %1, 1
+  // CHECK-NEXT: ret { ppc_fp128, ppc_fp128 } [[VAR2]]
+
+  // CHECK-AIX-LABEL: test_xl_cmplxl
+  // CHECK-AIX: %0 = load double, double* @lda
+  // CHECK-AIX-NEXT: %1 = load double, double* @ldb
+  // CHECK-AIX-NEXT: [[VAR3:%.*]] = insertvalue { double, double } undef, 
double %0, 0
+  // CHECK-AIX-NEXT: [[VAR4:%.*]] = insertvalue { double, double } [[VAR3]], 
double %1, 1
+  // CHECK-AIX-NEXT: ret { double, double } [[VAR4]]
+  return __cmplxl(lda, ldb);
+}
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -235,6 +235,7 @@
   Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
   Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+  Builder.defineMacro("__cmplxl", "__builtin_complex");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific


Index: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
@@ -0,0 +1,30 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s \
+// RUN:   --check-prefix=CHECK-AIX
+
+extern long double lda, ldb;
+
+long double _Complex test_xl_cmplxl() {
+  // CHECK-LABEL: test_xl_cmplxl
+  // CHECK: %0 = load ppc_fp128, ppc_fp128* @lda
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: [[VAR1:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } undef, ppc_fp128 %0, 0
+  // CHECK-NEXT: [[VAR2:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } [[VAR1]], ppc_fp128 %1, 1
+  // CHECK-NEXT: ret { ppc_fp128, ppc_fp128 } [[VAR2]]
+
+  // CHECK-AIX-LABEL: test_xl_cmplxl
+  // CHECK-AIX: %0 = load double, double* @lda
+  // CHECK-AIX-NEXT: %1 = load double, double* @ldb
+  // CHECK-AIX-NEXT: [[VAR3:%.*]] = insertvalue { double, double } undef, double %0, 0
+  // CHECK-AIX-NEXT: [[VAR4:%.*]] = insertvalue { double, double } [[VAR3]], double %1, 1
+  // CHECK-AIX-NEXT: ret { double, double } [[VAR4]]
+  return __cmplxl(lda, ldb);
+}
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -235,6 +235,7 @@
   Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
   Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+  Builder.defineMacro("__cmplxl", "__builtin_complex");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
___
cfe-commits mailing list
cfe-commits@lists.llvm.org

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-07-30 Thread Amy Kwan via Phabricator via cfe-commits 
amyk added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:35
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: %.fca.0.insert = insertvalue { ppc_fp128, ppc_fp128 } undef, 
ppc_fp128 %0, 0
+  // CHECK-NEXT: %.fca.1.insert = insertvalue { ppc_fp128, ppc_fp128 } 
%.fca.0.insert, ppc_fp128 %1, 1

I think it would probably be better not to hardcode the variable names in the 
tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-07-30 Thread Victor Huang via Phabricator via cfe-commits 
NeHuang added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

`// REQUIRES: powerpc-registered-target`



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

NeHuang wrote:
> `// REQUIRES: powerpc-registered-target`
Question: why do we need `-O2` for this builtin?




Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \

nemanjai wrote:
> I don't think we need the back end tests. No new IR is produced in this patch.
+1


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-07-30 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai requested changes to this revision.
nemanjai added inline comments.
This revision now requires changes to proceed.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:146
 BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
+BUILTIN(__builtin_ppc_cmplxl, "XLdLdLd", "")
 

Please remove this. The preprocessor will replace this and the builtin call 
will never make it to the front end.



Comment at: clang/lib/Basic/Targets/PPC.cpp:238
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+  Builder.defineMacro("__builtin_ppc_cmplxl", "__builtin_complex");
+  Builder.defineMacro("__cmplxl", "__builtin_complex");

I don't see a compelling reason to have this. Users that want this 
functionality in new code (that doesn't already use `__cmplxl`) can simply use 
`__builtin_complex`.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:45
+  // CHECK-AIX-NEXT: ret { double, double } %.fca.1.insert
+  return __cmplxl(lda, ldb);
+}

We really only need this test case and we should be able to just add it to one 
of the existing XL-compat clang test cases.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \

I don't think we need the back end tests. No new IR is produced in this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-07-30 Thread Albion Fung via Phabricator via cfe-commits 
Conanap created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch implements the builtins for cmplxl by utilising
__builtin_complex. This builtin is implemented to match XL
functionality.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107138

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+@lda = external local_unnamed_addr global ppc_fp128, align 16
+@ldb = external local_unnamed_addr global ppc_fp128, align 16
+
+define { ppc_fp128, ppc_fp128 } @test_long_double_complex() {
+; CHECK-LABEL: test_long_double_complex:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:addis 4, 2, .LC1@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 4, .LC1@toc@l(4)
+; CHECK-NEXT:lfd 1, 0(3)
+; CHECK-NEXT:lfd 2, 8(3)
+; CHECK-NEXT:lfd 3, 0(4)
+; CHECK-NEXT:lfd 4, 8(4)
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_long_double_complex:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @lda
+; CHECK-AIX64-NEXT:ld 4, L..C1(2) # @ldb
+; CHECK-AIX64-NEXT:lfd 1, 0(3)
+; CHECK-AIX64-NEXT:lfd 2, 8(3)
+; CHECK-AIX64-NEXT:lfd 3, 0(4)
+; CHECK-AIX64-NEXT:lfd 4, 8(4)
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @lda, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ldb, align 16
+  %.fca.0.insert = insertvalue { ppc_fp128, ppc_fp128 } undef, ppc_fp128 %0, 0
+  %.fca.1.insert = insertvalue { ppc_fp128, ppc_fp128 } %.fca.0.insert, ppc_fp128 %1, 1
+  ret { ppc_fp128, ppc_fp128 } %.fca.1.insert
+}
+
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+@lda = external local_unnamed_addr global double, align 16
+@ldb = external local_unnamed_addr global double, align 16
+
+define { double, double } @test_long_double_complex() {
+; CHECK-LABEL: test_long_double_complex:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lwz 3, L..C0(2) # @lda
+; CHECK-NEXT:lwz 4, L..C1(2) # @ldb
+; CHECK-NEXT:lfd 1, 0(3)
+; CHECK-NEXT:lfd 2, 0(4)
+; CHECK-NEXT:blr
+entry:
+  %0 = load double, double* @lda, align 16
+  %1 = load double, double* @ldb, align 16
+  %.fca.0.insert = insertvalue { double, double } undef, double %0, 0
+  %.fca.1.insert = insertvalue { double, double } %.fca.0.insert, double %1, 1
+  ret { double, double } %.fca.1.insert
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
@@ -0,0 +1,46 @@
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s \
+// RUN:   --check-prefix=CHECK-AIX
+
+extern long double lda, ldb;
+
+long double _Complex test_cmplxl() {
+  // CHECK-LABEL: test_cmplxl
+  // CHECK: %0 = load ppc_fp128, ppc_fp128* @lda
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: %.fca.0.insert = insertvalue { ppc_fp128, ppc_fp128 } undef, ppc_fp128 %0, 0
+  // CHECK-NEXT: %.fca.1.insert = insertvalue { ppc_fp128, ppc_fp128 } %.fca.0.insert, ppc_fp128 %1, 1
+  // CHECK-NEXT: ret { ppc_fp128, ppc_fp128 }