[PATCH] D113638: [xray] Add support for hexagon architecture

2022-12-28 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay added a comment.
Herald added a subscriber: Enna1.
Herald added a project: All.

`recordSled(CurSled, MI, Kind, 0);` is not intended. All new ports should use 
version 2.


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[PATCH] D113638: [xray] Add support for hexagon architecture

2021-12-15 Thread Dean Michael Berris via Phabricator via cfe-commits 
dberris added a comment.

Whoops -- sorry, I had forgotten to change my email settings and missed this.

Thanks for the patch, it's exciting to see XRay being supported in the Hexagon 
architecture!


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[PATCH] D113638: [xray] Add support for hexagon architecture

2021-12-09 Thread Brian Cain via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG543a9ad7c460: [xray] add support for hexagon (authored by 
androm3da).

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Files:
  clang/lib/Driver/ToolChains/Hexagon.cpp
  clang/lib/Driver/XRayArgs.cpp
  compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
  compiler-rt/lib/xray/CMakeLists.txt
  compiler-rt/lib/xray/xray_hexagon.cpp
  compiler-rt/lib/xray/xray_interface.cpp
  compiler-rt/lib/xray/xray_trampoline_hexagon.S
  compiler-rt/lib/xray/xray_tsc.h
  llvm/lib/CodeGen/XRayInstrumentation.cpp
  llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
  llvm/lib/Target/Hexagon/HexagonAsmPrinter.h
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.h
  llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
  llvm/lib/Target/Hexagon/HexagonSubtarget.h
  llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  llvm/test/CodeGen/Hexagon/xray-pred-ret.ll
  llvm/test/CodeGen/Hexagon/xray.ll

Index: llvm/test/CodeGen/Hexagon/xray.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Hexagon/xray.ll
@@ -0,0 +1,29 @@
+; RUN: llc -filetype=asm -o - -mtriple=hexagon-unknown-elf < %s | FileCheck %s
+; RUN: llc -filetype=asm -o - -mtriple=hexagon-unknown-linux-musl  < %s | FileCheck %s
+
+define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" {
+; CHECK-LABEL: .Lxray_sled_0:
+; CHECK:   jump .Ltmp0
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK-LABEL: .Ltmp0:
+  ret i32 0
+; CHECK-LABEL: .Lxray_sled_1:
+; CHECK:   jump .Ltmp1
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK-LABEL: .Ltmp1:
+; CHECK:   jumpr r31
+}
+; CHECK-LABEL: xray_instr_map
+; CHECK-LABEL: .Lxray_sleds_start0:
+; CHECK:   .word {{.*}}Lxray_sled_0
+; CHECK:   .word {{.*}}Lxray_sled_1
+; CHECK-LABEL: .Lxray_sleds_end0:
+; CHECK-LABEL: xray_fn_idx
+; CHECK:   .word {{.*}}Lxray_sleds_start0
+; CHECK-NEXT:  .word {{.*}}Lxray_sleds_end0
Index: llvm/test/CodeGen/Hexagon/xray-pred-ret.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Hexagon/xray-pred-ret.ll
@@ -0,0 +1,27 @@
+; RUN: llc -filetype=asm -o - -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s
+
+define void @Foo(i32 signext %a, i32 signext %b) #0 {
+; CHECK-LABEL: @Foo
+; CHECK-LABEL: .Lxray_sled_0:
+; CHECK:jump .Ltmp0
+; CHECK-COUNT-4: nop
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+; CHECK-LABEL: .Lxray_sled_1:
+; CHECK:jump .Ltmp1
+; CHECK-COUNT-4: nop
+; CHECK-LABEL: .Ltmp1:
+; CHECK:   if (p0) jumpr:nt r31
+if.end:
+  tail call void @Bar()
+  br label %return
+
+return:
+  ret void
+}
+
+declare void @Bar()
+
+attributes #0 = { "function-instrument"="xray-always" }
Index: llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
===
--- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1082,6 +1082,11 @@
   if (HII->isSolo(MI))
 return true;
 
+  if (MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_ENTER ||
+  MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_EXIT ||
+  MI.getOpcode() == Hexagon::PATCHABLE_TAIL_CALL)
+return true;
+
   if (MI.getOpcode() == Hexagon::A2_nop)
 return true;
 
Index: llvm/lib/Target/Hexagon/HexagonSubtarget.h
===
--- llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -138,6 +138,8 @@
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 
+  bool isXRaySupported() const override { return true; }
+
   bool hasV5Ops() const {
 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
   }
Index: llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
===
--- llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
+++ llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
@@ -104,6 +104,19 @@
 HexagonMCInstrInfo::setOuterLoop(MCB);
 return;
   }
+  if (MI->getOpcode() == Hexagon::PATCHABLE_FUNCTION_ENTER) {
+AP.EmitSled(*MI, HexagonAsmPrinter::SledKind::FUNCTION_ENTER);
+return;
+  }
+  if (MI->getOpcode() == Hexagon::PATCHABLE_FUNCTION_EXIT) {
+AP.EmitSled(*MI, HexagonAsmPrinter::SledKind::FUNCTION_EXIT);
+return;
+  }
+  if (MI->getOpcode() == Hexagon::PATCHABLE_TAIL_CALL) {
+AP.EmitSled(*MI, HexagonAsmPrinter::SledKind::TAIL_CALL);
+return;
+  }
+
   MCInst *MCI =

[PATCH] D113638: [xray] Add support for hexagon architecture

2021-12-08 Thread Krzysztof Parzyszek via Phabricator via cfe-commits 
kparzysz accepted this revision.
kparzysz added a comment.
This revision is now accepted and ready to land.

LGTM.  Thanks!


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[PATCH] D113638: [xray] Add support for hexagon architecture

2021-12-02 Thread Sid Manning via Phabricator via cfe-commits 
sidneym added a comment.

LGTM.


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[PATCH] D113638: [xray] Add support for hexagon architecture

2021-11-17 Thread Brian Cain via Phabricator via cfe-commits 
androm3da added a comment.

Ping - any thoughts/concerns?


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[PATCH] D113638: [xray] Add support for hexagon architecture

2021-11-10 Thread Brian Cain via Phabricator via cfe-commits 
androm3da added a comment.

This patch spans several areas, so I would be happy to decompose it into 
smaller parts if it made it easier for reviewers.




Comment at: compiler-rt/lib/xray/xray_hexagon.cpp:76-84
+static void WriteInstFlushCache(void *Addr, uint32_t NewInstruction) {
+  asm volatile("icinva(%[inst_addr])\n\t"
+   "isync\n\t"
+   "memw(%[inst_addr]) = %[new_inst]\n\t"
+   "dccleaninva(%[inst_addr])\n\t"
+   "syncht\n\t"
+   :

If we need to support cases where the entire sled spans cache lines, then we 
must iterate over the icinva() instead.




Comment at: compiler-rt/lib/xray/xray_hexagon.cpp:76-84
+static void WriteInstFlushCache(void *Addr, uint32_t NewInstruction) {
+  asm volatile("icinva(%[inst_addr])\n\t"
+   "isync\n\t"
+   "memw(%[inst_addr]) = %[new_inst]\n\t"
+   "dccleaninva(%[inst_addr])\n\t"
+   "syncht\n\t"
+   :

androm3da wrote:
> If we need to support cases where the entire sled spans cache lines, then we 
> must iterate over the icinva() instead.
> 
Other arches do atomic stores.  I think we will need to change this to: LL 
first, then icinva/isync, then SC.  

If the SC fails then either we re-run all those steps because we want to 
clobber it or we do nothing because we assume some other thread applied the 
same patch first?


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[PATCH] D113638: [xray] Add support for hexagon architecture

2021-11-10 Thread Brian Cain via Phabricator via cfe-commits 
androm3da created this revision.
androm3da added reviewers: dberris, kparzysz.
Herald added subscribers: hiraditya, mgorny.
androm3da requested review of this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

Adds x-ray support for hexagon to llvm codegen, clang driver, compiler-rt libs.


Repository:
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https://reviews.llvm.org/D113638

Files:
  clang/lib/Driver/ToolChains/Hexagon.cpp
  clang/lib/Driver/XRayArgs.cpp
  compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
  compiler-rt/lib/xray/CMakeLists.txt
  compiler-rt/lib/xray/xray_hexagon.cpp
  compiler-rt/lib/xray/xray_interface.cpp
  compiler-rt/lib/xray/xray_trampoline_hexagon.S
  compiler-rt/lib/xray/xray_tsc.h
  llvm/lib/CodeGen/XRayInstrumentation.cpp
  llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
  llvm/lib/Target/Hexagon/HexagonAsmPrinter.h
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.h
  llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
  llvm/lib/Target/Hexagon/HexagonSubtarget.h
  llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  llvm/test/CodeGen/Hexagon/xray-pred-ret.ll
  llvm/test/CodeGen/Hexagon/xray.ll

Index: llvm/test/CodeGen/Hexagon/xray.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Hexagon/xray.ll
@@ -0,0 +1,29 @@
+; RUN: llc -filetype=asm -o - -mtriple=hexagon-unknown-elf < %s | FileCheck %s
+; RUN: llc -filetype=asm -o - -mtriple=hexagon-unknown-linux-musl  < %s | FileCheck %s
+
+define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" {
+; CHECK-LABEL: .Lxray_sled_0:
+; CHECK:   jump .Ltmp0
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK-LABEL: .Ltmp0:
+  ret i32 0
+; CHECK-LABEL: .Lxray_sled_1:
+; CHECK:   jump .Ltmp1
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK: nop
+; CHECK-LABEL: .Ltmp1:
+; CHECK:   jumpr r31
+}
+; CHECK-LABEL: xray_instr_map
+; CHECK-LABEL: .Lxray_sleds_start0:
+; CHECK:   .word {{.*}}Lxray_sled_0
+; CHECK:   .word {{.*}}Lxray_sled_1
+; CHECK-LABEL: .Lxray_sleds_end0:
+; CHECK-LABEL: xray_fn_idx
+; CHECK:   .word {{.*}}Lxray_sleds_start0
+; CHECK-NEXT:  .word {{.*}}Lxray_sleds_end0
Index: llvm/test/CodeGen/Hexagon/xray-pred-ret.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Hexagon/xray-pred-ret.ll
@@ -0,0 +1,27 @@
+; RUN: llc -filetype=asm -o - -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s
+
+define void @Foo(i32 signext %a, i32 signext %b) #0 {
+; CHECK-LABEL: @Foo
+; CHECK-LABEL: .Lxray_sled_0:
+; CHECK:jump .Ltmp0
+; CHECK-COUNT-4: nop
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  br i1 %cmp, label %return, label %if.end
+
+; CHECK-LABEL: .Lxray_sled_1:
+; CHECK:jump .Ltmp1
+; CHECK-COUNT-4: nop
+; CHECK-LABEL: .Ltmp1:
+; CHECK:   if (p0) jumpr:nt r31
+if.end:
+  tail call void @Bar()
+  br label %return
+
+return:
+  ret void
+}
+
+declare void @Bar()
+
+attributes #0 = { "function-instrument"="xray-always" }
Index: llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
===
--- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1082,6 +1082,11 @@
   if (HII->isSolo(MI))
 return true;
 
+  if (MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_ENTER ||
+  MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_EXIT ||
+  MI.getOpcode() == Hexagon::PATCHABLE_TAIL_CALL)
+return true;
+
   if (MI.getOpcode() == Hexagon::A2_nop)
 return true;
 
Index: llvm/lib/Target/Hexagon/HexagonSubtarget.h
===
--- llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -138,6 +138,8 @@
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 
+  bool isXRaySupported() const override { return true; }
+
   bool hasV5Ops() const {
 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
   }
Index: llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
===
--- llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
+++ llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp
@@ -104,6 +104,19 @@
 HexagonMCInstrInfo::setOuterLoop(MCB);
 return;
   }
+  if (MI->getOpcode() == Hexagon::PATCHABLE_FUNCTION_ENTER) {
+AP.EmitSled(*MI, HexagonAsmPrinter::SledKind::FUNCTION_ENTER);
+return;
+  }
+  if (MI->getOpcode() == Hexagon::PATCHABLE_FUNCTION_EXIT) {
+AP.EmitSled(*MI, HexagonAsmPrinter::SledKind::FUNCTION_EXIT);
+return;
+  }
+  if (MI->getOpcode() == Hexagon::PATCHABLE_TAIL_CALL) {
+AP.EmitSled(*MI,