[PATCH] D126749: [RISCV][Clang] Support policy functions for Vector Mask Instructions.

2022-08-02 Thread Zakk Chen via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbb99d4b11d84: [RISCV][Clang] Support policy functions for 
Vector Mask Instructions. (authored by khchen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126749/new/

https://reviews.llvm.org/D126749

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsof_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsif_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsbf_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
@@ -204,7 +204,7 @@
 
 // CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64( [[MASKEDOFF:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
 vuint8mf8_t

[PATCH] D126749: [RISCV][Clang] Support policy functions for Vector Mask Instructions.

2022-05-31 Thread Zakk Chen via Phabricator via cfe-commits 
khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, kito-cheng, fakepaper56, eopXD.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
khchen requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126749

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsof_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsof_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsof.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsof_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsof_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsif_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsif_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsif.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsif_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsif_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
@@ -136,3 +136,21 @@
  size_t vl) {
   return vmsbf_m_b64_m(mask, maskedoff, op1, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_ma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( undef,  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_ma(vbool4_t mask, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_ma(mask, op1, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmsbf_m_b4_mu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vmsbf.mask.nxv16i1.i64( [[MERGE:%.*]],  [[OP1:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:ret  [[TMP0]]
+//
+vbool4_t test_vmsbf_m_b4_mu(vbool4_t mask, vbool4_t merge, vbool4_t op1, size_t vl) {
+  return vmsbf_m_b4_mu(mask, merge, op1, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c
@@ -204,7 +204,7 @@
 
 // CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.viota.mask.nxv1i8.i64(