[PATCH] D128624: [RISCV] Zero immediate for vget/vset builtins to match vector.insert/extract intrinsics.

[Yeting Kuo via Phabricator via cfe-commits]

fakepaper56 added a comment.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D128624/new/

https://reviews.llvm.org/D128624

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[PATCH] D128624: [RISCV] Zero immediate for vget/vset builtins to match vector.insert/extract intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
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The vector.insert/extract intrinsics require an i64 immediate argument.
This fixes a crash on RV32.

This is an alternative to D128613 .


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128624

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
@@ -1,600 +1,603 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
-// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK %s
 
 #include 
 
-// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
-// CHECK-RV64-NEXT:ret  [[TMP0]]
+// CHECK-LABEL: @test_vset_v_i8m1_i8m2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 8)
+// CHECK-NEXT:ret  [[TMP0]]
 //
 vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
   return vset_v_i8m1_i8m2(dest, 1, val);
 }
 
-// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 24)
-// CHECK-RV64-NEXT:ret  [[TMP0]]
+// CHECK-LABEL: @test_vset_v_i8m1_i8m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 24)
+// CHECK-NEXT:ret  [[TMP0]]
 //
 vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
   return vset_v_i8m1_i8m4(dest, 3, val);
 }
 
-// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 16)
-// CHECK-RV64-NEXT:ret  [[TMP0]]
+// CHECK-LABEL: @test_vset_v_i8m2_i8m4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 16)
+// CHECK-NEXT:ret  [[TMP0]]
 //
 vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
   return vset_v_i8m2_i8m4(dest, 1, val);
 }
 
-// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 56)
-// CHECK-RV64-NEXT:ret  [[TMP0]]
+// CHECK-LABEL: @test_vset_v_i8m1_i8m8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv8i8( [[DEST:%.*]],  [[VAL:%.*]], i64 56)
+// CHECK-NEXT:ret  [[TMP0]]
 //
 vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
   return vset_v_i8m1_i8m8(dest, 7, val);
 }
 
-// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8(
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
-// CHECK-RV64-NEXT:ret  [[TMP0]]
+// CHECK-LABEL: @test_vset_v_i8m2_i8m8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv64i8.nxv16i8( [[DEST:%.*]],  [[VAL:%.*]], i64 32)
+// CHECK-NEXT:ret  [[TMP0]]
 //
 vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
   return vset_v_i8m2_i8m8(dest, 2, val);
 }
 
-// CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8(
-//