[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-18 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei updated this revision to Diff 468463.
pengfei added a comment.

Rebased on D136145  and split RIP 
optimization.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/prfchiintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/test/CodeGen/X86/prefetchi-builtins.c
  clang/test/Driver/x86-target-features.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/prefetch.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/PREFETCH-64.s

Index: llvm/test/MC/X86/PREFETCH-64.s
===
--- llvm/test/MC/X86/PREFETCH-64.s
+++ llvm/test/MC/X86/PREFETCH-64.s
@@ -168,3 +168,50 @@
 // CHECK: encoding: [0x0f,0x0d,0x12]
 prefetchwt1 (%rdx) 
 
+// CHECK: prefetchit0 485498096
+// CHECK: encoding: [0x0f,0x18,0x3c,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit0 485498096
+
+// CHECK: prefetchit0 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x7a,0x40]
+prefetchit0 64(%rdx)
+
+// CHECK: prefetchit0 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0x40]
+prefetchit0 64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0xc0]
+prefetchit0 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x02,0x40]
+prefetchit0 64(%rdx,%rax)
+
+// CHECK: prefetchit0 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x3a]
+prefetchit0 (%rdx)
+
+// CHECK: prefetchit1 485498096
+// CHECK: encoding: [0x0f,0x18,0x34,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit1 485498096
+
+// CHECK: prefetchit1 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x72,0x40]
+prefetchit1 64(%rdx)
+
+// CHECK: prefetchit1 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0x40]
+prefetchit1 64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0xc0]
+prefetchit1 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x74,0x02,0x40]
+prefetchit1 64(%rdx,%rax)
+
+// CHECK: prefetchit1 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x32]
+prefetchit1 (%rdx)
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -761,3 +761,9 @@
 
 # CHECK: rdpru
 0x0f,0x01,0xfd
+
+# CHECK: prefetchit0 (%rip)
+0x0f,0x18,0x3d,0x00,0x00,0x00,0x00
+
+# CHECK: prefetchit1 (%rip)
+0x0f,0x18,0x35,0x00,0x00,0x00,0x00
Index: llvm/test/CodeGen/X86/prefetch.ll
===
--- llvm/test/CodeGen/X86/prefetch.ll
+++ llvm/test/CodeGen/X86/prefetch.ll
@@ -11,6 +11,8 @@
 ; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=3DNOW
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=3DNOW
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchi | FileCheck %s -check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchi | FileCheck %s -check-prefix=PREFETCHI
 
 ; Rules:
 ; 3dnow by itself get you just the single prefetch instruction with no hints
@@ -89,6 +91,22 @@
 ; 3DNOW-NEXT:prefetch t
 ; 3DNOW-NEXT:prefetch ext
 ; 3DNOW-NEXT:retl
+;
+; PREFETCHI-LABEL: t:
+; PREFETCHI:   # %bb.0: # %entry
+; PREFETCHI-NEXT:prefetcht2 (%rdi)
+; PREFETCHI-NEXT:prefetcht1 (%rdi)
+; PREFETCHI-NEXT:prefetcht0 (%rdi)
+; PREFETCHI-NEXT:prefetchnta (%rdi)
+; PREFETCHI-NEXT:prefetcht2 (%rdi)
+; PREFETCHI-NEXT:prefetcht1 (%rdi)
+; PREFETCHI-NEXT:prefetcht0 (%rdi)
+; PREFETCHI-NEXT:prefetchnta (%rdi)
+; PREFETCHI-NEXT:prefetchit1 (%rdi)
+; PREFETCHI-NEXT:prefetchit0 (%rdi)
+; PREFETCHI-NEXT:prefetchit1 t(%rip)
+; PREFETCHI-NEXT:prefetchit0 ext(%rip)
+; PREFETCHI-NEXT:retq
 entry:
 	tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 1, i32 1 )
 	tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 2, i32 1 )
Index: llvm/lib/Target/X86/X86Subtarget.h
===
--- llvm/lib/Target/X86/X86Subtarget.h
+++ llvm/lib/Target/X86/X86Subtarget.h
@@ -221,7 +221,8 @@
 // We implicitly enable these when we have a write prefix supporting cache
 // level OR if we have prfchw, but don't already have a read prefetch from
 // 3dnow.
-return

[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-18 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei added a comment.

In D136040#3862551 , @uweigand wrote:

> In D136040#3862386 , @pengfei wrote:
>
>> Sure, it is possible. But at least for now, there's no real target requires 
>> it. Checked with `grep -rwn 'llvm.prefetch.*i32 0\s*)' llvm/test/CodeGen/`.
>
> But that's just within the LLVM sources.  My point was that -up to now- this 
> was part of the public LLVM IR spec, so there could by other LLVM users out 
> there creating this IR, which would now suddenly break.  Not sure what the 
> rules are for breaking IR changes, but that would presumably need some wider 
> discussion.

Thanks @uweigand, you are right. I have split D136145 
 and put it in Discourse for broad discussion.


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[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-17 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added a comment.

There are too many things in this patch. Please up MC layer changes from 
intrinsic/builtin changes. The RIP optimization probably also be separate.


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[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-17 Thread Ulrich Weigand via Phabricator via cfe-commits 
uweigand added a comment.

In D136040#3862386 , @pengfei wrote:

> Sure, it is possible. But at least for now, there's no real target requires 
> it. Checked with `grep -rwn 'llvm.prefetch.*i32 0\s*)' llvm/test/CodeGen/`.

But that's just within the LLVM sources.  My point was that -up to now- this 
was part of the public LLVM IR spec, so there could by other LLVM users out 
there creating this IR, which would now suddenly break.  Not sure what the 
rules are for breaking IR changes, but that would presumably need some wider 
discussion.


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[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-17 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei added a comment.

In D136040#3862265 , @uweigand wrote:

> In D136040#3862225 , @pengfei wrote:
>
>> 3. Add semacheck for prefetch write to instruction cache;
>>
>> I think the affected ARM and SystemZ tests are not valid before. Could 
>> @t.p.northover and @uweigand help to have a look?
>
> This seems to be a semantic change.   The Language Reference does not spell 
> out that a write prefetch on the instruction cache is prohibited.  In fact, I 
> read it to explicitly state that every flavor of the prefetch intrinsic that 
> doesn't match anything supported on the target architecture should simply be 
> a no-op.  (I could imagine that on certain architectures, you might even have 
> such a prefetch, e.g. to handle self-modifying code more efficiently.)

Sure, it is possible. But at least for now, there's no real target requires it. 
Checked with `grep -rwn 'llvm.prefetch.*i32 0\s*)' llvm/test/CodeGen/`.
The reason I do it is it's ambiguity to backend when lower it to a target that 
has "write data", "read data" and "read instruction" prefetches. It's clear if 
we just support the semantic of "read instruction" and lower it to "read data" 
when available.
I think we can modify Language Reference for it.


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[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-17 Thread Ulrich Weigand via Phabricator via cfe-commits 
uweigand added a comment.

In D136040#3862225 , @pengfei wrote:

> 3. Add semacheck for prefetch write to instruction cache;
>
> I think the affected ARM and SystemZ tests are not valid before. Could 
> @t.p.northover and @uweigand help to have a look?

This seems to be a semantic change.   The Language Reference does not spell out 
that a write prefetch on the instruction cache is prohibited.  In fact, I read 
it to explicitly state that every flavor of the prefetch intrinsic that doesn't 
match anything supported on the target architecture should simply be a no-op.  
(I could imagine that on certain architectures, you might even have such a 
prefetch, e.g. to handle self-modifying code more efficiently.)


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[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-17 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei added inline comments.



Comment at: clang/include/clang/Driver/Options.td:4651
 def mno_popcnt : Flag<["-"], "mno-popcnt">, Group;
+def mprefetchi : Flag<["-"], "mprefetchi">, Group;
+def mno_prefetchi : Flag<["-"], "mno-prefetchi">, Group;

LuoYuanke wrote:
> I notice in line 4655 the option name is "prfch", do we need to follow the 
> naming convention?
I don't know the reason why we used `prfchw` before, but we are now using the 
option the same as feature name so that user can easily guess the right option.



Comment at: llvm/lib/Target/X86/X86InstrInfo.td:3007
+  def PREFETCHIT0 : I<0x18, MRM7m, (outs), (ins i8mem:$src),
+"prefetchit0\t$src", [(prefetch addr:$src, (i32 1), (i32 3), (i32 0))]>, 
TB;
+  def PREFETCHIT1 : I<0x18, MRM6m, (outs), (ins i8mem:$src),

LuoYuanke wrote:
> Could you add comments to explain the what the constant (1, 3, 0) means?  I 
> guess it is the same to the arguments that llvm.prefetch defines.
Added short introduction. Full description is in 
https://llvm.org/docs/LangRef.html#llvm-prefetch-intrinsic


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[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-17 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei updated this revision to Diff 468195.
pengfei added subscribers: uweigand, t.p.northover.
pengfei added a comment.

1. Address review comments;
2. Optimize prefetchit0/1 to prefetcht0/1 for non-rip address;
3. Add semacheck for prefetch write to instruction cache;
4. Fix a bug that set `rw` = 1 for prefetchit0/1;

I think the affected ARM and SystemZ tests are not valid before. Could 
@t.p.northover and @uweigand help to have a look?


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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/prfchiintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/prefetchi-builtins.c
  clang/test/CodeGen/builtins-arm.c
  clang/test/Driver/x86-target-features.c
  clang/test/Sema/builtin-prefetch.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86Instr3DNow.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/SystemZ/prefetch-01.ll
  llvm/test/CodeGen/X86/prefetch.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/PREFETCH-64.s

Index: llvm/test/MC/X86/PREFETCH-64.s
===
--- llvm/test/MC/X86/PREFETCH-64.s
+++ llvm/test/MC/X86/PREFETCH-64.s
@@ -168,3 +168,50 @@
 // CHECK: encoding: [0x0f,0x0d,0x12]
 prefetchwt1 (%rdx) 
 
+// CHECK: prefetchit0 485498096
+// CHECK: encoding: [0x0f,0x18,0x3c,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit0 485498096
+
+// CHECK: prefetchit0 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x7a,0x40]
+prefetchit0 64(%rdx)
+
+// CHECK: prefetchit0 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0x40]
+prefetchit0 64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0xc0]
+prefetchit0 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x02,0x40]
+prefetchit0 64(%rdx,%rax)
+
+// CHECK: prefetchit0 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x3a]
+prefetchit0 (%rdx)
+
+// CHECK: prefetchit1 485498096
+// CHECK: encoding: [0x0f,0x18,0x34,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit1 485498096
+
+// CHECK: prefetchit1 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x72,0x40]
+prefetchit1 64(%rdx)
+
+// CHECK: prefetchit1 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0x40]
+prefetchit1 64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0xc0]
+prefetchit1 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x74,0x02,0x40]
+prefetchit1 64(%rdx,%rax)
+
+// CHECK: prefetchit1 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x32]
+prefetchit1 (%rdx)
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -761,3 +761,9 @@
 
 # CHECK: rdpru
 0x0f,0x01,0xfd
+
+# CHECK: prefetchit0 (%rip)
+0x0f,0x18,0x3d,0x00,0x00,0x00,0x00
+
+# CHECK: prefetchit1 (%rip)
+0x0f,0x18,0x35,0x00,0x00,0x00,0x00
Index: llvm/test/CodeGen/X86/prefetch.ll
===
--- llvm/test/CodeGen/X86/prefetch.ll
+++ llvm/test/CodeGen/X86/prefetch.ll
@@ -11,6 +11,8 @@
 ; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=3DNOW
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=3DNOW
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchi | FileCheck %s -check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchi | FileCheck %s -check-prefix=PREFETCHI
 
 ; Rules:
 ; 3dnow by itself get you just the single prefetch instruction with no hints
@@ -21,7 +23,7 @@
 
 ; rdar://10538297
 
-define void @t(ptr %ptr) nounwind  {
+define dso_local void @t(ptr %ptr) nounwind  {
 ; SSE-LABEL: t:
 ; SSE:   # %bb.0: # %entry
 ; SSE-NEXT:movl {{[0-9]+}}(%esp), %eax
@@ -33,6 +35,10 @@
 ; SSE-NEXT:prefetcht1 (%eax)
 ; SSE-NEXT:prefetcht0 (%eax)
 ; SSE-NEXT:prefetchnta (%eax)
+; SSE-NEXT:prefetcht1 (%eax)
+; SSE-NEXT:prefetcht0 (%eax)
+; SSE-NEXT:prefetcht1 t
+; SSE-NEXT:prefetcht0 ext
 ; SSE-NEXT:retl
 ;
 ; PRFCHWSSE-LABEL: t:
@@ -46,6 +52,10 @@
 ;

[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-17 Thread LuoYuanke via Phabricator via cfe-commits 
LuoYuanke added inline comments.



Comment at: clang/include/clang/Driver/Options.td:4651
 def mno_popcnt : Flag<["-"], "mno-popcnt">, Group;
+def mprefetchi : Flag<["-"], "mprefetchi">, Group;
+def mno_prefetchi : Flag<["-"], "mno-prefetchi">, Group;

I notice in line 4655 the option name is "prfch", do we need to follow the 
naming convention?



Comment at: llvm/lib/Target/X86/X86InstrInfo.td:3007
+  def PREFETCHIT0 : I<0x18, MRM7m, (outs), (ins i8mem:$src),
+"prefetchit0\t$src", [(prefetch addr:$src, (i32 1), (i32 3), (i32 0))]>, 
TB;
+  def PREFETCHIT1 : I<0x18, MRM6m, (outs), (ins i8mem:$src),

Could you add comments to explain the what the constant (1, 3, 0) means?  I 
guess it is the same to the arguments that llvm.prefetch defines.


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[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-16 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei updated this revision to Diff 468109.
pengfei added a comment.

Fix lit fails.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/prfchiintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/prefetchi-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Sema/builtin-prefetch.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
  llvm/lib/Target/X86/X86Instr3DNow.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/prefetch.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/PREFETCH-64.s

Index: llvm/test/MC/X86/PREFETCH-64.s
===
--- llvm/test/MC/X86/PREFETCH-64.s
+++ llvm/test/MC/X86/PREFETCH-64.s
@@ -168,3 +168,50 @@
 // CHECK: encoding: [0x0f,0x0d,0x12]
 prefetchwt1 (%rdx) 
 
+// CHECK: prefetchit0 485498096
+// CHECK: encoding: [0x0f,0x18,0x3c,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit0 485498096
+
+// CHECK: prefetchit0 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x7a,0x40]
+prefetchit0 64(%rdx)
+
+// CHECK: prefetchit0 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0x40]
+prefetchit0 64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0xc0]
+prefetchit0 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x02,0x40]
+prefetchit0 64(%rdx,%rax)
+
+// CHECK: prefetchit0 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x3a]
+prefetchit0 (%rdx)
+
+// CHECK: prefetchit1 485498096
+// CHECK: encoding: [0x0f,0x18,0x34,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit1 485498096
+
+// CHECK: prefetchit1 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x72,0x40]
+prefetchit1 64(%rdx)
+
+// CHECK: prefetchit1 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0x40]
+prefetchit1 64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0xc0]
+prefetchit1 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x74,0x02,0x40]
+prefetchit1 64(%rdx,%rax)
+
+// CHECK: prefetchit1 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x32]
+prefetchit1 (%rdx)
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -761,3 +761,9 @@
 
 # CHECK: rdpru
 0x0f,0x01,0xfd
+
+# CHECK: prefetchit0 (%rip)
+0x0f,0x18,0x3d,0x00,0x00,0x00,0x00
+
+# CHECK: prefetchit1 (%rip)
+0x0f,0x18,0x35,0x00,0x00,0x00,0x00
Index: llvm/test/CodeGen/X86/prefetch.ll
===
--- llvm/test/CodeGen/X86/prefetch.ll
+++ llvm/test/CodeGen/X86/prefetch.ll
@@ -11,6 +11,8 @@
 ; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=3DNOW
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=3DNOW
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchwt1,+prefetchi | FileCheck %s -check-prefix=PREFETCHWT1
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchwt1,+prefetchi | FileCheck %s -check-prefix=PREFETCHI
 
 ; Rules:
 ; 3dnow by itself get you just the single prefetch instruction with no hints
@@ -33,6 +35,8 @@
 ; SSE-NEXT:prefetcht1 (%eax)
 ; SSE-NEXT:prefetcht0 (%eax)
 ; SSE-NEXT:prefetchnta (%eax)
+; SSE-NEXT:prefetcht0 (%eax)
+; SSE-NEXT:prefetcht1 (%eax)
 ; SSE-NEXT:retl
 ;
 ; PRFCHWSSE-LABEL: t:
@@ -46,6 +50,8 @@
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
+; PRFCHWSSE-NEXT:prefetcht0 (%eax)
+; PRFCHWSSE-NEXT:prefetcht1 (%eax)
 ; PRFCHWSSE-NEXT:retl
 ;
 ; PREFETCHWT1-LABEL: t:
@@ -59,6 +65,8 @@
 ; PREFETCHWT1-NEXT:prefetchwt1 (%eax)
 ; PREFETCHWT1-NEXT:prefetchw (%eax)
 ; PREFETCHWT1-NEXT:prefetchwt1 (%eax)
+; PREFETCHWT1-NEXT:prefetcht0 (%eax)
+; PREFETCHWT1-NEXT:prefetcht1 (%eax)
 ; PREFETCHWT1-NEXT:retl
 ;
 ; 3DNOW-LABEL: t:
@@ -72,7 +80,23 @@
 ; 3DNOW-NEXT:prefetchw (%eax)
 ; 3DNOW-NEXT:prefetchw (%eax)
 ; 3DNOW-NEXT:prefetchw (%eax)
+; 3DNOW-NEXT:prefetch (%eax)
+; 3DNOW-NEXT:prefetch (%eax)
 ; 3DNOW-NEXT:retl
+;
+; PREFETCHI-LABEL: t:
+; PREFETCHI:   # %bb.0: # %entry
+;

[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-16 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei updated this revision to Diff 468080.
pengfei added a comment.

Fix lit fails.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136040/new/

https://reviews.llvm.org/D136040

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/prfchiintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/prefetchi-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Sema/builtin-prefetch.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
  llvm/lib/Target/X86/X86Instr3DNow.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/prefetch.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/PREFETCH-64.s

Index: llvm/test/MC/X86/PREFETCH-64.s
===
--- llvm/test/MC/X86/PREFETCH-64.s
+++ llvm/test/MC/X86/PREFETCH-64.s
@@ -168,3 +168,50 @@
 // CHECK: encoding: [0x0f,0x0d,0x12]
 prefetchwt1 (%rdx) 
 
+// CHECK: prefetchit0 485498096
+// CHECK: encoding: [0x0f,0x18,0x3c,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit0 485498096
+
+// CHECK: prefetchit0 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x7a,0x40]
+prefetchit0 64(%rdx)
+
+// CHECK: prefetchit0 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0x40]
+prefetchit0 64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0xc0]
+prefetchit0 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x02,0x40]
+prefetchit0 64(%rdx,%rax)
+
+// CHECK: prefetchit0 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x3a]
+prefetchit0 (%rdx)
+
+// CHECK: prefetchit1 485498096
+// CHECK: encoding: [0x0f,0x18,0x34,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit1 485498096
+
+// CHECK: prefetchit1 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x72,0x40]
+prefetchit1 64(%rdx)
+
+// CHECK: prefetchit1 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0x40]
+prefetchit1 64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0xc0]
+prefetchit1 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x74,0x02,0x40]
+prefetchit1 64(%rdx,%rax)
+
+// CHECK: prefetchit1 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x32]
+prefetchit1 (%rdx)
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -761,3 +761,9 @@
 
 # CHECK: rdpru
 0x0f,0x01,0xfd
+
+# CHECK: prefetchit0 (%rip)
+0x0f,0x18,0x3d,0x00,0x00,0x00,0x00
+
+# CHECK: prefetchit1 (%rip)
+0x0f,0x18,0x35,0x00,0x00,0x00,0x00
Index: llvm/test/CodeGen/X86/prefetch.ll
===
--- llvm/test/CodeGen/X86/prefetch.ll
+++ llvm/test/CodeGen/X86/prefetch.ll
@@ -11,6 +11,8 @@
 ; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=3DNOW
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=3DNOW
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchwt1,+prefetchi | FileCheck %s -check-prefix=PREFETCHWT1
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchwt1,+prefetchi | FileCheck %s -check-prefix=PREFETCHI
 
 ; Rules:
 ; 3dnow by itself get you just the single prefetch instruction with no hints
@@ -33,6 +35,8 @@
 ; SSE-NEXT:prefetcht1 (%eax)
 ; SSE-NEXT:prefetcht0 (%eax)
 ; SSE-NEXT:prefetchnta (%eax)
+; SSE-NEXT:prefetcht0 (%eax)
+; SSE-NEXT:prefetcht1 (%eax)
 ; SSE-NEXT:retl
 ;
 ; PRFCHWSSE-LABEL: t:
@@ -46,6 +50,8 @@
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
+; PRFCHWSSE-NEXT:prefetcht0 (%eax)
+; PRFCHWSSE-NEXT:prefetcht1 (%eax)
 ; PRFCHWSSE-NEXT:retl
 ;
 ; PREFETCHWT1-LABEL: t:
@@ -59,6 +65,8 @@
 ; PREFETCHWT1-NEXT:prefetchwt1 (%eax)
 ; PREFETCHWT1-NEXT:prefetchw (%eax)
 ; PREFETCHWT1-NEXT:prefetchwt1 (%eax)
+; PREFETCHWT1-NEXT:prefetcht0 (%eax)
+; PREFETCHWT1-NEXT:prefetcht1 (%eax)
 ; PREFETCHWT1-NEXT:retl
 ;
 ; 3DNOW-LABEL: t:
@@ -72,7 +80,23 @@
 ; 3DNOW-NEXT:prefetchw (%eax)
 ; 3DNOW-NEXT:prefetchw (%eax)
 ; 3DNOW-NEXT:prefetchw (%eax)
+; 3DNOW-NEXT:prefetch (%eax)
+; 3DNOW-NEXT:prefetch (%eax)
 ; 3DNOW-NEXT:retl
+;
+; PREFETCHI-LABEL: t:
+; PREFETCHI:   # %bb.0: # %entry
+; PREFETCHI-NEXT:prefetcht2 (%rdi)
+;

[PATCH] D136040: [X86] Support PREFETCHI instructions

2022-10-16 Thread Phoebe Wang via Phabricator via cfe-commits 
pengfei created this revision.
Herald added a subscriber: hiraditya.
Herald added a project: All.
pengfei requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

For more details about these instructions, please refer to the latest ISE 
document: 
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136040

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/cpuid.h
  clang/lib/Headers/prfchiintrin.h
  clang/lib/Headers/x86gprintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/prefetchi-builtins.c
  clang/test/Driver/x86-target-features.c
  clang/test/Sema/builtin-prefetch.c
  llvm/include/llvm/Support/X86TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86DiscriminateMemOps.cpp
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/test/CodeGen/X86/prefetch.ll
  llvm/test/MC/Disassembler/X86/x86-64.txt
  llvm/test/MC/X86/PREFETCH-64.s

Index: llvm/test/MC/X86/PREFETCH-64.s
===
--- llvm/test/MC/X86/PREFETCH-64.s
+++ llvm/test/MC/X86/PREFETCH-64.s
@@ -168,3 +168,50 @@
 // CHECK: encoding: [0x0f,0x0d,0x12]
 prefetchwt1 (%rdx) 
 
+// CHECK: prefetchit0 485498096
+// CHECK: encoding: [0x0f,0x18,0x3c,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit0 485498096
+
+// CHECK: prefetchit0 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x7a,0x40]
+prefetchit0 64(%rdx)
+
+// CHECK: prefetchit0 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0x40]
+prefetchit0 64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x82,0xc0]
+prefetchit0 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit0 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x7c,0x02,0x40]
+prefetchit0 64(%rdx,%rax)
+
+// CHECK: prefetchit0 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x3a]
+prefetchit0 (%rdx)
+
+// CHECK: prefetchit1 485498096
+// CHECK: encoding: [0x0f,0x18,0x34,0x25,0xf0,0x1c,0xf0,0x1c]
+prefetchit1 485498096
+
+// CHECK: prefetchit1 64(%rdx)
+// CHECK: encoding: [0x0f,0x18,0x72,0x40]
+prefetchit1 64(%rdx)
+
+// CHECK: prefetchit1 64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0x40]
+prefetchit1 64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 -64(%rdx,%rax,4)
+// CHECK: encoding: [0x0f,0x18,0x74,0x82,0xc0]
+prefetchit1 -64(%rdx,%rax,4)
+
+// CHECK: prefetchit1 64(%rdx,%rax)
+// CHECK: encoding: [0x0f,0x18,0x74,0x02,0x40]
+prefetchit1 64(%rdx,%rax)
+
+// CHECK: prefetchit1 (%rdx)
+// CHECK: encoding: [0x0f,0x18,0x32]
+prefetchit1 (%rdx)
Index: llvm/test/MC/Disassembler/X86/x86-64.txt
===
--- llvm/test/MC/Disassembler/X86/x86-64.txt
+++ llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -761,3 +761,9 @@
 
 # CHECK: rdpru
 0x0f,0x01,0xfd
+
+# CHECK: prefetchit0 (%rip)
+0x0f,0x18,0x3d,0x00,0x00,0x00,0x00
+
+# CHECK: prefetchit1 (%rip)
+0x0f,0x18,0x35,0x00,0x00,0x00,0x00
Index: llvm/test/CodeGen/X86/prefetch.ll
===
--- llvm/test/CodeGen/X86/prefetch.ll
+++ llvm/test/CodeGen/X86/prefetch.ll
@@ -11,6 +11,8 @@
 ; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=3DNOW
 ; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=3DNOW
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchwt1,+prefetchi | FileCheck %s -check-prefix=PREFETCHWT1
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+prefetchwt1,+prefetchi | FileCheck %s -check-prefix=PREFETCHI
 
 ; Rules:
 ; 3dnow by itself get you just the single prefetch instruction with no hints
@@ -33,6 +35,8 @@
 ; SSE-NEXT:prefetcht1 (%eax)
 ; SSE-NEXT:prefetcht0 (%eax)
 ; SSE-NEXT:prefetchnta (%eax)
+; SSE-NEXT:prefetcht0 (%eax)
+; SSE-NEXT:prefetcht1 (%eax)
 ; SSE-NEXT:retl
 ;
 ; PRFCHWSSE-LABEL: t:
@@ -46,6 +50,8 @@
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
 ; PRFCHWSSE-NEXT:prefetchw (%eax)
+; PRFCHWSSE-NEXT:prefetcht0 (%eax)
+; PRFCHWSSE-NEXT:prefetcht1 (%eax)
 ; PRFCHWSSE-NEXT:retl
 ;
 ; PREFETCHWT1-LABEL: t:
@@ -59,6 +65,8 @@
 ; PREFETCHWT1-NEXT:prefetchwt1 (%eax)
 ; PREFETCHWT1-NEXT:prefetchw (%eax)
 ; PREFETCHWT1-NEXT:prefetchwt1 (%eax)
+; PREFETCHWT1-NEXT:prefetcht0 (%eax)
+; PREFETCHWT1-NEXT:prefetcht1 (%eax)
 ; PREFETCHWT1-NEXT:retl
 ;
 ; 3DNOW-LABEL: t:
@@ -72,7 +80,24 @@
 ; 3DNOW-NEXT:prefetchw (%eax)
 ; 3DNOW-NEXT: