[PATCH] D136817: [RISCV] Add H extension
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf4c887c3a840: [RISCV] Add H extension (authored by kito-cheng). Changed prior to commit: https://reviews.llvm.org/D136817?vs=485360&id=487624#toc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/priv-aliases-valid.s llvm/test/MC/RISCV/priv-rv64-valid.s llvm/test/MC/RISCV/priv-valid.s llvm/test/MC/RISCV/rv32h-invalid.s llvm/test/MC/RISCV/rv32ih-aliases-valid.s llvm/test/MC/RISCV/rv32ih-valid.s llvm/test/MC/RISCV/rv64h-invalid.s llvm/test/MC/RISCV/rv64ih-valid.s llvm/test/MC/RISCV/rvi-aliases-valid.s Index: llvm/test/MC/RISCV/rvi-aliases-valid.s === --- llvm/test/MC/RISCV/rvi-aliases-valid.s +++ llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -256,18 +256,6 @@ # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero # CHECK-S-OBJ: sfence.vma a0 sfence.vma a0 -# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero -# CHECK-S-OBJ: hfence.gvma -hfence.gvma -# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero -# CHECK-S-OBJ: hfence.gvma a0 -hfence.gvma a0 -# CHECK-S-OBJ-NOALIAS: hfence.vvma zero, zero -# CHECK-S-OBJ: hfence.vvma -hfence.vvma -# CHECK-S-OBJ-NOALIAS: hfence.vvma a0, zero -# CHECK-S-OBJ: hfence.vvma a0 -hfence.vvma a0 # The following aliases are accepted as input but the canonical form # of the instruction will always be printed. Index: llvm/test/MC/RISCV/rv64ih-valid.s === --- llvm/test/MC/RISCV/rv64ih-valid.s +++ llvm/test/MC/RISCV/rv64ih-valid.s @@ -1,10 +1,10 @@ -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -M no-aliases -d - \ +# RUN: llvm-mc -filetype=obj -mattr=+h -triple riscv64 < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+h < %s 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-RV32 %s # CHECK-INST: hlv.wu a0, (a1) Index: llvm/test/MC/RISCV/rv64h-invalid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv64h-invalid.s @@ -0,0 +1,12 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+h < %s 2>&1 \ +# RUN: | FileCheck %s -check-prefixes=CHECK-OFFSET +# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \ +# RUN: | FileCheck %s -check-prefixes=CHECK,CHECK-OFFSET + +hfence.vvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor) + +hlv.h a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor) + +hlv.wu a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor) + +hlv.b a0, 100(a1) # CHECK-OFFSET: :[[@LINE]]:13: error: optional integer offset must be 0 Index: llvm/test/MC/RISCV/rv32ih-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv32ih-valid.s @@ -0,0 +1,66 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: hfence.vvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x22] +hfence.vvma zero, zero + +# CHECK-INST: hfence.vvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x22] +hfence.vvma a0, a1 + +# CHECK-INST: hfence.gvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x62] +hfence.gvma zero, zero + +# CHECK-INST: hfence.gvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x62] +hfence.gvma a0, a1 + +# CHECK-INST: hlv.b a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x05,0x60] +hlv.b a0, (a1) + +# CHECK-INST: hlv.bu a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x60] +hlv.bu a0, (a1) + +# CHECK-INST: hlv.h a1, (a2) +# CHECK: encoding: [0xf3,0x45,0x06,0x64] +hlv.h a1, (a2)
[PATCH] D136817: [RISCV] Add H extension
reames accepted this revision. reames added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng added a comment. ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng updated this revision to Diff 485360. kito-cheng added a comment. Changes: - Rebase to main - Add negative test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/TargetParser/RISCVISAInfo.cpp llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/priv-aliases-valid.s llvm/test/MC/RISCV/priv-rv64-valid.s llvm/test/MC/RISCV/priv-valid.s llvm/test/MC/RISCV/rv32h-invalid.s llvm/test/MC/RISCV/rv32ih-aliases-valid.s llvm/test/MC/RISCV/rv32ih-valid.s llvm/test/MC/RISCV/rv64h-invalid.s llvm/test/MC/RISCV/rv64ih-valid.s llvm/test/MC/RISCV/rvi-aliases-valid.s Index: llvm/test/MC/RISCV/rvi-aliases-valid.s === --- llvm/test/MC/RISCV/rvi-aliases-valid.s +++ llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -256,18 +256,6 @@ # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero # CHECK-S-OBJ: sfence.vma a0 sfence.vma a0 -# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero -# CHECK-S-OBJ: hfence.gvma -hfence.gvma -# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero -# CHECK-S-OBJ: hfence.gvma a0 -hfence.gvma a0 -# CHECK-S-OBJ-NOALIAS: hfence.vvma zero, zero -# CHECK-S-OBJ: hfence.vvma -hfence.vvma -# CHECK-S-OBJ-NOALIAS: hfence.vvma a0, zero -# CHECK-S-OBJ: hfence.vvma a0 -hfence.vvma a0 # The following aliases are accepted as input but the canonical form # of the instruction will always be printed. Index: llvm/test/MC/RISCV/rv64ih-valid.s === --- llvm/test/MC/RISCV/rv64ih-valid.s +++ llvm/test/MC/RISCV/rv64ih-valid.s @@ -1,10 +1,10 @@ -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -M no-aliases -d - \ +# RUN: llvm-mc -filetype=obj -mattr=+h -triple riscv64 < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+h < %s 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-RV32 %s # CHECK-INST: hlv.wu a0, (a1) Index: llvm/test/MC/RISCV/rv64h-invalid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv64h-invalid.s @@ -0,0 +1,12 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+h < %s 2>&1 \ +# RUN: | FileCheck %s -check-prefixes=CHECK-OFFSET +# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \ +# RUN: | FileCheck %s -check-prefixes=CHECK,CHECK-OFFSET + +hfence.vvma zero, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor) + +hlv.h a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor) + +hlv.wu a0, 0(a1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor) + +hlv.b a0, 100(a1) # CHECK-OFFSET: :[[@LINE]]:13: error: optional integer offset must be 0 Index: llvm/test/MC/RISCV/rv32ih-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv32ih-valid.s @@ -0,0 +1,66 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: hfence.vvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x22] +hfence.vvma zero, zero + +# CHECK-INST: hfence.vvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x22] +hfence.vvma a0, a1 + +# CHECK-INST: hfence.gvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x62] +hfence.gvma zero, zero + +# CHECK-INST: hfence.gvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x62] +hfence.gvma a0, a1 + +# CHECK-INST: hlv.b a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x05,0x60] +hlv.b a0, (a1) + +# CHECK-INST: hlv.bu a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x60] +hlv.bu a0, (a1) + +# CHECK-INST: hlv.h a1, (a2) +# CHECK: encoding: [0xf3,0x45,0x06,0x64] +hlv.h a1, (a2) + +# CHECK-INST: hlv.hu a1, (a1) +# CHECK: encoding: [0xf3,0xc5,0x15,0x64] +hlv.hu a1, (a1) + +# CHECK-INST: hlvx.hu a1, (a2) +# CHECK: encoding: [0xf3,0x45,0x36,0x64
[PATCH] D136817: [RISCV] Add H extension
asb added a comment. Thanks Kito, I think my only remaining request would be to add at least some test coverage for using a H extensions when h isn't included in the ISA string. I don't think such tests are handled very cleanly or consistently right now, but adding something to rv32i-invalid.s alongside similar checks would be better than nothing. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng marked an inline comment as done. kito-cheng added a comment. ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: llvm/docs/RISCVUsage.rst:54 ``F``Supported + ``H``Supported ``M``Supported reames wrote: > If I'm reading the code right here, we only have assembly support here. > Given that, shouldn't this be Assembly Support? Corrected, thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng updated this revision to Diff 471701. kito-cheng added a comment. Changes: - Update doc, H is support assembly only. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/priv-aliases-valid.s llvm/test/MC/RISCV/priv-rv64-valid.s llvm/test/MC/RISCV/priv-valid.s llvm/test/MC/RISCV/rv32ih-aliases-valid.s llvm/test/MC/RISCV/rv32ih-valid.s llvm/test/MC/RISCV/rv64ih-valid.s llvm/test/MC/RISCV/rvi-aliases-valid.s Index: llvm/test/MC/RISCV/rvi-aliases-valid.s === --- llvm/test/MC/RISCV/rvi-aliases-valid.s +++ llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -256,18 +256,6 @@ # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero # CHECK-S-OBJ: sfence.vma a0 sfence.vma a0 -# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero -# CHECK-S-OBJ: hfence.gvma -hfence.gvma -# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero -# CHECK-S-OBJ: hfence.gvma a0 -hfence.gvma a0 -# CHECK-S-OBJ-NOALIAS: hfence.vvma zero, zero -# CHECK-S-OBJ: hfence.vvma -hfence.vvma -# CHECK-S-OBJ-NOALIAS: hfence.vvma a0, zero -# CHECK-S-OBJ: hfence.vvma a0 -hfence.vvma a0 # The following aliases are accepted as input but the canonical form # of the instruction will always be printed. Index: llvm/test/MC/RISCV/rv64ih-valid.s === --- llvm/test/MC/RISCV/rv64ih-valid.s +++ llvm/test/MC/RISCV/rv64ih-valid.s @@ -1,10 +1,10 @@ -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -M no-aliases -d - \ +# RUN: llvm-mc -filetype=obj -mattr=+h -triple riscv64 < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+h < %s 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-RV32 %s # CHECK-INST: hlv.wu a0, (a1) Index: llvm/test/MC/RISCV/rv32ih-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv32ih-valid.s @@ -0,0 +1,66 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: hfence.vvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x22] +hfence.vvma zero, zero + +# CHECK-INST: hfence.vvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x22] +hfence.vvma a0, a1 + +# CHECK-INST: hfence.gvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x62] +hfence.gvma zero, zero + +# CHECK-INST: hfence.gvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x62] +hfence.gvma a0, a1 + +# CHECK-INST: hlv.b a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x05,0x60] +hlv.b a0, (a1) + +# CHECK-INST: hlv.bu a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x60] +hlv.bu a0, (a1) + +# CHECK-INST: hlv.h a1, (a2) +# CHECK: encoding: [0xf3,0x45,0x06,0x64] +hlv.h a1, (a2) + +# CHECK-INST: hlv.hu a1, (a1) +# CHECK: encoding: [0xf3,0xc5,0x15,0x64] +hlv.hu a1, (a1) + +# CHECK-INST: hlvx.hu a1, (a2) +# CHECK: encoding: [0xf3,0x45,0x36,0x64] +hlvx.hu a1, (a2) + +# CHECK-INST: hlv.w a2, (a2) +# CHECK: encoding: [0x73,0x46,0x06,0x68] +hlv.w a2, (a2) + +# CHECK-INST: hlvx.wu a2, (a3) +# CHECK: encoding: [0x73,0xc6,0x36,0x68] +hlvx.wu a2, (a3) + +# CHECK-INST: hsv.b a0, (a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x62] +hsv.b a0, (a1) + +# CHECK-INST: hsv.h a0, (a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x66] +hsv.h a0, (a1) + +# CHECK-INST: hsv.w a0, (a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x6a] +hsv.w a0, (a1) Index: llvm/test/MC/RISCV/rv32ih-aliases-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv32ih-aliases-valid.s @@ -0,0 +1,70 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-ALIAS-INST %s +# RUN: llvm-mc %s
[PATCH] D136817: [RISCV] Add H extension
reames added inline comments. Comment at: llvm/docs/RISCVUsage.rst:54 ``F``Supported + ``H``Supported ``M``Supported If I'm reading the code right here, we only have assembly support here. Given that, shouldn't this be Assembly Support? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng added inline comments. Comment at: llvm/test/MC/RISCV/rvi-aliases-valid.s:270 -# CHECK-S-OBJ: hfence.vvma a0 -hfence.vvma a0 Note: Those testcase are moved to `rv32ih-aliases-valid.s`, not just removed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng updated this revision to Diff 471386. kito-cheng added a comment. Update instructions which are belong H extension now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/priv-aliases-valid.s llvm/test/MC/RISCV/priv-rv64-valid.s llvm/test/MC/RISCV/priv-valid.s llvm/test/MC/RISCV/rv32ih-aliases-valid.s llvm/test/MC/RISCV/rv32ih-valid.s llvm/test/MC/RISCV/rv64ih-valid.s llvm/test/MC/RISCV/rvi-aliases-valid.s Index: llvm/test/MC/RISCV/rvi-aliases-valid.s === --- llvm/test/MC/RISCV/rvi-aliases-valid.s +++ llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -256,18 +256,6 @@ # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero # CHECK-S-OBJ: sfence.vma a0 sfence.vma a0 -# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero -# CHECK-S-OBJ: hfence.gvma -hfence.gvma -# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero -# CHECK-S-OBJ: hfence.gvma a0 -hfence.gvma a0 -# CHECK-S-OBJ-NOALIAS: hfence.vvma zero, zero -# CHECK-S-OBJ: hfence.vvma -hfence.vvma -# CHECK-S-OBJ-NOALIAS: hfence.vvma a0, zero -# CHECK-S-OBJ: hfence.vvma a0 -hfence.vvma a0 # The following aliases are accepted as input but the canonical form # of the instruction will always be printed. Index: llvm/test/MC/RISCV/rv64ih-valid.s === --- llvm/test/MC/RISCV/rv64ih-valid.s +++ llvm/test/MC/RISCV/rv64ih-valid.s @@ -1,10 +1,10 @@ -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -M no-aliases -d - \ +# RUN: llvm-mc -filetype=obj -mattr=+h -triple riscv64 < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+h < %s 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-RV32 %s # CHECK-INST: hlv.wu a0, (a1) Index: llvm/test/MC/RISCV/rv32ih-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv32ih-valid.s @@ -0,0 +1,66 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+h < %s \ +# RUN: | llvm-objdump --mattr=+h -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: hfence.vvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x22] +hfence.vvma zero, zero + +# CHECK-INST: hfence.vvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x22] +hfence.vvma a0, a1 + +# CHECK-INST: hfence.gvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x62] +hfence.gvma zero, zero + +# CHECK-INST: hfence.gvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x62] +hfence.gvma a0, a1 + +# CHECK-INST: hlv.b a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x05,0x60] +hlv.b a0, (a1) + +# CHECK-INST: hlv.bu a0, (a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x60] +hlv.bu a0, (a1) + +# CHECK-INST: hlv.h a1, (a2) +# CHECK: encoding: [0xf3,0x45,0x06,0x64] +hlv.h a1, (a2) + +# CHECK-INST: hlv.hu a1, (a1) +# CHECK: encoding: [0xf3,0xc5,0x15,0x64] +hlv.hu a1, (a1) + +# CHECK-INST: hlvx.hu a1, (a2) +# CHECK: encoding: [0xf3,0x45,0x36,0x64] +hlvx.hu a1, (a2) + +# CHECK-INST: hlv.w a2, (a2) +# CHECK: encoding: [0x73,0x46,0x06,0x68] +hlv.w a2, (a2) + +# CHECK-INST: hlvx.wu a2, (a3) +# CHECK: encoding: [0x73,0xc6,0x36,0x68] +hlvx.wu a2, (a3) + +# CHECK-INST: hsv.b a0, (a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x62] +hsv.b a0, (a1) + +# CHECK-INST: hsv.h a0, (a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x66] +hsv.h a0, (a1) + +# CHECK-INST: hsv.w a0, (a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x6a] +hsv.w a0, (a1) Index: llvm/test/MC/RISCV/rv32ih-aliases-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/rv32ih-aliases-valid.s @@ -0,0 +1,70 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+h -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST,CHECK-ALIAS-INST %s +# RUN: llvm-mc
[PATCH] D136817: [RISCV] Add H extension
kito-cheng planned changes to this revision. kito-cheng added a comment. Let me do that within this patch :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
asb added a comment. Thanks for this patch Kito - I'm thinking that perhaps we erred in not treating the hypervisor instructions (e.g. HLV* and HSV*) as being gated on the H extension, so a sensible follow-on to this patch would be to mark those instructions as requiring FeatureStdExtH - what do you think? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D136817: [RISCV] Add H extension
kito-cheng created this revision.
kito-cheng added reviewers: asb, craig.topper, reames.
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`h` was the prefix of multi-letter extension name, but it become a
extension name in later RISC-V isa spec.
Fortunately we don't have any extension really defined is prefixed
with `h`, so we can just change that.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D136817
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -16,6 +16,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s
; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
; RUN: llc -mtriple=riscv32 -mattr=+v %s -o - | FileCheck --check-prefix=RV32V %s
+; RUN: llc -mtriple=riscv32 -mattr=+h %s -o - | FileCheck --check-prefix=RV32H %s
; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV32ZBKC %s
@@ -54,6 +55,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s
; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
; RUN: llc -mtriple=riscv64 -mattr=+v %s -o - | FileCheck --check-prefix=RV64V %s
+; RUN: llc -mtriple=riscv64 -mattr=+h %s -o - | FileCheck --check-prefix=RV64H %s
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV64ZBKC %s
@@ -95,6 +97,7 @@
; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32H: .attribute 5, "rv32i2p0_h1p0"
; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
@@ -134,6 +137,7 @@
; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64H: .attribute 5, "rv64i2p0_h1p0"
; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -57,6 +57,7 @@
bool HasStdExtZbs = false;
bool HasStdExtZca = false;
bool HasStdExtV = false;
+ bool HasStdExtH = false;
bool HasStdExtZve32x = false;
bool HasStdExtZve32f = false;
bool HasStdExtZve64x = false;
@@ -157,6 +158,7 @@
bool hasStdExtD() const { return HasStdExtD; }
bool hasStdExtC() const { return HasStdExtC; }
bool hasStdExtV() const { return HasStdExtV; }
+ bool hasStdExtH() const { return HasStdExtH; }
bool hasStdExtZihintpause() const { return HasStdExtZihintpause; }
bool hasStdExtZihintntl() const { return HasStdExtZihintntl; }
bool hasStdExtZba() const { return HasStdExtZba; }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -51,6 +51,10 @@
AssemblerPredicate<(all_of FeatureStdExtD),
"'D' (Double-Precision Floating-Point)">;
+def FeatureStdExtH
+: SubtargetFeature<"h", "HasStdExtH", "true",
+ "'H' (Hypervisor)">;
+
def FeatureStdExtZihintpause
