[PATCH] D138249: [WebAssembly] Update relaxed-simd instruction names

2022-11-21 Thread Thomas Lively via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGae96b5bd2dd0: [WebAssembly] Update relaxed-simd instruction 
names (authored by tlively).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -794,17 +794,17 @@
 # CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0x84,0x02]
 i32x4.relaxed_trunc_f64x2_u_zero
 
-# CHECK: f32x4.relaxed_fma # encoding: [0xfd,0x85,0x02]
-f32x4.relaxed_fma
+# CHECK: f32x4.relaxed_madd # encoding: [0xfd,0x85,0x02]
+f32x4.relaxed_madd
 
-# CHECK: f32x4.relaxed_fms # encoding: [0xfd,0x86,0x02]
-f32x4.relaxed_fms
+# CHECK: f32x4.relaxed_nmadd # encoding: [0xfd,0x86,0x02]
+f32x4.relaxed_nmadd
 
-# CHECK: f64x2.relaxed_fma # encoding: [0xfd,0x87,0x02]
-f64x2.relaxed_fma
+# CHECK: f64x2.relaxed_madd # encoding: [0xfd,0x87,0x02]
+f64x2.relaxed_madd
 
-# CHECK: f64x2.relaxed_fms # encoding: [0xfd,0x88,0x02]
-f64x2.relaxed_fms
+# CHECK: f64x2.relaxed_nmadd # encoding: [0xfd,0x88,0x02]
+f64x2.relaxed_nmadd
 
 # CHECK: i8x16.relaxed_laneselect # encoding: [0xfd,0x89,0x02]
 i8x16.relaxed_laneselect
@@ -833,10 +833,10 @@
 # CHECK: i16x8.relaxed_q15mulr_s # encoding: [0xfd,0x91,0x02]
 i16x8.relaxed_q15mulr_s
 
-# CHECK: i16x8.dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
-i16x8.dot_i8x16_i7x16_s
+# CHECK: i16x8.relaxed_dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
+i16x8.relaxed_dot_i8x16_i7x16_s
 
-# CHECK: i32x4.dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
-i32x4.dot_i8x16_i7x16_add_s
+# CHECK: i32x4.relaxed_dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
+i32x4.relaxed_dot_i8x16_i7x16_add_s
 
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -184,9 +184,9 @@
 ; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
-  %v = call <16 x i8> @llvm.wasm.laneselect.v16i8(
+  %v = call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(
 <16 x i8> %a, <16 x i8> %b, <16 x i8> %c
   )
   ret <16 x i8> %v
@@ -360,9 +360,9 @@
 ; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
-  %v = call <8 x i16> @llvm.wasm.laneselect.v8i16(
+  %v = call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(
 <8 x i16> %a, <8 x i16> %b, <8 x i16> %c
   )
   ret <8 x i16> %v
@@ -382,11 +382,11 @@
 
 ; CHECK-LABEL: dot_i8x16_i7x16_s_i16x8:
 ; CHECK-NEXT: .functype dot_i8x16_i7x16_s_i16x8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
 define <8 x i16> @dot_i8x16_i7x16_s_i16x8(<16 x i8> %a, <16 x i8> %b) {
-  %v = call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(
+  %v = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(
 <16 x i8> %a, <16 x i8> %b
   )
   ret <8 x i16> %v
@@ -542,9 +542,9 @@
 ; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define

[PATCH] D138249: [WebAssembly] Update relaxed-simd instruction names

2022-11-18 Thread Marat Dukhan via Phabricator via cfe-commits 
maratyszcza accepted this revision.
maratyszcza added a comment.

Intrinsic naming LGTM. Not qualified to review the rest.


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[PATCH] D138249: [WebAssembly] Update relaxed-simd instruction names

2022-11-18 Thread Thomas Lively via Phabricator via cfe-commits 
tlively updated this revision to Diff 476490.
tlively added a comment.

- Fix type


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138249/new/

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Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -794,17 +794,17 @@
 # CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0x84,0x02]
 i32x4.relaxed_trunc_f64x2_u_zero
 
-# CHECK: f32x4.relaxed_fma # encoding: [0xfd,0x85,0x02]
-f32x4.relaxed_fma
+# CHECK: f32x4.relaxed_madd # encoding: [0xfd,0x85,0x02]
+f32x4.relaxed_madd
 
-# CHECK: f32x4.relaxed_fms # encoding: [0xfd,0x86,0x02]
-f32x4.relaxed_fms
+# CHECK: f32x4.relaxed_nmadd # encoding: [0xfd,0x86,0x02]
+f32x4.relaxed_nmadd
 
-# CHECK: f64x2.relaxed_fma # encoding: [0xfd,0x87,0x02]
-f64x2.relaxed_fma
+# CHECK: f64x2.relaxed_madd # encoding: [0xfd,0x87,0x02]
+f64x2.relaxed_madd
 
-# CHECK: f64x2.relaxed_fms # encoding: [0xfd,0x88,0x02]
-f64x2.relaxed_fms
+# CHECK: f64x2.relaxed_nmadd # encoding: [0xfd,0x88,0x02]
+f64x2.relaxed_nmadd
 
 # CHECK: i8x16.relaxed_laneselect # encoding: [0xfd,0x89,0x02]
 i8x16.relaxed_laneselect
@@ -833,10 +833,10 @@
 # CHECK: i16x8.relaxed_q15mulr_s # encoding: [0xfd,0x91,0x02]
 i16x8.relaxed_q15mulr_s
 
-# CHECK: i16x8.dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
-i16x8.dot_i8x16_i7x16_s
+# CHECK: i16x8.relaxed_dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
+i16x8.relaxed_dot_i8x16_i7x16_s
 
-# CHECK: i32x4.dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
-i32x4.dot_i8x16_i7x16_add_s
+# CHECK: i32x4.relaxed_dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
+i32x4.relaxed_dot_i8x16_i7x16_add_s
 
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -184,9 +184,9 @@
 ; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
-  %v = call <16 x i8> @llvm.wasm.laneselect.v16i8(
+  %v = call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(
 <16 x i8> %a, <16 x i8> %b, <16 x i8> %c
   )
   ret <16 x i8> %v
@@ -360,9 +360,9 @@
 ; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
-  %v = call <8 x i16> @llvm.wasm.laneselect.v8i16(
+  %v = call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(
 <8 x i16> %a, <8 x i16> %b, <8 x i16> %c
   )
   ret <8 x i16> %v
@@ -382,11 +382,11 @@
 
 ; CHECK-LABEL: dot_i8x16_i7x16_s_i16x8:
 ; CHECK-NEXT: .functype dot_i8x16_i7x16_s_i16x8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
 define <8 x i16> @dot_i8x16_i7x16_s_i16x8(<16 x i8> %a, <16 x i8> %b) {
-  %v = call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(
+  %v = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(
 <16 x i8> %a, <16 x i8> %b
   )
   ret <8 x i16> %v
@@ -542,9 +542,9 @@
 ; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.wasm.relaxed.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
-  %v = call <4 x i32> @llv

[PATCH] D138249: [WebAssembly] Update relaxed-simd instruction names

2022-11-18 Thread Thomas Lively via Phabricator via cfe-commits 
tlively added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsWebAssembly.def:180
 TARGET_BUILTIN(__builtin_wasm_relaxed_min_f64x2, "V2dV2dV2d", "nc", 
"relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nc", 
"relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nC", 
"relaxed-simd")
 

maratyszcza wrote:
> Typo?
Yep, thanks.


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[PATCH] D138249: [WebAssembly] Update relaxed-simd instruction names

2022-11-18 Thread Marat Dukhan via Phabricator via cfe-commits 
maratyszcza added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsWebAssembly.def:180
 TARGET_BUILTIN(__builtin_wasm_relaxed_min_f64x2, "V2dV2dV2d", "nc", 
"relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nc", 
"relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nC", 
"relaxed-simd")
 

Typo?


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[PATCH] D138249: [WebAssembly] Update relaxed-simd instruction names

2022-11-17 Thread Thomas Lively via Phabricator via cfe-commits 
tlively created this revision.
tlively added reviewers: aheejin, maratyszcza.
Herald added subscribers: pmatos, asb, wingo, ecnelises, sunfish, hiraditya, 
jgravelle-google, sbc100, dschuff.
Herald added a project: All.
tlively requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Including builtin and intrinsic names. These should be the final names for the
proposal.
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138249

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -794,17 +794,17 @@
 # CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0x84,0x02]
 i32x4.relaxed_trunc_f64x2_u_zero
 
-# CHECK: f32x4.relaxed_fma # encoding: [0xfd,0x85,0x02]
-f32x4.relaxed_fma
+# CHECK: f32x4.relaxed_madd # encoding: [0xfd,0x85,0x02]
+f32x4.relaxed_madd
 
-# CHECK: f32x4.relaxed_fms # encoding: [0xfd,0x86,0x02]
-f32x4.relaxed_fms
+# CHECK: f32x4.relaxed_nmadd # encoding: [0xfd,0x86,0x02]
+f32x4.relaxed_nmadd
 
-# CHECK: f64x2.relaxed_fma # encoding: [0xfd,0x87,0x02]
-f64x2.relaxed_fma
+# CHECK: f64x2.relaxed_madd # encoding: [0xfd,0x87,0x02]
+f64x2.relaxed_madd
 
-# CHECK: f64x2.relaxed_fms # encoding: [0xfd,0x88,0x02]
-f64x2.relaxed_fms
+# CHECK: f64x2.relaxed_nmadd # encoding: [0xfd,0x88,0x02]
+f64x2.relaxed_nmadd
 
 # CHECK: i8x16.relaxed_laneselect # encoding: [0xfd,0x89,0x02]
 i8x16.relaxed_laneselect
@@ -833,10 +833,10 @@
 # CHECK: i16x8.relaxed_q15mulr_s # encoding: [0xfd,0x91,0x02]
 i16x8.relaxed_q15mulr_s
 
-# CHECK: i16x8.dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
-i16x8.dot_i8x16_i7x16_s
+# CHECK: i16x8.relaxed_dot_i8x16_i7x16_s # encoding: [0xfd,0x92,0x02]
+i16x8.relaxed_dot_i8x16_i7x16_s
 
-# CHECK: i32x4.dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
-i32x4.dot_i8x16_i7x16_add_s
+# CHECK: i32x4.relaxed_dot_i8x16_i7x16_add_s # encoding: [0xfd,0x93,0x02]
+i32x4.relaxed_dot_i8x16_i7x16_add_s
 
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -184,9 +184,9 @@
 ; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
 define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
-  %v = call <16 x i8> @llvm.wasm.laneselect.v16i8(
+  %v = call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(
 <16 x i8> %a, <16 x i8> %b, <16 x i8> %c
   )
   ret <16 x i8> %v
@@ -360,9 +360,9 @@
 ; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
 define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
-  %v = call <8 x i16> @llvm.wasm.laneselect.v8i16(
+  %v = call <8 x i16> @llvm.wasm.relaxed.laneselect.v8i16(
 <8 x i16> %a, <8 x i16> %b, <8 x i16> %c
   )
   ret <8 x i16> %v
@@ -382,11 +382,11 @@
 
 ; CHECK-LABEL: dot_i8x16_i7x16_s_i16x8:
 ; CHECK-NEXT: .functype dot_i8x16_i7x16_s_i16x8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.relaxed_dot_i8x16_i7x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
 define <8 x i16> @dot_i8x16_i7x16_s_i16x8(<16 x i8> %a, <16 x i8> %b) {
-  %v = call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(
+  %v = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(
 <16 x i8> %a, <16 x i8> %b
   )
   ret <8 x i16> %v
@@ -542,9 +542,9 @@
 ; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; CHEC