Re: [PATCH] D13980: Add "x87" in x86 target feature map

2016-03-23 Thread Andrey Turetskiy via cfe-commits 
aturetsk added a comment.

The test Eric asked for was added.


Repository:
  rL LLVM

http://reviews.llvm.org/D13980



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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2016-03-23 Thread Andrey Turetskiy via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL264149: [X86] Add "x87" in x86 target feature map. (authored 
by aturetsk).

Changed prior to commit:
  http://reviews.llvm.org/D13980?vs=48904&id=51398#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D13980

Files:
  cfe/trunk/lib/Basic/Targets.cpp
  cfe/trunk/test/CodeGen/attr-target-x86-mmx.c
  cfe/trunk/test/CodeGen/attr-target-x86.c
  cfe/trunk/test/CodeGen/attr-target-x87-softfp.c

Index: cfe/trunk/test/CodeGen/attr-target-x86.c
===
--- cfe/trunk/test/CodeGen/attr-target-x86.c
+++ cfe/trunk/test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
+// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes"
+// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,+x87,-3dnow,-3dnowa,-mmx"
Index: cfe/trunk/test/CodeGen/attr-target-x87-softfp.c
===
--- cfe/trunk/test/CodeGen/attr-target-x87-softfp.c
+++ cfe/trunk/test/CodeGen/attr-target-x87-softfp.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -triple x86_64-linux-gnu -target-cpu x86-64 -emit-llvm %s 
-o - | FileCheck %s -check-prefix=CHECK -check-prefix=HARD
+// RUN: %clang_cc1 -msoft-float -triple x86_64-linux-gnu -target-cpu x86-64 
-emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT
+
+int __attribute__((target("x87"))) foo(int a) { return 4; }
+int __attribute__((target("no-x87"))) bar(int a) { return 4; }
+
+// CHECK: foo{{.*}} #0
+// CHECK: bar{{.*}} #1
+
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// HARD: "use-soft-float"="false"
+// SOFT: "use-soft-float"="true"
+
+// CHECK: #1 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,-x87"
+// HARD: "use-soft-float"="false"
+// SOFT: "use-soft-float"="true"
Index: cfe/trunk/test/CodeGen/attr-target-x86-mmx.c
===
--- cfe/trunk/test/CodeGen/attr-target-x86-mmx.c
+++ cfe/trunk/test/CodeGen/attr-target-x86-mmx.c
@@ -19,4 +19,4 @@
   _mm_srai_pi32(a, c);
 }
 
-// CHECK: "target-features"="+mmx,+sse"
+// CHECK: "target-features"="+mmx,+sse,+x87"
Index: cfe/trunk/lib/Basic/Targets.cpp
===
--- cfe/trunk/lib/Basic/Targets.cpp
+++ cfe/trunk/lib/Basic/Targets.cpp
@@ -2585,6 +2585,9 @@
   if (getTriple().getArch() == llvm::Triple::x86_64)
 setFeatureEnabledImpl(Features, "sse2", true);
 
+  // Enable X87 for all X86 processors.
+  setFeatureEnabledImpl(Features, "x87", true);
+
   switch (getCPUKind(CPU)) {
   case CK_Generic:
   case CK_i386:


Index: cfe/trunk/test/CodeGen/attr-target-x86.c
===
--- cfe/trunk/test/CodeGen/attr-target-x86.c
+++ cfe/trunk/test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+

Re: [PATCH] D13980: Add "x87" in x86 target feature map

2016-02-26 Thread Eric Christopher via cfe-commits 
echristo accepted this revision.
echristo added a reviewer: echristo.
echristo added a comment.
This revision is now accepted and ready to land.

LGTM.

Thanks!

-eric


http://reviews.llvm.org/D13980



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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2016-02-26 Thread Richard Smith via cfe-commits 
rsmith added inline comments.


Comment at: lib/Basic/Targets.cpp:2603
@@ -2599,3 +2602,3 @@
   case CK_i386:
   case CK_i486:
   case CK_i586:

echristo wrote:
> Waiting for rsmith to comment here.
> 
> 
This seems fine to me.


http://reviews.llvm.org/D13980



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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2016-02-26 Thread Eric Christopher via cfe-commits 
echristo added a comment.

Can you add an explicit test for soft/hard-float.

One inline comment as well, waiting on Richard to pipe up.

-eric



Comment at: lib/Basic/Targets.cpp:2603
@@ -2599,3 +2602,3 @@
   case CK_i386:
   case CK_i486:
   case CK_i586:

Waiting for rsmith to comment here.




http://reviews.llvm.org/D13980



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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2016-02-24 Thread Andrey Turetskiy via cfe-commits 
aturetsk added a comment.

Hi,
The related LLVM patch (http://reviews.llvm.org/D13979) was approved. Is this 
patch ok for commit?


http://reviews.llvm.org/D13980



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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2016-02-24 Thread Andrey Turetskiy via cfe-commits 
aturetsk updated this revision to Diff 48904.
aturetsk added a comment.

Rebased.


http://reviews.llvm.org/D13980

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/attr-target-x86-mmx.c
  test/CodeGen/attr-target-x86.c

Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
+// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes"
+// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,+x87,-3dnow,-3dnowa,-mmx"
Index: test/CodeGen/attr-target-x86-mmx.c
===
--- test/CodeGen/attr-target-x86-mmx.c
+++ test/CodeGen/attr-target-x86-mmx.c
@@ -19,4 +19,4 @@
   _mm_srai_pi32(a, c);
 }
 
-// CHECK: "target-features"="+mmx,+sse"
+// CHECK: "target-features"="+mmx,+sse,+x87"
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2594,6 +2594,9 @@
   if (getTriple().getArch() == llvm::Triple::x86_64)
 setFeatureEnabledImpl(Features, "sse2", true);
 
+  // Enable X87 for all X86 processors.
+  setFeatureEnabledImpl(Features, "x87", true);
+
   switch (getCPUKind(CPU)) {
   case CK_Generic:
   case CK_i386:


Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "targe

Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-12-01 Thread Andrey Turetskiy via cfe-commits 
aturetsk added inline comments.


Comment at: lib/Basic/Targets.cpp:2551
@@ -2547,3 +2550,3 @@
   case CK_i386:
   case CK_i486:
   case CK_i586:

"x87 instructions probably work" is more like it, and having feature x87 
disabled would mean "x87 instructions definitely don't work". That's what I 
intended. If feature soft float is specified it takes precedence over feature 
x87 causing compiler to generate calls instead of X87 instructions.
Support of -m80387/-mno-80387 seems to be a good thing to have in Clang to be 
compatible with GCC (although briefly looking at GCC's sources these options 
just seem to be synonyms to -mhard-float/-msoft-float). I can add the flags, 
but I think that's better to be done in a separate patch.


http://reviews.llvm.org/D13980



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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-12-01 Thread Andrey Turetskiy via cfe-commits 
aturetsk updated this revision to Diff 41511.
aturetsk added a comment.

Enable X87 back for all X86 processors.


http://reviews.llvm.org/D13980

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/attr-target-x86-mmx.c
  test/CodeGen/attr-target-x86.c

Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
+// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes"
+// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,+x87,-3dnow,-3dnowa,-mmx"
Index: test/CodeGen/attr-target-x86-mmx.c
===
--- test/CodeGen/attr-target-x86-mmx.c
+++ test/CodeGen/attr-target-x86-mmx.c
@@ -19,4 +19,4 @@
   _mm_srai_pi32(a, c);
 }
 
-// CHECK: "target-features"="+mmx,+sse"
+// CHECK: "target-features"="+mmx,+sse,+x87"
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2542,6 +2542,9 @@
   if (getTriple().getArch() == llvm::Triple::x86_64)
 setFeatureEnabledImpl(Features, "sse2", true);
 
+  // Enable X87 for all X86 processors.
+  setFeatureEnabledImpl(Features, "x87", true);
+
   switch (getCPUKind(CPU)) {
   case CK_Generic:
   case CK_i386:


Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.

Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-30 Thread Richard Smith via cfe-commits 
rsmith added inline comments.


Comment at: lib/Basic/Targets.cpp:2548
@@ +2547,3 @@
+  // All X86 processors but i386 have X87.
+  if (Kind != CK_i386)
+setFeatureEnabledImpl(Features, "x87", true);

aturetsk wrote:
> rsmith wrote:
> > What about `CK_Generic`? Also, if `CK_i486` can be used for the 486SX, we 
> > need to exclude it here too. It looks (from wikipedia) like all the 
> > "WinChip" flavours of 486 have an x87 unit, but it'd be nice if someone 
> > could confirm that. Maybe we should have separate `CPUKind`s for 486 SX 
> > versus 486 DX.
> Before this changeset clang would generate x87 instructions for Generic, i386 
> and i486. So one can say they had FeatureX87 enabled implicitly. If that was 
> ok formerly why do we want to change that now? Wouldn't it be better to keep 
> clang's behavior unchanged?
OK, if this means "x87 instructions probably work" (although they may be 
emulated in software) and not "x87 instructions definitely work", then we 
shouldn't be checking the CPU kind here at all. It looks like the former is how 
GCC handles this; it has `-mno-80387` to specify that we're building for an 
i386 with no support for x87 instructions. Should we handle that flag?


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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-30 Thread Andrey Turetskiy via cfe-commits 
aturetsk added inline comments.


Comment at: lib/Basic/Targets.cpp:2548
@@ +2547,3 @@
+  // All X86 processors but i386 have X87.
+  if (Kind != CK_i386)
+setFeatureEnabledImpl(Features, "x87", true);

rsmith wrote:
> What about `CK_Generic`? Also, if `CK_i486` can be used for the 486SX, we 
> need to exclude it here too. It looks (from wikipedia) like all the "WinChip" 
> flavours of 486 have an x87 unit, but it'd be nice if someone could confirm 
> that. Maybe we should have separate `CPUKind`s for 486 SX versus 486 DX.
Before this changeset clang would generate x87 instructions for Generic, i386 
and i486. So one can say they had FeatureX87 enabled implicitly. If that was ok 
formerly why do we want to change that now? Wouldn't it be better to keep 
clang's behavior unchanged?


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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-25 Thread Richard Smith via cfe-commits 
rsmith added inline comments.


Comment at: lib/Basic/Targets.cpp:2548
@@ +2547,3 @@
+  // All X86 processors but i386 have X87.
+  if (Kind != CK_i386)
+setFeatureEnabledImpl(Features, "x87", true);

What about `CK_Generic`? Also, if `CK_i486` can be used for the 486SX, we need 
to exclude it here too. It looks (from wikipedia) like all the "WinChip" 
flavours of 486 have an x87 unit, but it'd be nice if someone could confirm 
that. Maybe we should have separate `CPUKind`s for 486 SX versus 486 DX.


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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-25 Thread Andrey Turetskiy via cfe-commits 
aturetsk added a comment.

> Are there any of the intrinsics in the headers that also depend on x87?


Not that I could find.



Comment at: lib/Basic/Targets.cpp:2545-2546
@@ -2544,2 +2544,4 @@
 
-  switch (getCPUKind(CPU)) {
+  CPUKind Kind = getCPUKind(CPU);
+
+  // All X86 processors but i386 have X87.

Done.


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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-25 Thread Andrey Turetskiy via cfe-commits 
aturetsk updated this revision to Diff 41137.
aturetsk added a comment.

Use getCPUKind once


http://reviews.llvm.org/D13980

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/attr-target-x86-mmx.c
  test/CodeGen/attr-target-x86.c

Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -18,6 +18,8 @@
 
 int __attribute__((target("no-mmx"))) qq(int a) { return 40; }
 
+int __attribute__((target("arch=i386"))) qix(int a) { return 4; }
+
 // Check that we emit the additional subtarget and cpu features for foo and 
not for baz or bar.
 // CHECK: baz{{.*}} #0
 // CHECK: foo{{.*}} #1
@@ -31,9 +33,11 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: qix{{.*}} #6
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
+// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes"
+// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,+x87,-3dnow,-3dnowa,-mmx"
+// CHECK: #6 = {{.*}}"target-cpu"="i386" "target-features"="+mmx,+sse,+sse2"
Index: test/CodeGen/attr-target-x86-mmx.c
===
--- test/CodeGen/attr-target-x86-mmx.c
+++ test/CodeGen/attr-target-x86-mmx.c
@@ -19,4 +19,4 @@
   _mm_srai_pi32(a, c);
 }
 
-// CHECK: "target-features"="+mmx,+sse"
+// CHECK: "target-features"="+mmx,+sse,+x87"
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2542,7 +2542,13 @@
   if (getTriple().getArch() == llvm::Triple::x86_64)
 setFeatureEnabledImpl(Features, "sse2", true);
 
-  switch (getCPUKind(CPU)) {
+  CPUKind Kind = getCPUKind(CPU);
+
+  // All X86 processors but i386 have X87.
+  if (Kind != CK_i386)
+setFeatureEnabledImpl(Features, "x87", true);
+
+  switch (Kind) {
   case CK_Generic:
   case CK_i386:
   case CK_i486:


Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -18,6 +18,8 @@
 
 int __attribute__((target("no-mmx"))) qq(int a) { return 40; }
 
+int __attribute__((target("arch=i386"))) qix(int a) { return 4; }
+
 // Check that we emit the additional subtarget and cpu features for foo and not for baz or bar.
 // CHECK: baz{{.*}} #0
 // CHECK: foo{{.*}} #1
@@ -31,9 +33,11 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+

Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-19 Thread Eric Christopher via cfe-commits 
echristo added a subscriber: echristo.
echristo added a comment.

Are there any of the intrinsics in the headers that also depend on x87?

One inline comment.

-eric



Comment at: lib/Basic/Targets.cpp:2538-2539
@@ -2537,1 +2537,4 @@
 
+  // All X86 processors but i386 have X87.
+  if (getCPUKind(CPU) != CK_i386)
+setFeatureEnabledImpl(Features, "x87", true);

aturetsk wrote:
> You are right. Fixed.
Mind only doing getCPUKind once here? :)


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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-19 Thread Andrey Turetskiy via cfe-commits 
aturetsk added a comment.

Hello Richard,
Thank for the review.



Comment at: lib/Basic/Targets.cpp:2538-2539
@@ -2537,1 +2537,4 @@
 
+  // All X86 processors but i386 have X87.
+  if (getCPUKind(CPU) != CK_i386)
+setFeatureEnabledImpl(Features, "x87", true);

You are right. Fixed.


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Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-19 Thread Andrey Turetskiy via cfe-commits 
aturetsk updated this revision to Diff 40645.
aturetsk added a comment.

Do not enable X87 for i386


http://reviews.llvm.org/D13980

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/attr-target-x86-mmx.c
  test/CodeGen/attr-target-x86.c

Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -18,6 +18,8 @@
 
 int __attribute__((target("no-mmx"))) qq(int a) { return 40; }
 
+int __attribute__((target("arch=i386"))) qix(int a) { return 4; }
+
 // Check that we emit the additional subtarget and cpu features for foo and 
not for baz or bar.
 // CHECK: baz{{.*}} #0
 // CHECK: foo{{.*}} #1
@@ -31,9 +33,11 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: qix{{.*}} #6
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
+// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes"
+// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,+x87,-3dnow,-3dnowa,-mmx"
+// CHECK: #6 = {{.*}}"target-cpu"="i386" "target-features"="+mmx,+sse,+sse2"
Index: test/CodeGen/attr-target-x86-mmx.c
===
--- test/CodeGen/attr-target-x86-mmx.c
+++ test/CodeGen/attr-target-x86-mmx.c
@@ -19,4 +19,4 @@
   _mm_srai_pi32(a, c);
 }
 
-// CHECK: "target-features"="+mmx,+sse"
+// CHECK: "target-features"="+mmx,+sse,+x87"
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2535,6 +2535,10 @@
   if (getTriple().getArch() == llvm::Triple::x86_64)
 setFeatureEnabledImpl(Features, "sse2", true);
 
+  // All X86 processors but i386 have X87.
+  if (getCPUKind(CPU) != CK_i386)
+setFeatureEnabledImpl(Features, "x87", true);
+
   switch (getCPUKind(CPU)) {
   case CK_Generic:
   case CK_i386:


Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -18,6 +18,8 @@
 
 int __attribute__((target("no-mmx"))) qq(int a) { return 40; }
 
+int __attribute__((target("arch=i386"))) qix(int a) { return 4; }
+
 // Check that we emit the additional subtarget and cpu features for foo and not for baz or bar.
 // CHECK: baz{{.*}} #0
 // CHECK: foo{{.*}} #1
@@ -31,9 +33,11 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,

Re: [PATCH] D13980: Add "x87" in x86 target feature map

2015-11-03 Thread Richard Smith via cfe-commits 
rsmith added inline comments.


Comment at: lib/Basic/Targets.cpp:2516-2517
@@ -2515,1 +2515,4 @@
 
+  // X86 always has X87.
+  setFeatureEnabledImpl(Features, "x87", true);
+

i386 doesn't necessarily have x87, does it? IIRC the floating point 
co-processor is only guaranteed to be available in the 486 DX and later.


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[PATCH] D13980: Add "x87" in x86 target feature map

2015-10-22 Thread Andrey Turetskiy via cfe-commits 
aturetsk created this revision.
aturetsk added a reviewer: rsmith.
aturetsk added a subscriber: cfe-commits.

Add 'x87' in x86 target feature map

http://reviews.llvm.org/D13980

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/attr-target-x86-mmx.c
  test/CodeGen/attr-target-x86.c

Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+// CHECK: #3 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
+// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes"
+// CHECK: #5 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+fxsr,+sse,+sse2,+x87,-3dnow,-3dnowa,-mmx"
Index: test/CodeGen/attr-target-x86-mmx.c
===
--- test/CodeGen/attr-target-x86-mmx.c
+++ test/CodeGen/attr-target-x86-mmx.c
@@ -19,4 +19,4 @@
   _mm_srai_pi32(a, c);
 }
 
-// CHECK: "target-features"="+mmx,+sse"
+// CHECK: "target-features"="+mmx,+sse,+x87"
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2513,6 +2513,9 @@
   if (getTriple().getArch() == llvm::Triple::x86_64)
 setFeatureEnabledImpl(Features, "sse2", true);
 
+  // X86 always has X87.
+  setFeatureEnabledImpl(Features, "x87", true);
+
   switch (getCPUKind(CPU)) {
   case CK_Generic:
   case CK_i386:


Index: test/CodeGen/attr-target-x86.c
===
--- test/CodeGen/attr-target-x86.c
+++ test/CodeGen/attr-target-x86.c
@@ -31,9 +31,9 @@
 // CHECK: qux{{.*}} #1
 // CHECK: qax{{.*}} #4
 // CHECK: qq{{.*}} #5
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
-// CHECK: #3 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3"
-// CHECK: #4 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+xsave,+xsaveopt,-aes"
-// CHECK: #5 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+sse,+sse2,-3dnow,-3dnowa,-mmx"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512pf,-avx512vl,-f16c,-fma,-fma4,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-xop,-xsave,-xsaveopt"
+/