[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG235e90c1d760: [Clang][RISCV] Guard vector float16 type 
correctly with semantic analysis (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143657/new/

https://reviews.llvm.org/D143657

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -368,14 +368,13 @@
   }
 }
   }
-  OS << "#if defined(__riscv_zvfh)\n";
+
   for (int Log2LMUL : Log2LMULs) {
 auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
PrototypeDescriptor::Vector);
 if (T)
   printType(*T);
   }
-  OS << "#endif\n";
 
   OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- /dev/null
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include 
+
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -171,7 +171,6 @@
   const TargetInfo  = Context.getTargetInfo();
   bool HasVectorFloat32 = TI.hasFeature("zve32f");
   bool HasVectorFloat64 = TI.hasFeature("zve64d");
-  bool HasZvfh = TI.hasFeature("experimental-zvfh");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
@@ -223,9 +222,6 @@
 continue;
 
   // Check requirement.
-  if (BaseType == BasicType::Float16 && !HasZvfh)
-continue;
-
   if (BaseType == BasicType::Float32 && !HasVectorFloat32)
 continue;
 
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2039,6 +2039,12 @@
 targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
 }
 
+if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
+!Context.getTargetInfo().hasFeature("experimental-zvfh")) {
+  Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+  << Ty << "zvfh";
+}
+
 // Don't allow SVE types in functions without a SVE target.
 if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
   llvm::StringMap CallerFeatureMap;
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===
--- clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11738,6 +11738,9 @@
   "builtin requires%select{| at least one of the following extensions to be enabled}0: %1">;
 def err_riscv_builtin_invalid_lmul : Error<
   "LMUL argument must be in the range [0,3] or [5,7]">;
+def err_riscv_type_requires_extension : Error<
+  "RISC-V type %0 requires the '%1' extension"
+>;
 
 def err_std_source_location_impl_not_found : Error<
   "'std::source_location::__impl' was not found; it must be defined before '__builtin_source_location' is called">;
Index: clang/include/clang/AST/Type.h
===
--- clang/include/clang/AST/Type.h
+++ clang/include/clang/AST/Type.h
@@ -2275,6 +2275,8 @@
 
   bool isRVVType() const;
 
+  bool isRVVType(unsigned Bitwidth, bool IsFloat) const;
+
   /// Return the implicit lifetime for this type, which must not be dependent.
   Qualifiers::ObjCLifetime getObjCARCImplicitLifetime() const;
 
@@ -7153,6 +7155,17 @@
 false; // end of boolean or operation.
 }
 
+inline bool Type::isRVVType(unsigned Bitwidth, bool IsFloat) const {
+  bool Ret = false;
+#define RVV_TYPE(Name, Id, SingletonId)
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,   \
+IsFP)  \
+  if (ElBits == Bitwidth && IsFloat == IsFP)   \
+Ret |= isSpecificBuiltinType(BuiltinType::Id);
+#include 

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 496680.
eopXD added a comment.

Address comment from Craig.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143657/new/

https://reviews.llvm.org/D143657

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -368,14 +368,13 @@
   }
 }
   }
-  OS << "#if defined(__riscv_zvfh)\n";
+
   for (int Log2LMUL : Log2LMULs) {
 auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
PrototypeDescriptor::Vector);
 if (T)
   printType(*T);
   }
-  OS << "#endif\n";
 
   OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- /dev/null
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include 
+
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -171,7 +171,6 @@
   const TargetInfo  = Context.getTargetInfo();
   bool HasVectorFloat32 = TI.hasFeature("zve32f");
   bool HasVectorFloat64 = TI.hasFeature("zve64d");
-  bool HasZvfh = TI.hasFeature("experimental-zvfh");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
@@ -223,9 +222,6 @@
 continue;
 
   // Check requirement.
-  if (BaseType == BasicType::Float16 && !HasZvfh)
-continue;
-
   if (BaseType == BasicType::Float32 && !HasVectorFloat32)
 continue;
 
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2046,6 +2046,12 @@
 targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
 }
 
+if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
+!Context.getTargetInfo().hasFeature("experimental-zvfh")) {
+  Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+  << Ty << "zvfh";
+}
+
 // Don't allow SVE types in functions without a SVE target.
 if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
   llvm::StringMap CallerFeatureMap;
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===
--- clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11738,6 +11738,9 @@
   "builtin requires%select{| at least one of the following extensions to be enabled}0: %1">;
 def err_riscv_builtin_invalid_lmul : Error<
   "LMUL argument must be in the range [0,3] or [5,7]">;
+def err_riscv_type_requires_extension : Error<
+  "RISC-V type %0 requires the '%1' extension"
+>;
 
 def err_std_source_location_impl_not_found : Error<
   "'std::source_location::__impl' was not found; it must be defined before '__builtin_source_location' is called">;
Index: clang/include/clang/AST/Type.h
===
--- clang/include/clang/AST/Type.h
+++ clang/include/clang/AST/Type.h
@@ -2279,6 +2279,8 @@
 
   bool isRVVType() const;
 
+  bool isRVVType(unsigned Bitwidth, bool IsFloat) const;
+
   /// Return the implicit lifetime for this type, which must not be dependent.
   Qualifiers::ObjCLifetime getObjCARCImplicitLifetime() const;
 
@@ -7160,6 +7162,17 @@
 false; // end of boolean or operation.
 }
 
+inline bool Type::isRVVType(unsigned Bitwidth, bool IsFloat) const {
+  bool Ret = false;
+#define RVV_TYPE(Name, Id, SingletonId)
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,   \
+IsFP)  \
+  if (ElBits == Bitwidth && IsFloat == IsFP)   \
+Ret |= isSpecificBuiltinType(BuiltinType::Id);
+#include "clang/Basic/RISCVVTypes.def"
+  return Ret;
+}
+
 inline bool Type::isTemplateTypeParmType() const {
   return isa(CanonicalType);
 }
___

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.



Comment at: clang/lib/Sema/Sema.cpp:2052
+  Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+  << Ty << "experimental-zvfh";
+}

experimental- is an internal naming scheme. "experimental-" is not used in 
-march so it should be in the error message.


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[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 496382.
eopXD added a comment.

Update code: use a more scalable way to check for RVV type.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143657/new/

https://reviews.llvm.org/D143657

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -368,14 +368,13 @@
   }
 }
   }
-  OS << "#if defined(__riscv_zvfh)\n";
+
   for (int Log2LMUL : Log2LMULs) {
 auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
PrototypeDescriptor::Vector);
 if (T)
   printType(*T);
   }
-  OS << "#endif\n";
 
   OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- /dev/null
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include 
+
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'experimental-zvfh' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -171,7 +171,6 @@
   const TargetInfo  = Context.getTargetInfo();
   bool HasVectorFloat32 = TI.hasFeature("zve32f");
   bool HasVectorFloat64 = TI.hasFeature("zve64d");
-  bool HasZvfh = TI.hasFeature("experimental-zvfh");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
@@ -223,9 +222,6 @@
 continue;
 
   // Check requirement.
-  if (BaseType == BasicType::Float16 && !HasZvfh)
-continue;
-
   if (BaseType == BasicType::Float32 && !HasVectorFloat32)
 continue;
 
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2046,6 +2046,12 @@
 targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
 }
 
+if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
+!Context.getTargetInfo().hasFeature("experimental-zvfh")) {
+  Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+  << Ty << "experimental-zvfh";
+}
+
 // Don't allow SVE types in functions without a SVE target.
 if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
   llvm::StringMap CallerFeatureMap;
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===
--- clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11738,6 +11738,9 @@
   "builtin requires%select{| at least one of the following extensions to be enabled}0: %1">;
 def err_riscv_builtin_invalid_lmul : Error<
   "LMUL argument must be in the range [0,3] or [5,7]">;
+def err_riscv_type_requires_extension : Error<
+  "RISC-V type %0 requires the '%1' extension"
+>;
 
 def err_std_source_location_impl_not_found : Error<
   "'std::source_location::__impl' was not found; it must be defined before '__builtin_source_location' is called">;
Index: clang/include/clang/AST/Type.h
===
--- clang/include/clang/AST/Type.h
+++ clang/include/clang/AST/Type.h
@@ -2279,6 +2279,8 @@
 
   bool isRVVType() const;
 
+  bool isRVVType(unsigned Bitwidth, bool IsFloat) const;
+
   /// Return the implicit lifetime for this type, which must not be dependent.
   Qualifiers::ObjCLifetime getObjCARCImplicitLifetime() const;
 
@@ -7160,6 +7162,17 @@
 false; // end of boolean or operation.
 }
 
+inline bool Type::isRVVType(unsigned Bitwidth, bool IsFloat) const {
+  bool Ret = false;
+#define RVV_TYPE(Name, Id, SingletonId)
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned,   \
+IsFP)  \
+  if (ElBits == Bitwidth && IsFloat == IsFP)   \
+Ret |= isSpecificBuiltinType(BuiltinType::Id);
+#include "clang/Basic/RISCVVTypes.def"
+  return Ret;
+}
+
 inline bool Type::isTemplateTypeParmType() const {
   return 

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 496311.
eopXD added a comment.

Update code based on comments from Craig.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143657/new/

https://reviews.llvm.org/D143657

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -368,14 +368,13 @@
   }
 }
   }
-  OS << "#if defined(__riscv_zvfh)\n";
+
   for (int Log2LMUL : Log2LMULs) {
 auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
PrototypeDescriptor::Vector);
 if (T)
   printType(*T);
   }
-  OS << "#endif\n";
 
   OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- /dev/null
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include 
+
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'experimental-zvfh' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -171,7 +171,6 @@
   const TargetInfo  = Context.getTargetInfo();
   bool HasVectorFloat32 = TI.hasFeature("zve32f");
   bool HasVectorFloat64 = TI.hasFeature("zve64d");
-  bool HasZvfh = TI.hasFeature("experimental-zvfh");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
@@ -223,9 +222,6 @@
 continue;
 
   // Check requirement.
-  if (BaseType == BasicType::Float16 && !HasZvfh)
-continue;
-
   if (BaseType == BasicType::Float32 && !HasVectorFloat32)
 continue;
 
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2046,6 +2046,12 @@
 targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
 }
 
+if (Ty->isRVVFloat16Type() &&
+!Context.getTargetInfo().hasFeature("experimental-zvfh")) {
+  Diag(Loc, diag::err_riscv_type_requires_extension, FD)
+  << Ty << "experimental-zvfh";
+}
+
 // Don't allow SVE types in functions without a SVE target.
 if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
   llvm::StringMap CallerFeatureMap;
Index: clang/include/clang/Basic/RISCVVTypes.def
===
--- clang/include/clang/Basic/RISCVVTypes.def
+++ clang/include/clang/Basic/RISCVVTypes.def
@@ -60,6 +60,10 @@
   RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
 #endif
 
+#ifndef RVV_VECTOR_TYPE_HALF_FLOAT
+#define RVV_VECTOR_TYPE_HALF_FLOAT RVV_VECTOR_TYPE_FLOAT
+#endif
+
 //===- Vector types ---===//
 
 RVV_VECTOR_TYPE_INT("__rvv_int8mf8_t", RvvInt8mf8, RvvInt8mf8Ty, 1,   8, 1, true)
@@ -114,12 +118,12 @@
 RVV_VECTOR_TYPE_INT("__rvv_uint64m4_t",RvvUint64m4,RvvUint64m4Ty,4,  64, 1, false)
 RVV_VECTOR_TYPE_INT("__rvv_uint64m8_t",RvvUint64m8,RvvUint64m8Ty,8,  64, 1, false)
 
-RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4_t",RvvFloat16mf4,RvvFloat16mf4Ty,1,  16, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2_t",RvvFloat16mf2,RvvFloat16mf2Ty,2,  16, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1_t", RvvFloat16m1, RvvFloat16m1Ty, 4,  16, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2, RvvFloat16m2Ty, 8,  16, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16, 16, 1)
-RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32, 16, 1)
+RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16mf4_t",RvvFloat16mf4,RvvFloat16mf4Ty,1,  16, 1)
+RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16mf2_t",RvvFloat16mf2,RvvFloat16mf2Ty,2,  16, 1)
+RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m1_t", RvvFloat16m1, RvvFloat16m1Ty, 4,  16, 1)
+RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m2_t", RvvFloat16m2, RvvFloat16m2Ty, 8,  16, 1)
+RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16, 16, 1)
+RVV_VECTOR_TYPE_HALF_FLOAT("__rvv_float16m8_t", RvvFloat16m8, 

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 496183.
eopXD added a comment.

Update code: check for `experimental-zvfh` instead of `zvfh`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143657/new/

https://reviews.llvm.org/D143657

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -368,14 +368,13 @@
   }
 }
   }
-  OS << "#if defined(__riscv_zvfh)\n";
+
   for (int Log2LMUL : Log2LMULs) {
 auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
PrototypeDescriptor::Vector);
 if (T)
   printType(*T);
   }
-  OS << "#endif\n";
 
   OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- /dev/null
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include 
+
+vfloat16m1_t foo() {  /* expected-error {{Vector type 'vfloat16m1_t' (aka '__rvv_float16m1_t') is not supported in the current target}} */ /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -171,7 +171,6 @@
   const TargetInfo  = Context.getTargetInfo();
   bool HasVectorFloat32 = TI.hasFeature("zve32f");
   bool HasVectorFloat64 = TI.hasFeature("zve64d");
-  bool HasZvfh = TI.hasFeature("experimental-zvfh");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
@@ -223,9 +222,6 @@
 continue;
 
   // Check requirement.
-  if (BaseType == BasicType::Float16 && !HasZvfh)
-continue;
-
   if (BaseType == BasicType::Float32 && !HasVectorFloat32)
 continue;
 
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2046,6 +2046,14 @@
 targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
 }
 
+if (Ty->isVectorFloat16Type() &&
+!Context.getTargetInfo().hasVectorFloat16Support()) {
+  Diag(Loc, diag::err_require_vector_support) << Ty;
+  if (Ty->isVectorFloat16Type() && Ty->isRVVFloat16Type()) {
+Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zvfh";
+  }
+}
+
 // Don't allow SVE types in functions without a SVE target.
 if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
   llvm::StringMap CallerFeatureMap;
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -100,6 +100,10 @@
 
   bool hasBitIntType() const override { return true; }
 
+  bool hasVectorFloat16Support() const override {
+return hasFeature("experimental-zvfh");
+  }
+
   bool useFP16ConversionIntrinsics() const override {
 return false;
   }
Index: clang/include/clang/Basic/TargetInfo.h
===
--- clang/include/clang/Basic/TargetInfo.h
+++ clang/include/clang/Basic/TargetInfo.h
@@ -664,6 +664,10 @@
   /// Determine whether constrained floating point is supported on this target.
   virtual bool hasStrictFP() const { return HasStrictFP; }
 
+  /// Determine whether vector half float (float16) type is supported on this
+  /// target.
+  virtual bool hasVectorFloat16Support() const { return false; }
+
   /// Return the alignment that is the largest alignment ever used for any
   /// scalar/SIMD data type on the target machine you are compiling for
   /// (including types with an extended alignment requirement).
Index: clang/include/clang/Basic/RISCVVTypes.def
===
--- clang/include/clang/Basic/RISCVVTypes.def
+++ clang/include/clang/Basic/RISCVVTypes.def
@@ -60,6 +60,10 @@
   RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
 #endif
 

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 496160.
eopXD added a comment.

Update code: rename error for vector support, remove dead code under 
SemaRISCVVectorLoopup.cpp


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143657/new/

https://reviews.llvm.org/D143657

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -368,14 +368,13 @@
   }
 }
   }
-  OS << "#if defined(__riscv_zvfh)\n";
+
   for (int Log2LMUL : Log2LMULs) {
 auto T = TypeCache.computeType(BasicType::Float16, Log2LMUL,
PrototypeDescriptor::Vector);
 if (T)
   printType(*T);
   }
-  OS << "#endif\n";
 
   OS << "#if (__riscv_v_elen_fp >= 32)\n";
   for (int Log2LMUL : Log2LMULs) {
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- /dev/null
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// REQUIRES: riscv-registered-target
+#include 
+
+vfloat16m1_t foo() {  /* expected-error {{Vector type 'vfloat16m1_t' (aka '__rvv_float16m1_t') is not supported in the current target}} */ /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+} /* expected-warning {{non-void function does not return a value}}*/
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -171,7 +171,6 @@
   const TargetInfo  = Context.getTargetInfo();
   bool HasVectorFloat32 = TI.hasFeature("zve32f");
   bool HasVectorFloat64 = TI.hasFeature("zve64d");
-  bool HasZvfh = TI.hasFeature("experimental-zvfh");
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
@@ -223,9 +222,6 @@
 continue;
 
   // Check requirement.
-  if (BaseType == BasicType::Float16 && !HasZvfh)
-continue;
-
   if (BaseType == BasicType::Float32 && !HasVectorFloat32)
 continue;
 
Index: clang/lib/Sema/Sema.cpp
===
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2046,6 +2046,14 @@
 targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
 }
 
+if (Ty->isVectorFloat16Type() &&
+!Context.getTargetInfo().hasVectorFloat16Support()) {
+  Diag(Loc, diag::err_require_vector_support) << Ty;
+  if (Ty->isVectorFloat16Type() && Ty->isRVVFloat16Type()) {
+Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zvfh";
+  }
+}
+
 // Don't allow SVE types in functions without a SVE target.
 if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
   llvm::StringMap CallerFeatureMap;
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -100,6 +100,8 @@
 
   bool hasBitIntType() const override { return true; }
 
+  bool hasVectorFloat16Support() const override { return hasFeature("zvfh"); }
+
   bool useFP16ConversionIntrinsics() const override {
 return false;
   }
Index: clang/include/clang/Basic/TargetInfo.h
===
--- clang/include/clang/Basic/TargetInfo.h
+++ clang/include/clang/Basic/TargetInfo.h
@@ -664,6 +664,10 @@
   /// Determine whether constrained floating point is supported on this target.
   virtual bool hasStrictFP() const { return HasStrictFP; }
 
+  /// Determine whether vector half float (float16) type is supported on this
+  /// target.
+  virtual bool hasVectorFloat16Support() const { return false; }
+
   /// Return the alignment that is the largest alignment ever used for any
   /// scalar/SIMD data type on the target machine you are compiling for
   /// (including types with an extended alignment requirement).
Index: clang/include/clang/Basic/RISCVVTypes.def
===
--- clang/include/clang/Basic/RISCVVTypes.def
+++ clang/include/clang/Basic/RISCVVTypes.def
@@ -60,6 +60,10 @@
   RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, 

[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

Forward declaration (snippet below) is still allowed after this commit.

  #include 
  
  vfloat16m1_t foo();

I see the same behavior under 
https://github.com/llvm/llvm-project/blob/main/clang/test/Sema/x86_64-no-x87.cpp.
  If I add type check under `SemaDecl.cpp::Sema::ActOnFunctionDeclarator`, the 
compiler will emit repeating warning for the same function. Currently I don't 
know what is the best fix for this.


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[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added a comment.

In D143657#4115721 , @craig.topper 
wrote:

> Are you going to do f32, f64, and i64 as well?

Yes, going to add them once this commit lands.


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[PATCH] D143657: [Clang][RISCV] Guard vector float16 type correctly with semantic analysis

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Are you going to do f32, f64, and i64 as well?


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