[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 542245.
yonghong-song added a comment.

- remove a copy-paste comment from s390 arch


Repository:
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Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/ldsx.ll
  llvm/test/CodeGen/BPF/movsx.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll

Index: llvm/test/CodeGen/BPF/sdiv_smod.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sdiv_smod.ll
@@ -0,0 +1,77 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  int foo(int a, int b, int c) {
+;return a/b + a%c;
+;  }
+;  long bar(long a, long b, long c) {
+;   return a/b + a%c;
+; }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i32 @foo(i32 noundef %a, i32 noundef %b, i32 noundef %c) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  store i32 %b, ptr %b.addr, align 4, !tbaa !3
+  store i32 %c, ptr %c.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %1 = load i32, ptr %b.addr, align 4, !tbaa !3
+  %div = sdiv i32 %0, %1
+  %2 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %3 = load i32, ptr %c.addr, align 4, !tbaa !3
+  %rem = srem i32 %2, %3
+  %add = add nsw i32 %div, %rem
+  ret i32 %add
+}
+
+; CHECK:   w0 = w1
+; CHECK-NEXT:  *(u32 *)(r10 - 8) = w2
+; CHECK-NEXT:  *(u32 *)(r10 - 4) = w0
+; CHECK-NEXT:  *(u32 *)(r10 - 12) = w3
+; CHECK-NEXT:  w1 s%= w3  # encoding: [0x9c,0x31,0x01,0x00,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:  w0 s/= w2  # encoding: [0x3c,0x20,0x01,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @bar(i64 noundef %a, i64 noundef %b, i64 noundef %c) #0 {
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8, !tbaa !7
+  store i64 %b, ptr %b.addr, align 8, !tbaa !7
+  store i64 %c, ptr %c.addr, align 8, !tbaa !7
+  %0 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %1 = load i64, ptr %b.addr, align 8, !tbaa !7
+  %div = sdiv i64 %0, %1
+  %2 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %3 = load i64, ptr %c.addr, align 8, !tbaa !7
+  %rem = srem i64 %2, %3
+  %add = add nsw i64 %div, %rem
+  ret i64 %add
+}
+
+; CHECK:   r0 = r1
+; CHECK-NEXT:  *(u64 *)(r10 - 16) = r2
+; CHECK-NEXT:  *(u64 *)(r10 - 8) = r0
+; CHECK-NEXT:  *(u64 *)(r10 - 24) = r3
+; CHECK-NEXT:  r1 s%= r3  # encoding: [0x9f,0x31,0x01,0x00,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:  r0 s/= r2  # encoding: [0x3f,0x20,0x01,0x00,0x00,0x00,0x00,0x00]
+
+attributes #0 = { nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 569bd3b841e3167ddd7c6ceeddb282d3c280e761)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"long", !5, i64 0}
Index: llvm/test/CodeGen/BPF/movsx.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/movsx.ll
@@ -0,0 +1,79 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;   short f1(char a) {
+; return a;
+;   }
+;   int f2(char a) {
+; return a;
+;   }
+;   long f3(char a) {
+; return a;
+;   }
+;   int f4(short a) {
+; return a;
+;   }
+;   long f5(short a) {
+; return a;
+;   }
+;   long f6(int a) {
+; return a;
+;   }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm t.c
+
+; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
+define

[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Alexei Starovoitov via Phabricator via cfe-commits]

ast accepted this revision.
ast added a comment.
This revision is now accepted and ready to land.

overall looks good. one small nit.




Comment at: llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h:17
+enum FixupKind {
+  // These correspond directly to R_390_* relocations.
+  FK_BPF_PCRel_4 = FirstTargetFixupKind,

a little bit too much of copy paste :)


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[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 541265.
yonghong-song edited the summary of this revision.
yonghong-song added a comment.

- Dropping 'CPUv4' in some variable/function names and also in debug flags.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144829/new/

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Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/ldsx.ll
  llvm/test/CodeGen/BPF/movsx.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll

Index: llvm/test/CodeGen/BPF/sdiv_smod.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sdiv_smod.ll
@@ -0,0 +1,77 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  int foo(int a, int b, int c) {
+;return a/b + a%c;
+;  }
+;  long bar(long a, long b, long c) {
+;   return a/b + a%c;
+; }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i32 @foo(i32 noundef %a, i32 noundef %b, i32 noundef %c) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  store i32 %b, ptr %b.addr, align 4, !tbaa !3
+  store i32 %c, ptr %c.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %1 = load i32, ptr %b.addr, align 4, !tbaa !3
+  %div = sdiv i32 %0, %1
+  %2 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %3 = load i32, ptr %c.addr, align 4, !tbaa !3
+  %rem = srem i32 %2, %3
+  %add = add nsw i32 %div, %rem
+  ret i32 %add
+}
+
+; CHECK:   w0 = w1
+; CHECK-NEXT:  *(u32 *)(r10 - 8) = w2
+; CHECK-NEXT:  *(u32 *)(r10 - 4) = w0
+; CHECK-NEXT:  *(u32 *)(r10 - 12) = w3
+; CHECK-NEXT:  w1 s%= w3  # encoding: [0x9c,0x31,0x01,0x00,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:  w0 s/= w2  # encoding: [0x3c,0x20,0x01,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @bar(i64 noundef %a, i64 noundef %b, i64 noundef %c) #0 {
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8, !tbaa !7
+  store i64 %b, ptr %b.addr, align 8, !tbaa !7
+  store i64 %c, ptr %c.addr, align 8, !tbaa !7
+  %0 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %1 = load i64, ptr %b.addr, align 8, !tbaa !7
+  %div = sdiv i64 %0, %1
+  %2 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %3 = load i64, ptr %c.addr, align 8, !tbaa !7
+  %rem = srem i64 %2, %3
+  %add = add nsw i64 %div, %rem
+  ret i64 %add
+}
+
+; CHECK:   r0 = r1
+; CHECK-NEXT:  *(u64 *)(r10 - 16) = r2
+; CHECK-NEXT:  *(u64 *)(r10 - 8) = r0
+; CHECK-NEXT:  *(u64 *)(r10 - 24) = r3
+; CHECK-NEXT:  r1 s%= r3  # encoding: [0x9f,0x31,0x01,0x00,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:  r0 s/= r2  # encoding: [0x3f,0x20,0x01,0x00,0x00,0x00,0x00,0x00]
+
+attributes #0 = { nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 569bd3b841e3167ddd7c6ceeddb282d3c280e761)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"long", !5, i64 0}
Index: llvm/test/CodeGen/BPF/movsx.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/movsx.ll
@@ -0,0 +1,79 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;   short f1(char a) {
+; return a;
+;   }
+;   int f2(char a) {
+; return a;
+;   }
+;   long f3(char a) {
+; return a;
+;   }
+;   int f4(short a) {
+; return a;
+;   }
+;   long f5(short a) {
+; return a;
+;   }
+;   long f6(int a) {
+; return a;
+;   }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm t.c
+
+; Function At

[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song added inline comments.



Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:56
 def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
+def BPFHasCPUv4_ldsx : Predicate<"Subtarget->getCPUv4_ldsx()">;
+def BPFHasCPUv4_movsx : Predicate<"Subtarget->getCPUv4_movsx()">;

ast wrote:
> Here and elsewhere... let's drop CPUv4 mid prefix. imo the extra verbosity 
> doesn't improve readability.
> Same with the flag: disable-cpuv4-movsx. I can be disable-movsx.
> 
> s/BPFHasCPUv4_ldsx/BPFHasLdsx/
> s/getCPUv4_bswap/getHasBswap/ or even shorter hasBswap ?
Make sense. Will do. Ya, hasBswap is good enough to capture what it means.


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[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Alexei Starovoitov via Phabricator via cfe-commits]

ast added inline comments.



Comment at: llvm/lib/Target/BPF/BPFInstrInfo.td:56
 def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
+def BPFHasCPUv4_ldsx : Predicate<"Subtarget->getCPUv4_ldsx()">;
+def BPFHasCPUv4_movsx : Predicate<"Subtarget->getCPUv4_movsx()">;

Here and elsewhere... let's drop CPUv4 mid prefix. imo the extra verbosity 
doesn't improve readability.
Same with the flag: disable-cpuv4-movsx. I can be disable-movsx.

s/BPFHasCPUv4_ldsx/BPFHasLdsx/
s/getCPUv4_bswap/getHasBswap/ or even shorter hasBswap ?


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[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 539842.
yonghong-song edited the summary of this revision.
yonghong-song added a comment.

- rename some insn names or mode names (movs -> movsx, lds -> ldsx, MEMS -> 
MEMSX) etc to be consistent with kernel.
- add 5 llc flags to control on/off for each kind of insn (sdiv/smod, ldsx, 
movsx, bswap, gotol) to debugging purpose.


Repository:
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Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/ldsx.ll
  llvm/test/CodeGen/BPF/movsx.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll

Index: llvm/test/CodeGen/BPF/sdiv_smod.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sdiv_smod.ll
@@ -0,0 +1,77 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  int foo(int a, int b, int c) {
+;return a/b + a%c;
+;  }
+;  long bar(long a, long b, long c) {
+;   return a/b + a%c;
+; }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i32 @foo(i32 noundef %a, i32 noundef %b, i32 noundef %c) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  store i32 %b, ptr %b.addr, align 4, !tbaa !3
+  store i32 %c, ptr %c.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %1 = load i32, ptr %b.addr, align 4, !tbaa !3
+  %div = sdiv i32 %0, %1
+  %2 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %3 = load i32, ptr %c.addr, align 4, !tbaa !3
+  %rem = srem i32 %2, %3
+  %add = add nsw i32 %div, %rem
+  ret i32 %add
+}
+
+; CHECK:   w0 = w1
+; CHECK-NEXT:  *(u32 *)(r10 - 8) = w2
+; CHECK-NEXT:  *(u32 *)(r10 - 4) = w0
+; CHECK-NEXT:  *(u32 *)(r10 - 12) = w3
+; CHECK-NEXT:  w1 s%= w3  # encoding: [0x9c,0x31,0x01,0x00,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:  w0 s/= w2  # encoding: [0x3c,0x20,0x01,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @bar(i64 noundef %a, i64 noundef %b, i64 noundef %c) #0 {
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8, !tbaa !7
+  store i64 %b, ptr %b.addr, align 8, !tbaa !7
+  store i64 %c, ptr %c.addr, align 8, !tbaa !7
+  %0 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %1 = load i64, ptr %b.addr, align 8, !tbaa !7
+  %div = sdiv i64 %0, %1
+  %2 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %3 = load i64, ptr %c.addr, align 8, !tbaa !7
+  %rem = srem i64 %2, %3
+  %add = add nsw i64 %div, %rem
+  ret i64 %add
+}
+
+; CHECK:   r0 = r1
+; CHECK-NEXT:  *(u64 *)(r10 - 16) = r2
+; CHECK-NEXT:  *(u64 *)(r10 - 8) = r0
+; CHECK-NEXT:  *(u64 *)(r10 - 24) = r3
+; CHECK-NEXT:  r1 s%= r3  # encoding: [0x9f,0x31,0x01,0x00,0x00,0x00,0x00,0x00]
+; CHECK-NEXT:  r0 s/= r2  # encoding: [0x3f,0x20,0x01,0x00,0x00,0x00,0x00,0x00]
+
+attributes #0 = { nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 569bd3b841e3167ddd7c6ceeddb282d3c280e761)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"long", !5, i64 0}
Index: llvm/test/CodeGen/BPF/movsx.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/movsx.ll
@@ -0,0 +1,79 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;   short f1(char a) {
+; return a;
+;   }
+;   int f2(char a) {
+; return a;
+;   }
+;   long f3(char a) {
+; return a;
+;   }
+;   int f4(short a) {
+; return a;
+;   }
+;   long f5(sh

[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song added a comment.

In D144829#4465193 , @eddyz87 wrote:

> Hi Yonghong,
>
> What is the current plan for these changes?
> I'd like to refresh D140804  to make BPF_ST 
> instruction available for cpu v4.
> I see that the latest CI run failed because of libcxx issue, I think it is 
> completely unrelated to this revision, see here 
> .

Eduard, please go ahead to refresh BPF_ST patch (D140804 
). For this patch, we will land it until the 
kernel patch addressed all major comments. When it is ready to merge, you will 
comment and let you know.


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[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Eduard Zingerman via Phabricator via cfe-commits]

eddyz87 added a comment.

Hi Yonghong,

What is the current plan for these changes?
I'd like to refresh D140804  to make BPF_ST 
instruction available for cpu v4.
I see that the latest CI run failed because of libcxx issue, I think it is 
completely unrelated to this revision, see here 
.


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[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 534801.
yonghong-song added a comment.

- avoid changing conditions during JMP -> JMPL conversion. Otherwise, 
verification may fail in some cases.


Repository:
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Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll
  llvm/test/CodeGen/BPF/sext_ld.ll
  llvm/test/CodeGen/BPF/sext_mov.ll

Index: llvm/test/CodeGen/BPF/sext_mov.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_mov.ll
@@ -0,0 +1,109 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  short f1(int a) {
+;return (char)a;
+;  }
+;  int f2(int a) {
+;return (char)a;
+;  }
+;  long f3(int a) {
+;return (char)a;
+;  }
+;  int f4(int a) {
+;return (short)a;
+;  }
+;  long f5(int a) {
+;return (short)a;
+;  }
+;  long f6(long a) {
+;return (int)a;
+;  }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i16 @f1(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i16
+  ret i16 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f2(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f3(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s8)r1  # encoding: [0xbf,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f4(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s16)w1  # encoding: [0xbc,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f5(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s16)r1  # encoding: [0xbf,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f6(i64 noundef %a) #0 {
+entry:
+  %a.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8, !tbaa !7
+  %0 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %conv = trunc i64 %0 to i32
+  %conv1 = sext i32 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s32)r1  # encoding: [0xbf,0x10,0x20,0x00,0x00,0x00,0x00,0x00]
+
+attributes #0 = { nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 569bd3b841e3167ddd7c6ceeddb282d3c280e761)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"long", !5, i64 0}
Index: llvm/test/CodeGen/BPF/sext_ld.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_ld.ll
@@ -0,0 +1,104 @@
+; RUN: llc -march=bpfel -

[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 534361.
yonghong-song added a comment.

- added support of new instructions in inline assembly.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144829/new/

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Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll
  llvm/test/CodeGen/BPF/sext_ld.ll
  llvm/test/CodeGen/BPF/sext_mov.ll

Index: llvm/test/CodeGen/BPF/sext_mov.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_mov.ll
@@ -0,0 +1,109 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  short f1(int a) {
+;return (char)a;
+;  }
+;  int f2(int a) {
+;return (char)a;
+;  }
+;  long f3(int a) {
+;return (char)a;
+;  }
+;  int f4(int a) {
+;return (short)a;
+;  }
+;  long f5(int a) {
+;return (short)a;
+;  }
+;  long f6(long a) {
+;return (int)a;
+;  }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i16 @f1(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i16
+  ret i16 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f2(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f3(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s8)r1  # encoding: [0xbf,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f4(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s16)w1  # encoding: [0xbc,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f5(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s16)r1  # encoding: [0xbf,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f6(i64 noundef %a) #0 {
+entry:
+  %a.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8, !tbaa !7
+  %0 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %conv = trunc i64 %0 to i32
+  %conv1 = sext i32 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s32)r1  # encoding: [0xbf,0x10,0x20,0x00,0x00,0x00,0x00,0x00]
+
+attributes #0 = { nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 569bd3b841e3167ddd7c6ceeddb282d3c280e761)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"long", !5, i64 0}
Index: llvm/test/CodeGen/BPF/sext_ld.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_ld.ll
@@ -0,0 +1,104 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s

[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 523569.
yonghong-song edited the summary of this revision.
yonghong-song added a comment.

- Fixed previous llvm-objdump issue for '> 16bit' 'gotol' insns.
- Now basic functionality for cpu=v4 should be complete for llvm, further work 
will focus on kernel.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144829/new/

https://reviews.llvm.org/D144829

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll
  llvm/test/CodeGen/BPF/sext_ld.ll
  llvm/test/CodeGen/BPF/sext_mov.ll

Index: llvm/test/CodeGen/BPF/sext_mov.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_mov.ll
@@ -0,0 +1,109 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  short f1(int a) {
+;return (char)a;
+;  }
+;  int f2(int a) {
+;return (char)a;
+;  }
+;  long f3(int a) {
+;return (char)a;
+;  }
+;  int f4(int a) {
+;return (short)a;
+;  }
+;  long f5(int a) {
+;return (short)a;
+;  }
+;  long f6(long a) {
+;return (int)a;
+;  }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i16 @f1(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i16
+  ret i16 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f2(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f3(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s8)r1  # encoding: [0xbf,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f4(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s16)w1  # encoding: [0xbc,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f5(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s16)r1  # encoding: [0xbf,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f6(i64 noundef %a) #0 {
+entry:
+  %a.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8, !tbaa !7
+  %0 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %conv = trunc i64 %0 to i32
+  %conv1 = sext i32 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s32)r1  # encoding: [0xbf,0x10,0x20,0x00,0x00,0x00,0x00,0x00]
+
+attributes #0 = { nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 569bd3b841e3167ddd7c6ceeddb282d3c280e761)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"long", !5, i64 0}
Index: llvm/test/CodeGen/BPF/sext_ld.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_ld.ll
@@ -0,0 +1,104 @@
+; RUN: llc -m

[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song updated this revision to Diff 523253.
yonghong-song added a comment.

- Fixed issues reported by Eduard
- llvm-objdump issue (as stated in 'Summary') is not resolved yet.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144829/new/

https://reviews.llvm.org/D144829

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.cpp
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll
  llvm/test/CodeGen/BPF/sext_ld.ll
  llvm/test/CodeGen/BPF/sext_mov.ll

Index: llvm/test/CodeGen/BPF/sext_mov.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_mov.ll
@@ -0,0 +1,109 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  short f1(int a) {
+;return (char)a;
+;  }
+;  int f2(int a) {
+;return (char)a;
+;  }
+;  long f3(int a) {
+;return (char)a;
+;  }
+;  int f4(int a) {
+;return (short)a;
+;  }
+;  long f5(int a) {
+;return (short)a;
+;  }
+;  long f6(long a) {
+;return (int)a;
+;  }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i16 @f1(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i16
+  ret i16 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f2(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f3(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s8)r1  # encoding: [0xbf,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f4(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s16)w1  # encoding: [0xbc,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f5(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s16)r1  # encoding: [0xbf,0x10,0x10,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f6(i64 noundef %a) #0 {
+entry:
+  %a.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8, !tbaa !7
+  %0 = load i64, ptr %a.addr, align 8, !tbaa !7
+  %conv = trunc i64 %0 to i32
+  %conv1 = sext i32 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s32)r1  # encoding: [0xbf,0x10,0x20,0x00,0x00,0x00,0x00,0x00]
+
+attributes #0 = { nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+
+!llvm.module.flags = !{!0, !1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"frame-pointer", i32 2}
+!2 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git 569bd3b841e3167ddd7c6ceeddb282d3c280e761)"}
+!3 = !{!4, !4, i64 0}
+!4 = !{!"int", !5, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
+!7 = !{!8, !8, i64 0}
+!8 = !{!"long", !5, i64 0}
Index: llvm/test/CodeGen/BPF/sext_ld.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_ld.ll
@@ -0,0 +1,104 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  int f1(char *p) {
+;return *p;
+; 

[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Eduard Zingerman via Phabricator via cfe-commits]

eddyz87 added a comment.

Hi Yonghong,

Left a few nitpicks and one comment in `BPFMIPreEmitPeephole::adjustBranch()` 
that I think points to a bug.
Overall `adjustBranch()` algorithm looks good. It would be great to have some 
test cases for it, e.g. preprocess test .ll by replacing some template with a 
bunch of noops or something like this.
The instruction encoding seem to match mailing list description.
Also one `check-all` test is failing for me:

  home/eddy/work/llvm-project/clang/test/Misc/target-invalid-cpu-note.c:76:14: 
error: BPF-NEXT: expected string not found in input
  // BPF-NEXT: note: valid target CPU values are: generic, v1, v2, v3, 
probe{{$}}




Comment at: llvm/lib/Target/BPF/BPFInstrFormats.td:93
 def BPF_MEM  : BPFModeModifer<0x3>;
+def BPF_MEMS : BPFModeModifer<0x4>;
 def BPF_ATOMIC : BPFModeModifer<0x6>;

Nitpick: the mailing list doc refers to this as `BPF_SMEM`.



Comment at: llvm/lib/Target/BPF/BPFMIPeephole.cpp:331
+if (IsCPUv4)
+  Changed = adjustBranch() || Changed;
+return Changed;

Nitpick: this would not be executed for `-O0`, but is required for correct 
execution.

```
void BPFPassConfig::addPreEmitPass() {
  addPass(createBPFMIPreEmitCheckingPass());
  if (getOptLevel() != CodeGenOpt::None)
if (!DisableMIPeephole)
  addPass(createBPFMIPreEmitPeepholePass());
}
```



Comment at: llvm/lib/Target/BPF/BPFMIPeephole.cpp:452
+  JmpBB = UncondJmp->getOperand(0).getMBB();
+  Dist = SoFarNumInsns[JmpBB] - CurrNumInsns;
+  if (Dist <= INT16_MAX && Dist >= INT16_MIN)

As far as I understand:
- `SoFarNumInsns[JmpBB]` is a number of instructions from function start till 
the end of `JmpBB`;
- `CurrNumInsns` is a number of instructions from function start till the end 
of `MBB`.

So, `SoFarNumInsns[JmpBB] - CurrNumInsns` gives the distance between basic 
block ends. However, the jump would happen to the basic block start, so the 
actual distance should be computed as `SoFarNumInsns[JmpBB] - JmpBB.size() - 
CurrNumInsns`.

Am I confused?



Comment at: llvm/lib/Target/BPF/BPFMIPeephole.cpp:479
+  //
+  // We do not have 32bit cond jmp insn. So we try to do
+  // the following.

Is it possible to rewrite as below instead?

```
B2: ...
if (!cond) goto B3
gotol B5
B3: ...
```

Seems to be equivalent but with less instructions.



Comment at: llvm/lib/Target/BPF/BPFMIPeephole.cpp:549
+Dist = SoFarNumInsns[CondTargetBB] - CurrNumInsns;
+if (Dist > INT16_MAX || Dist < INT16_MIN) {
+  MachineBasicBlock *New_B = MF->CreateMachineBasicBlock(TermBB);

Nitpick: `(Dist <= INT16_MAX && Dist >= INT16_MIN)` is used in the previous two 
cases.



Comment at: llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp:108
+  } else if (Fixup.getTargetKind() == BPF::FK_BPF_PCRel_4) {
+Value = (uint32_t)((Value - 8) / 8);
+support::endian::write(&Data[Fixup.getOffset() + 4], Value,

This is because `Value` is in bytes, right?
Could you please drop a comment here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144829/new/

https://reviews.llvm.org/D144829

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[PATCH] D144829: [WIP][BPF] Add a few new insns under cpu=v4

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song created this revision.
Herald added a subscriber: hiraditya.
Herald added a project: All.
yonghong-song requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

In [1], a few new insns are proposed to exgend BPF ISA to

  . fixing the limitation of existing insn (e.g., 16bit jmp offset)
  . adding new insns which may improve code quality (sext_ld, sext_mov, st) 
  . feature complete (sdiv, smod)
  . better user experience (bswap)

This patch implemented insn encoding for

  . sign-extended load
  . sign-extended mov 
  . sdiv/smod
  . bswap insns
  . unconditional jump with 32bit offset

The encoding for sign-extended load/mov, sdiv/smod are followed by
proposal in [1] except a couple of changes like sign-extended load
does not really have alu32 mode, and sign-extend mov only supports
`dst_reg<-(sign extend)src_reg` format. I will update the proposal
in bpf mailing list later.

The new bswap insns are generated under cpu=v4 for __builtin_bswap.
For cpu=v3 or earlier, for __builtin_bswap, be or le insns are generated
which is not intuitive for the user.

To support 32-bit branch offset, a 32-bit ja (JMPL) insn is implemented.
For conditional branch which is beyond 16-bit offset, llvm will do
some transformation 'cond_jmp' -> 'cond_jmp + jmpl' to simulate 32bit
conditional jmp. See BPFMIPeephole.cpp for details. The algorithm is
hueristic based. I have tested bpf selftest pyperf600 with unroll account
600 which can indeed generate 32-bit jump insn, e.g.,

  14:   06 00 00 00 27 ef 00 00 gotol +0xef27 


In the above, need to investigate why llvm-objdump prints out 
'', probably due to my introduction
of BPF specific fixup kinds.

Eduard is working on to add 'st' insn to cpu=v4.

This patch is in WIP stage since I need to:

  (1). investigate the above '' print,
  (2). add verifier support for the above insns.

References:

  [1] https://lore.kernel.org/bpf/01515302-c37d-2ee5-c950-2f556a4ca...@meta.com/


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144829

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  llvm/lib/Target/BPF/BPF.td
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFInstrFormats.td
  llvm/lib/Target/BPF/BPFInstrInfo.td
  llvm/lib/Target/BPF/BPFMIPeephole.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCFixups.h
  llvm/test/CodeGen/BPF/bswap.ll
  llvm/test/CodeGen/BPF/sdiv_smod.ll
  llvm/test/CodeGen/BPF/sext_ld.ll
  llvm/test/CodeGen/BPF/sext_mov.ll

Index: llvm/test/CodeGen/BPF/sext_mov.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/sext_mov.ll
@@ -0,0 +1,109 @@
+; RUN: llc -march=bpfel -mcpu=v4 -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
+; Source:
+;  short f1(int a) {
+;return (char)a;
+;  }
+;  int f2(int a) {
+;return (char)a;
+;  }
+;  long f3(int a) {
+;return (char)a;
+;  }
+;  int f4(int a) {
+;return (short)a;
+;  }
+;  long f5(int a) {
+;return (short)a;
+;  }
+;  long f6(long a) {
+;return (int)a;
+;  }
+; Compilation flags:
+;   clang -target bpf -O2 -S -emit-llvm -Xclang -disable-llvm-passes t.c
+
+; Function Attrs: nounwind
+define dso_local i16 @f1(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i16
+  ret i16 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f2(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: w0 = (s8)w1  # encoding: [0xbc,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i64 @f3(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i8
+  %conv1 = sext i8 %conv to i64
+  ret i64 %conv1
+}
+; CHECK: r0 = (s8)r1  # encoding: [0xbf,0x10,0x08,0x00,0x00,0x00,0x00,0x00]
+
+; Function Attrs: nounwind
+define dso_local i32 @f4(i32 noundef %a) #0 {
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4, !tbaa !3
+  %0 = load i32, ptr %a.addr, align 4, !tbaa !3
+  %conv = trunc i32 %0 to i16
+  %conv1 = sext i16 %conv to i32
+  ret i32 %conv1
+}
+; CHECK: