subject:"\[PATCH\] D147327\: \[clang\-format\] Add option for having one port per line in Verilog"

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

2023-04-04 Thread sstwcw via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG74cc4389f37d: [clang-format] Add option for having one port 
per line in Verilog (authored by sstwcw).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147327/new/

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Files:
  clang/docs/ClangFormatStyleOptions.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/ConfigParseTest.cpp
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

Index: clang/unittests/Format/TokenAnnotatorTest.cpp
===
--- clang/unittests/Format/TokenAnnotatorTest.cpp
+++ clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -1645,6 +1645,18 @@
   EXPECT_TOKEN_PRECEDENCE(Tokens[1], prec::Assignment);
   EXPECT_TOKEN(Tokens[3], tok::lessequal, TT_BinaryOperator);
   EXPECT_TOKEN_PRECEDENCE(Tokens[3], prec::Relational);
+
+  // Port lists in module instantiation.
+  Tokens = Annotate("module_x instance_1(port_1), instance_2(port_2);");
+  ASSERT_EQ(Tokens.size(), 12u);
+  EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[7], tok::l_paren, TT_VerilogInstancePortLParen);
+  Tokens = Annotate("module_x #(parameter) instance_1(port_1), "
+"instance_2(port_2);");
+  ASSERT_EQ(Tokens.size(), 16u);
+  EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[6], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[11], tok::l_paren, TT_VerilogInstancePortLParen);
 }
 
 TEST_F(TokenAnnotatorTest, UnderstandConstructors) {
Index: clang/unittests/Format/FormatTestVerilog.cpp
===
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -673,6 +673,77 @@
"  x = x;");
 }
 
+TEST_F(FormatTestVerilog, Instantiation) {
+  // Without ports.
+  verifyFormat("ffnand ff1;");
+  // With named ports.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With wildcard.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2),\n"
+   "   .*);");
+  verifyFormat("ffnand ff1(.*,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With unconnected ports.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(),\n"
+   "   .clear(),\n"
+   "   .preset());");
+  verifyFormat("ffnand ff1(,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With positional ports.
+  verifyFormat("ffnand ff1(out1,\n"
+   "   in1,\n"
+   "   in2);");
+  verifyFormat("ffnand ff1(,\n"
+   "   out1,\n"
+   "   in1,\n"
+   "   in2);");
+  // Multiple instantiations.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2)),\n"
+   "   ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand //\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2)),\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2));");
+  // With breaking between instance ports disabled.
+  auto Style = getDefaultStyle();
+  Style.VerilogBreakBetweenInstancePorts = false;
+  verifyFormat("ffnand ff1;", Style);
+  verifyFormat("ffnand ff1(.qbar(out1), .clear(in1), .preset(in2), .*);",
+   Style);
+  verifyFormat("ffnand ff1(out1, in1, in2);", Style);
+  verifyFormat("ffnand ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "   ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+  verifyFormat("ffnand //\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+}
+

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

2023-04-02 Thread sstwcw via Phabricator via cfe-commits

sstwcw updated this revision to Diff 510385.
sstwcw added a comment.

- Use lambda


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/docs/ClangFormatStyleOptions.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/ConfigParseTest.cpp
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

Index: clang/unittests/Format/TokenAnnotatorTest.cpp
===
--- clang/unittests/Format/TokenAnnotatorTest.cpp
+++ clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -1579,6 +1579,18 @@
   EXPECT_TOKEN_PRECEDENCE(Tokens[1], prec::Assignment);
   EXPECT_TOKEN(Tokens[3], tok::lessequal, TT_BinaryOperator);
   EXPECT_TOKEN_PRECEDENCE(Tokens[3], prec::Relational);
+
+  // Port lists in module instantiation.
+  Tokens = Annotate("module_x instance_1(port_1), instance_2(port_2);");
+  ASSERT_EQ(Tokens.size(), 12u);
+  EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[7], tok::l_paren, TT_VerilogInstancePortLParen);
+  Tokens = Annotate("module_x #(parameter) instance_1(port_1), "
+"instance_2(port_2);");
+  ASSERT_EQ(Tokens.size(), 16u);
+  EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[6], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[11], tok::l_paren, TT_VerilogInstancePortLParen);
 }
 
 TEST_F(TokenAnnotatorTest, UnderstandConstructors) {
Index: clang/unittests/Format/FormatTestVerilog.cpp
===
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -673,6 +673,77 @@
"  x = x;");
 }
 
+TEST_F(FormatTestVerilog, Instantiation) {
+  // Without ports.
+  verifyFormat("ffnand ff1;");
+  // With named ports.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With wildcard.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2),\n"
+   "   .*);");
+  verifyFormat("ffnand ff1(.*,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With unconnected ports.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(),\n"
+   "   .clear(),\n"
+   "   .preset());");
+  verifyFormat("ffnand ff1(,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With positional ports.
+  verifyFormat("ffnand ff1(out1,\n"
+   "   in1,\n"
+   "   in2);");
+  verifyFormat("ffnand ff1(,\n"
+   "   out1,\n"
+   "   in1,\n"
+   "   in2);");
+  // Multiple instantiations.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2)),\n"
+   "   ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand //\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2)),\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2));");
+  // With breaking between instance ports disabled.
+  auto Style = getDefaultStyle();
+  Style.VerilogBreakBetweenInstancePorts = false;
+  verifyFormat("ffnand ff1;", Style);
+  verifyFormat("ffnand ff1(.qbar(out1), .clear(in1), .preset(in2), .*);",
+   Style);
+  verifyFormat("ffnand ff1(out1, in1, in2);", Style);
+  verifyFormat("ffnand ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "   ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+  verifyFormat("ffnand //\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+}
+
 TEST_F(FormatTestVerilog, Operators) {
   // Test that unary operators are not followed by space.
   verifyFormat("x = +x;");
Index:

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

2023-04-01 Thread Owen Pan via Phabricator via cfe-commits

owenpan added inline comments.



Comment at: clang/lib/Format/TokenAnnotator.cpp:1149-1191
+  if (Style.isVerilog()) {
+const FormatToken *Prev = Tok->getPreviousNonComment();
+const FormatToken *PrevPrev;
+// Identify the parameter list and port list in a module instantiation.
+// This is still needed when we already have
+// UnwrappedLineParser::parseVerilogHierarchyHeader because that
+// function is only responsible for the definition, not the

Can you make it a function or lambda with early returns?


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[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

2023-04-01 Thread sstwcw via Phabricator via cfe-commits

sstwcw updated this revision to Diff 510244.
sstwcw marked 2 inline comments as done.
sstwcw added a comment.

- Use shorter conditions


Repository:
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Files:
  clang/docs/ClangFormatStyleOptions.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/ConfigParseTest.cpp
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

Index: clang/unittests/Format/TokenAnnotatorTest.cpp
===
--- clang/unittests/Format/TokenAnnotatorTest.cpp
+++ clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -1579,6 +1579,18 @@
   EXPECT_TOKEN_PRECEDENCE(Tokens[1], prec::Assignment);
   EXPECT_TOKEN(Tokens[3], tok::lessequal, TT_BinaryOperator);
   EXPECT_TOKEN_PRECEDENCE(Tokens[3], prec::Relational);
+
+  // Port lists in module instantiation.
+  Tokens = Annotate("module_x instance_1(port_1), instance_2(port_2);");
+  ASSERT_EQ(Tokens.size(), 12u);
+  EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[7], tok::l_paren, TT_VerilogInstancePortLParen);
+  Tokens = Annotate("module_x #(parameter) instance_1(port_1), "
+"instance_2(port_2);");
+  ASSERT_EQ(Tokens.size(), 16u);
+  EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[6], tok::l_paren, TT_VerilogInstancePortLParen);
+  EXPECT_TOKEN(Tokens[11], tok::l_paren, TT_VerilogInstancePortLParen);
 }
 
 TEST_F(TokenAnnotatorTest, UnderstandConstructors) {
Index: clang/unittests/Format/FormatTestVerilog.cpp
===
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -659,6 +659,77 @@
"  x = x;");
 }
 
+TEST_F(FormatTestVerilog, Instantiation) {
+  // Without ports.
+  verifyFormat("ffnand ff1;");
+  // With named ports.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With wildcard.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2),\n"
+   "   .*);");
+  verifyFormat("ffnand ff1(.*,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With unconnected ports.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(),\n"
+   "   .clear(),\n"
+   "   .preset());");
+  verifyFormat("ffnand ff1(,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With positional ports.
+  verifyFormat("ffnand ff1(out1,\n"
+   "   in1,\n"
+   "   in2);");
+  verifyFormat("ffnand ff1(,\n"
+   "   out1,\n"
+   "   in1,\n"
+   "   in2);");
+  // Multiple instantiations.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2)),\n"
+   "   ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand //\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2)),\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2));");
+  // With breaking between instance ports disabled.
+  auto Style = getDefaultStyle();
+  Style.VerilogBreakBetweenInstancePorts = false;
+  verifyFormat("ffnand ff1;", Style);
+  verifyFormat("ffnand ff1(.qbar(out1), .clear(in1), .preset(in2), .*);",
+   Style);
+  verifyFormat("ffnand ff1(out1, in1, in2);", Style);
+  verifyFormat("ffnand ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "   ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+  verifyFormat("ffnand //\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+}
+
 TEST_F(FormatTestVerilog, Operators) {
   // Test that unary operators are not followed by space.

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

2023-03-31 Thread Björn Schäpers via Phabricator via cfe-commits

HazardyKnusperkeks requested changes to this revision.
HazardyKnusperkeks added inline comments.
This revision now requires changes to proceed.



Comment at: clang/include/clang/Format/Format.h:4185
+  /// For Verilog, put each port on its own line in module instantiations.
+  /// \code
+  ///ffnand ff1(.q(),

Can you put the true vs. false in the doc, like on other options?



Comment at: clang/include/clang/Format/Format.h:4192
+  /// \version 17
+  bool VerilogBreakBetweenInstancePorts;
+

V after U



Comment at: clang/lib/Format/TokenAnnotator.cpp:1150
+  if (Style.isVerilog()) {
+const FormatToken *Prev = Tok->getPreviousNonComment(), *Prev2;
+// Identify the parameter list and port list in a module instantiation.





Comment at: clang/lib/Format/TokenAnnotator.cpp:1156-1163
+if (Prev && (Prev2 = Prev->getPreviousNonComment()) &&
+((Prev->is(tok::hash) && Keywords.isVerilogIdentifier(*Prev2)) ||
+ (Keywords.isVerilogIdentifier(*Prev) &&
+  (Prev2->is(tok::r_paren) ||
+   Keywords.isVerilogIdentifier(*Prev2) ||
+   (Prev2->endsSequence(tok::comma, tok::r_paren) &&
+(Prev2 = Prev2->getPreviousNonComment()->MatchingParen) &&

I won't read that.

I think you should go with multiple if statements.


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[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

2023-03-31 Thread sstwcw via Phabricator via cfe-commits

sstwcw updated this revision to Diff 510038.
sstwcw added a comment.

Generate doc


Repository:
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Files:
  clang/docs/ClangFormatStyleOptions.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/ConfigParseTest.cpp
  clang/unittests/Format/FormatTestVerilog.cpp

Index: clang/unittests/Format/FormatTestVerilog.cpp
===
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -659,6 +659,77 @@
"  x = x;");
 }
 
+TEST_F(FormatTestVerilog, Instantiation) {
+  // Without ports.
+  verifyFormat("ffnand ff1;");
+  // With named ports.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With wildcard.
+  verifyFormat("ffnand ff1(.qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2),\n"
+   "   .*);");
+  verifyFormat("ffnand ff1(.*,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With unconnected ports.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(),\n"
+   "   .clear(),\n"
+   "   .preset());");
+  verifyFormat("ffnand ff1(,\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  // With positional ports.
+  verifyFormat("ffnand ff1(out1,\n"
+   "   in1,\n"
+   "   in2);");
+  verifyFormat("ffnand ff1(,\n"
+   "   out1,\n"
+   "   in1,\n"
+   "   in2);");
+  // Multiple instantiations.
+  verifyFormat("ffnand ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2)),\n"
+   "   ff1(.q(),\n"
+   "   .qbar(out1),\n"
+   "   .clear(in1),\n"
+   "   .preset(in2));");
+  verifyFormat("ffnand //\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2)),\n"
+   "ff1(.q(),\n"
+   ".qbar(out1),\n"
+   ".clear(in1),\n"
+   ".preset(in2));");
+  // With breaking between instance ports disabled.
+  auto Style = getDefaultStyle();
+  Style.VerilogBreakBetweenInstancePorts = false;
+  verifyFormat("ffnand ff1;", Style);
+  verifyFormat("ffnand ff1(.qbar(out1), .clear(in1), .preset(in2), .*);",
+   Style);
+  verifyFormat("ffnand ff1(out1, in1, in2);", Style);
+  verifyFormat("ffnand ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "   ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+  verifyFormat("ffnand //\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2)),\n"
+   "ff1(.q(), .qbar(out1), .clear(in1), .preset(in2));",
+   Style);
+}
+
 TEST_F(FormatTestVerilog, Operators) {
   // Test that unary operators are not followed by space.
   verifyFormat("x = +x;");
Index: clang/unittests/Format/ConfigParseTest.cpp
===
--- clang/unittests/Format/ConfigParseTest.cpp
+++ clang/unittests/Format/ConfigParseTest.cpp
@@ -192,6 +192,7 @@
   CHECK_PARSE_BOOL(SpaceBeforeJsonColon);
   CHECK_PARSE_BOOL(SpaceBeforeRangeBasedForLoopColon);
   CHECK_PARSE_BOOL(SpaceBeforeSquareBrackets);
+  CHECK_PARSE_BOOL(VerilogBreakBetweenInstancePorts);
 
   CHECK_PARSE_NESTED_BOOL(BraceWrapping, AfterCaseLabel);
   CHECK_PARSE_NESTED_BOOL(BraceWrapping, AfterClass);
Index: clang/lib/Format/TokenAnnotator.cpp
===
--- clang/lib/Format/TokenAnnotator.cpp
+++ clang/lib/Format/TokenAnnotator.cpp
@@ -311,6 +311,9 @@
   bool OperatorCalledAsMemberFunction =
   Prev->Previous && Prev->Previous->isOneOf(tok::period, tok::arrow);
   Contexts.back().IsExpression = OperatorCalledAsMemberFunction;
+} else if (OpeningParen.is(TT_VerilogInstancePortLParen)) {
+  Contexts.back().IsExpression = true;
+  Contexts.back().ContextType = Context::VerilogInstancePortList;
 } else if (Style.isJavaScript() &&
(Line.startsWith(Keywords.kw_type,

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

[PATCH] D147327: [clang-format] Add option for having one port per line in Verilog

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