[PATCH] D29117: SPARC: allow usage of floating-point registers in inline ASM

2017-05-12 Thread James Y Knight via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL302913: [SPARC] Support 'f' and 'e' inline asm constraints. 
(authored by jyknight).

Changed prior to commit:
  https://reviews.llvm.org/D29117?vs=85708=98782#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D29117

Files:
  cfe/trunk/lib/Basic/Targets.cpp
  cfe/trunk/test/CodeGen/sparcv8-inline-asm.c


Index: cfe/trunk/lib/Basic/Targets.cpp
===
--- cfe/trunk/lib/Basic/Targets.cpp
+++ cfe/trunk/lib/Basic/Targets.cpp
@@ -6862,6 +6862,11 @@
 case 'N': // Same as 'K' but zext (required for SIMode)
 case 'O': // The constant 4096
   return true;
+
+case 'f':
+case 'e':
+  info.setAllowsRegister();
+  return true;
 }
 return false;
   }
Index: cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
===
--- cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
+++ cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | 
FileCheck %s
+
+// CHECK: define float @fabsf(float %a)
+// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float 
%{{.*}}) #1
+float fabsf(float a) {
+  float res;
+  __asm __volatile__("fabss  %1, %0;"
+ : /* reg out*/ "=e"(res)
+ : /* reg in */ "f"(a));
+  return res;
+}


Index: cfe/trunk/lib/Basic/Targets.cpp
===
--- cfe/trunk/lib/Basic/Targets.cpp
+++ cfe/trunk/lib/Basic/Targets.cpp
@@ -6862,6 +6862,11 @@
 case 'N': // Same as 'K' but zext (required for SIMode)
 case 'O': // The constant 4096
   return true;
+
+case 'f':
+case 'e':
+  info.setAllowsRegister();
+  return true;
 }
 return false;
   }
Index: cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
===
--- cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
+++ cfe/trunk/test/CodeGen/sparcv8-inline-asm.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define float @fabsf(float %a)
+// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}}) #1
+float fabsf(float a) {
+  float res;
+  __asm __volatile__("fabss  %1, %0;"
+ : /* reg out*/ "=e"(res)
+ : /* reg in */ "f"(a));
+  return res;
+}
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[PATCH] D29117: SPARC: allow usage of floating-point registers in inline ASM

2017-03-07 Thread Simon Dardis via Phabricator via cfe-commits 
sdardis added a comment.

> How do I create full-context-patches? Does this mean just more context lines? 
> Like 500 or 1000 lines?

http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface


https://reviews.llvm.org/D29117



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[PATCH] D29117: SPARC: allow usage of floating-point registers in inline ASM

2017-03-07 Thread Patrick Boettcher via Phabricator via cfe-commits 
pboettch added a comment.

On SparcV8 there is no %e register.

Regarding soft-float, good question, I'll try.

How do I create full-context-patches? Does this mean just more context lines? 
Like 500 or 1000 lines?


https://reviews.llvm.org/D29117



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[PATCH] D29117: SPARC: allow usage of floating-point registers in inline ASM

2017-03-06 Thread Bruno Cardoso Lopes via Phabricator via cfe-commits 
bruno added a comment.

Hi,

Thanks for working on this. Few questions:

- What happens with the validation if +soft-float is used?
- What about the 'e' mode, can you double check if the sparc backend support 
these instructions? If so it might be interesting to add it here.

Also, please attach patches with full context, it's easier to review.


https://reviews.llvm.org/D29117



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[PATCH] D29117: SPARC: allow usage of floating-point registers in inline ASM

2017-01-25 Thread Patrick Boettcher via Phabricator via cfe-commits 
pboettch updated this revision to Diff 85708.
pboettch added a comment.

Added  test-code.


https://reviews.llvm.org/D29117

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/sparcv8-inline-asm.c


Index: test/CodeGen/sparcv8-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/sparcv8-inline-asm.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | 
FileCheck %s
+
+// CHECK: define float @fabsf(float %a) #0 {
+// CHECK: %2 = call float asm sideeffect "fabss  $1, $0;", "=f,f"(float %1) #1
+float fabsf(float a) {
+  float res;
+  __asm __volatile__("fabss  %1, %0;"
+ : /* reg out*/ "=f"(res)
+ : /* reg in */ "f"(a));
+  return res;
+}
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6707,6 +6707,10 @@
 case 'N': // Same as 'K' but zext (required for SIMode)
 case 'O': // The constant 4096
   return true;
+
+case 'f':
+  info.setAllowsRegister();
+  return true;
 }
 return false;
   }


Index: test/CodeGen/sparcv8-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/sparcv8-inline-asm.c
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define float @fabsf(float %a) #0 {
+// CHECK: %2 = call float asm sideeffect "fabss  $1, $0;", "=f,f"(float %1) #1
+float fabsf(float a) {
+  float res;
+  __asm __volatile__("fabss  %1, %0;"
+ : /* reg out*/ "=f"(res)
+ : /* reg in */ "f"(a));
+  return res;
+}
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6707,6 +6707,10 @@
 case 'N': // Same as 'K' but zext (required for SIMode)
 case 'O': // The constant 4096
   return true;
+
+case 'f':
+  info.setAllowsRegister();
+  return true;
 }
 return false;
   }
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[PATCH] D29117: SPARC: allow usage of floating-point registers in inline ASM

2017-01-24 Thread Patrick Boettcher via Phabricator via cfe-commits 
pboettch created this revision.
Herald added a subscriber: jyknight.

Make clang recognize floating point registers in inline assembler
when using the targeting Sparc.

This code now works:

static inline float fabsf(float a)
{

  float res;
  __asm __volatile__("fabss  %1, %0;"
 : "=f"(res)
 : "f"(a));
  return res;

}


https://reviews.llvm.org/D29117

Files:
  lib/Basic/Targets.cpp


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6707,6 +6707,10 @@
 case 'N': // Same as 'K' but zext (required for SIMode)
 case 'O': // The constant 4096
   return true;
+
+case 'f':
+  info.setAllowsRegister();
+  return true;
 }
 return false;
   }


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6707,6 +6707,10 @@
 case 'N': // Same as 'K' but zext (required for SIMode)
 case 'O': // The constant 4096
   return true;
+
+case 'f':
+  info.setAllowsRegister();
+  return true;
 }
 return false;
   }
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