[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli added a comment. Alexey, thank you for reviewing this. If you don't mind, I will wait applying the changes you requested, Unfortunately I am not ready yet to send out an update as I am still working on the vector ABI. I will ping you when ready. Francesco https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
ABataev added inline comments.
Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:6818-6819
+ISAData);
+}
+if (CGM.getTriple().getArch() == llvm::Triple::aarch64) {
+ ISADataTy ISAData[] = {
else if
Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:6826
+ISAData);
+}
}
Maybe it is better to create `SmallVector ISAData` and fill it
for all architectures independently, but have just one call of
`emitTargetDeclareSimdFunction()`?
https://reviews.llvm.org/D30739
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[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli planned changes to this revision. fpetrogalli added a comment. Dear all, thank you for reviewing this patch. We found out an error in the spec and would like to fix it before things are used. I will soon update this patch. Thanks, Francesco https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
ABataev added a comment. Guys, sorry for the delay with the reviews. I was on a vacation, now I'm on a relocation process. Will look at all patches as soon as possible, but not earlier than next week :( Sorry again. https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli added a comment. Thanks, I do not have commit rights, can anyone commit this? https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
Hahnfeld accepted this revision. Hahnfeld added a comment. This revision is now accepted and ready to land. In https://reviews.llvm.org/D30739#706304, @fpetrogalli wrote: > AFAIK, none of the machinery required in LLVM to expose the mangled names in > the vectorizer is present in trunk. There is a patch for x86 under review > that does that: https://reviews.llvm.org/D22792 Thanks for the link. I think this patch is fine in that case. https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli added a comment. In https://reviews.llvm.org/D30739#706292, @Hahnfeld wrote: > In principal looks good to me although I'm not really familiar with this > part. Does that work for you if you have the `declare simd` in a header file > and the implementation in another file? On x86_64 I currently get: The current infrastructure for vector names generation works only for function definition. Ideally we should implement it also for function definition provided by external libraries. > remark: loop not vectorized: call instruction cannot be vectorized > > > But that seems to be a general problem inside LLVM's LoopVectorize pass... AFAIK, none of the machinery required in LLVM to expose the mangled names in the vectorizer is present in trunk. There is a patch for x86 under review that does that: https://reviews.llvm.org/D22792 https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
Hahnfeld added a comment. In principal looks good to me although I'm not really familiar with this part. Does that work for you if you have the `declare simd` in a header file and the implementation in another file? On x86_64 I currently get: remark: loop not vectorized: call instruction cannot be vectorized But that seems to be a general problem inside LLVM's LoopVectorize pass... https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
rengolin added inline comments.
Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:6821
+ ISADataTy ISAData[] = {
+ {'n', 64}, // double-word Advanced SIMD
+ {'n', 128}, // quad-word Advanced SIMD
fpetrogalli wrote:
> rengolin wrote:
> > No f32?
> Sorry, I am not sure to understand what you mean here by f32.
>
> I am considering the double-word registers (64 bits wide) and quad-word
> registers (128 bits wide) that are used in AdvSIMD (NEON) for AArch64 [1].
>
> [1]
> https://developer.arm.com/docs/dui0473/latest/neon-programming/neon-views-of-the-extension-register-bank
Sorry, I meant S0~Sn, but that's silly, as it's VFP. Ignore me.
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[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli added inline comments.
Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:6821
+ ISADataTy ISAData[] = {
+ {'n', 64}, // double-word Advanced SIMD
+ {'n', 128}, // quad-word Advanced SIMD
rengolin wrote:
> No f32?
Sorry, I am not sure to understand what you mean here by f32.
I am considering the double-word registers (64 bits wide) and quad-word
registers (128 bits wide) that are used in AdvSIMD (NEON) for AArch64 [1].
[1]
https://developer.arm.com/docs/dui0473/latest/neon-programming/neon-views-of-the-extension-register-bank
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[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
rengolin added reviewers: Hahnfeld, carlo.bertolli, arpith-jacob.
rengolin added a comment.
Looks ok to me, but I'm not very knowledgeable in that area. Hopefully some
OpenMP Clang developers I added could give you a more concrete approval. :)
Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:6821
+ ISADataTy ISAData[] = {
+ {'n', 64}, // double-word Advanced SIMD
+ {'n', 128}, // quad-word Advanced SIMD
No f32?
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[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli added a comment. Gentle ping. Thanks, Francesco https://reviews.llvm.org/D30739 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli updated this revision to Diff 91035.
fpetrogalli marked an inline comment as done.
fpetrogalli added a comment.
Changes:
- fixed formatting;
- added two tests that were missing.
https://reviews.llvm.org/D30739
Files:
lib/Basic/Targets.cpp
lib/CodeGen/CGOpenMPRuntime.cpp
test/OpenMP/declare_simd_codegen.cpp
Index: test/OpenMP/declare_simd_codegen.cpp
===
--- test/OpenMP/declare_simd_codegen.cpp
+++ test/OpenMP/declare_simd_codegen.cpp
@@ -1,15 +1,86 @@
-// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck --check-prefix=X86 %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s
+// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck --check-prefix=X86 %s
+
+// RUN: %clang_cc1 -verify -triple aarch64-linux-gnu -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck --check-prefix=AARCH64 %s
+// RUN: %clang_cc1 -fopenmp -x c++ -triple aarch64-linux-gnu -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -x c++ -triple aarch64-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck --check-prefix=AARCH64 %s
+
// expected-no-diagnostics
+
+// X86-DAG: define {{.+}}@_Z5add_1Pf(
+// X86-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_(
+// X86-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_(
+// X86-DAG: define {{.+}}@_ZN2VV3addEii(
+// X86-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_(
+// X86-DAG: define {{.+}}@_ZN2VV4taddERA_iRi(
+// X86-DAG: define {{.+}}@_Z1fRA_i(
+// X86-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_(
+// X86-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi(
+// X86-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf(
+// X86-DAG: define {{.+}}@_Z3bar2VVPf(
+// X86-DAG: define {{.+}}@_Z3baz2VVPi(
+// X86-DAG: define {{.+}}@_Z3bay2VVRPd(
+// X86-DAG: define {{.+}}@_Z3bax2VVPdi(
+// X86-DAG: define {{.+}}@_Z3fooPffi(
+// X86-DAG: define {{.+}}@_Z3food(
+// X86-NOT: "_ZGV{{.+}}__Z1fRA_i
+
+// AARCH64-DAG: define {{.+}}@_Z5add_1Pf(
+// AARCH64-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_(
+// AARCH64-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_(
+// AARCH64-DAG: define {{.+}}@_ZN2VV3addEii(
+// AARCH64-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_(
+// AARCH64-DAG: define {{.+}}@_ZN2VV4taddERA_iRi(
+// AARCH64-DAG: define {{.+}}@_Z1fRA_i(
+// AARCH64-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_(
+// AARCH64-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi(
+// AARCH64-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf(
+// AARCH64-DAG: define {{.+}}@_Z3bar2VVPf(
+// AARCH64-DAG: define {{.+}}@_Z3baz2VVPi(
+// AARCH64-DAG: define {{.+}}@_Z3bay2VVRPd(
+// AARCH64-DAG: define {{.+}}@_Z3bax2VVPdi(
+// AARCH64-DAG: define {{.+}}@_Z3fooPffi(
+// AARCH64-DAG: define {{.+}}@_Z3food(
+// AARCH64-NOT: "_ZGV{{.+}}__Z1fRA_i
+
#ifndef HEADER
#define HEADER
#pragma omp declare simd linear(d : 8)
#pragma omp declare simd inbranch simdlen(32)
#pragma omp declare simd notinbranch
void add_1(float *d) {}
+// X86-DAG: "_ZGVbM4l8__Z5add_1Pf"
+// X86-DAG: "_ZGVbN4l8__Z5add_1Pf"
+// X86-DAG: "_ZGVcM8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVcN8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVdM8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVdN8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVeM16l8__Z5add_1Pf"
+// X86-DAG: "_ZGVeN16l8__Z5add_1Pf"
+// X86-DAG: "_ZGVbM32v__Z5add_1Pf"
+// X86-DAG: "_ZGVcM32v__Z5add_1Pf"
+// X86-DAG: "_ZGVdM32v__Z5add_1Pf"
+// X86-DAG: "_ZGVeM32v__Z5add_1Pf"
+// X86-DAG: "_ZGVbN2v__Z5add_1Pf"
+// X86-DAG: "_ZGVcN4v__Z5add_1Pf"
+// X86-DAG: "_ZGVdN4v__Z5add_1Pf"
+// X86-DAG: "_ZGVeN8v__Z5add_1Pf"
+
+// AARCH64-DAG: "_ZGVnM2l8__Z5add_1Pf"
+// AARCH64-DAG: "_ZGVnN2l8__Z5add_1Pf"
+// AARCH64-DAG: "_ZGVnM4l8__Z5add_1Pf"
+// AARCH64-DAG: "_ZGVnN4l8__Z5add_1Pf"
+
+// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf"
+// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf"
+// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf"
+// AARCH64-DAG: "_ZGVnM32v__Z5add_1Pf"
+
+// AARCH64-DAG: "_ZGVnN2v__Z5add_1Pf"
+
#pragma omp declare simd aligned(hp, hp2)
template
void h(C *hp, C *hp2, C *hq, C *lin) {
@@ -26,6 +97,30 @@
h((float *)hp, (float *)hp2, (float *)hq, (float *)lin);
}
+// X86-DAG: "_ZGVbM2va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+// X86-DAG: "_ZGVbN2va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+// X86-DAG: "_ZGVcM4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+// X86-DAG: "_ZGVcN4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+// X86-DAG: "_ZGVdM4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+// X86-DAG: "_ZGVdN4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+// X86-DAG: "_ZGVeM8va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+// X86-DAG: "_ZGVeN8va16va16vv__Z1hIiEvPT_S1_S1_S1_"
+
+// X86-DAG: "_ZGVbM2va16va16vv__Z1hIfEvPT_S1_S1_S1_"
+// X86-DAG:
[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fhahn added inline comments.
Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:6664
+
+ static void
+ emitTargetDeclareSimdFunction(const FunctionDecl *FD, llvm::Function *Fn,
Shouldn't this indentation be on the same level as namespace{}?
https://reviews.llvm.org/D30739
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[PATCH] D30739: [OpenMP] "declare simd" for AArch64 Advanced SIMD.
fpetrogalli created this revision.
Herald added subscribers: rengolin, aemerson.
This patch enables the code generation of vector function names that are
described by attaching a "#pragma omp declare simd" directive to the
scalar function definition/declaration, for the Advanced SIMD (NEON)
vector extension of the A64 instruction set for the AArch64 execution
state of the ARMv8 architecture.
As it is done for other targets, the available vector functions are
stored as string attributes attached to the scalar function in the IR,
and are made available for further processing in the middle
end (e.g. exposure to the loop vectorizer).
The mangling function of the vector names is compatible with the
Itanium-standard names that are being generated for X86.
The value of the token that specifies the architecture extension is 'n'
- as for NEON.
Changes
---
- The `SimdDefaultAlign` value of the AArch64TargetInfo class has been set to
128-bit - the size of a quad-word register "Q" for NEON.
- The name mangling function for X86 has been merged into a generic one
that is shared with AArch64, as `emitTargetDeclareSimdFunction`.
- The CodeGen test has been split into X86 and AArch64 runs.
- To improve readability and maintainability, the actual FileCheck
checks (both for X86 and AArch64) have been moved right after the
respective function declarations.
Note
The patch does not introduce any functional change for the X86 target.
https://reviews.llvm.org/D30739
Files:
lib/Basic/Targets.cpp
lib/CodeGen/CGOpenMPRuntime.cpp
test/OpenMP/declare_simd_codegen.cpp
Index: test/OpenMP/declare_simd_codegen.cpp
===
--- test/OpenMP/declare_simd_codegen.cpp
+++ test/OpenMP/declare_simd_codegen.cpp
@@ -1,15 +1,86 @@
-// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck --check-prefix=X86 %s
// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s
+// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck --check-prefix=X86 %s
+
+// RUN: %clang_cc1 -verify -triple aarch64-linux-gnu -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck --check-prefix=AARCH64 %s
+// RUN: %clang_cc1 -fopenmp -x c++ -triple aarch64-linux-gnu -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -x c++ -triple aarch64-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck --check-prefix=AARCH64 %s
+
// expected-no-diagnostics
+
+// X86-DAG: define {{.+}}@_Z5add_1Pf(
+// X86-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_(
+// X86-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_(
+// X86-DAG: define {{.+}}@_ZN2VV3addEii(
+// X86-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_(
+// X86-DAG: define {{.+}}@_ZN2VV4taddERA_iRi(
+// X86-DAG: define {{.+}}@_Z1fRA_i(
+// X86-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_(
+// X86-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi(
+// X86-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf(
+// X86-DAG: define {{.+}}@_Z3bar2VVPf(
+// X86-DAG: define {{.+}}@_Z3baz2VVPi(
+// X86-DAG: define {{.+}}@_Z3bay2VVRPd(
+// X86-DAG: define {{.+}}@_Z3bax2VVPdi(
+// X86-DAG: define {{.+}}@_Z3fooPffi(
+// X86-DAG: define {{.+}}@_Z3food(
+// X86-NOT: "_ZGV{{.+}}__Z1fRA_i
+
+// AARCH64-DAG: define {{.+}}@_Z5add_1Pf(
+// AARCH64-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_(
+// AARCH64-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_(
+// AARCH64-DAG: define {{.+}}@_ZN2VV3addEii(
+// AARCH64-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_(
+// AARCH64-DAG: define {{.+}}@_ZN2VV4taddERA_iRi(
+// AARCH64-DAG: define {{.+}}@_Z1fRA_i(
+// AARCH64-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_(
+// AARCH64-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi(
+// AARCH64-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf(
+// AARCH64-DAG: define {{.+}}@_Z3bar2VVPf(
+// AARCH64-DAG: define {{.+}}@_Z3baz2VVPi(
+// AARCH64-DAG: define {{.+}}@_Z3bay2VVRPd(
+// AARCH64-DAG: define {{.+}}@_Z3bax2VVPdi(
+// AARCH64-DAG: define {{.+}}@_Z3fooPffi(
+// AARCH64-DAG: define {{.+}}@_Z3food(
+// AARCH64-NOT: "_ZGV{{.+}}__Z1fRA_i
+
#ifndef HEADER
#define HEADER
#pragma omp declare simd linear(d : 8)
#pragma omp declare simd inbranch simdlen(32)
#pragma omp declare simd notinbranch
void add_1(float *d) {}
+// X86-DAG: "_ZGVbM4l8__Z5add_1Pf"
+// X86-DAG: "_ZGVbN4l8__Z5add_1Pf"
+// X86-DAG: "_ZGVcM8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVcN8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVdM8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVdN8l8__Z5add_1Pf"
+// X86-DAG: "_ZGVeM16l8__Z5add_1Pf"
+// X86-DAG: "_ZGVeN16l8__Z5add_1Pf"
+// X86-DAG: "_ZGVbM32v__Z5add_1Pf"
+// X86-DAG: "_ZGVcM32v__Z5add_1Pf"
+//
