[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
This revision was automatically updated to reflect the committed changes.
Closed by commit rL320528: [libunwind][MIPS]: Add support for unwinding in O32
and N64 processes. (authored by jhb, committed by ).
Repository:
rL LLVM
https://reviews.llvm.org/D38110
Files:
libunwind/trunk/include/__libunwind_config.h
libunwind/trunk/include/libunwind.h
libunwind/trunk/src/Registers.hpp
libunwind/trunk/src/UnwindCursor.hpp
libunwind/trunk/src/UnwindRegistersRestore.S
libunwind/trunk/src/UnwindRegistersSave.S
libunwind/trunk/src/config.h
libunwind/trunk/src/libunwind.cpp
Index: libunwind/trunk/src/UnwindRegistersRestore.S
===
--- libunwind/trunk/src/UnwindRegistersRestore.S
+++ libunwind/trunk/src/UnwindRegistersRestore.S
@@ -534,6 +534,118 @@
l.jr r9
l.nop
+#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float)
+
+//
+// void libunwind::Registers_mips_o32::jumpto()
+//
+// On entry:
+// thread state pointer is in a0 ($4)
+//
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
+ .set push
+ .set noat
+ .set noreorder
+ .set nomacro
+ // restore hi and lo
+ lw$8, (4 * 33)($4)
+ mthi $8
+ lw$8, (4 * 34)($4)
+ mtlo $8
+ // r0 is zero
+ lw$1, (4 * 1)($4)
+ lw$2, (4 * 2)($4)
+ lw$3, (4 * 3)($4)
+ // skip a0 for now
+ lw$5, (4 * 5)($4)
+ lw$6, (4 * 6)($4)
+ lw$7, (4 * 7)($4)
+ lw$8, (4 * 8)($4)
+ lw$9, (4 * 9)($4)
+ lw$10, (4 * 10)($4)
+ lw$11, (4 * 11)($4)
+ lw$12, (4 * 12)($4)
+ lw$13, (4 * 13)($4)
+ lw$14, (4 * 14)($4)
+ lw$15, (4 * 15)($4)
+ lw$16, (4 * 16)($4)
+ lw$17, (4 * 17)($4)
+ lw$18, (4 * 18)($4)
+ lw$19, (4 * 19)($4)
+ lw$20, (4 * 20)($4)
+ lw$21, (4 * 21)($4)
+ lw$22, (4 * 22)($4)
+ lw$23, (4 * 23)($4)
+ lw$24, (4 * 24)($4)
+ lw$25, (4 * 25)($4)
+ lw$26, (4 * 26)($4)
+ lw$27, (4 * 27)($4)
+ lw$28, (4 * 28)($4)
+ lw$29, (4 * 29)($4)
+ lw$30, (4 * 30)($4)
+ // load new pc into ra
+ lw$31, (4 * 32)($4)
+ // jump to ra, load a0 in the delay slot
+ jr$31
+ lw$4, (4 * 4)($4)
+ .set pop
+
+#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float)
+
+//
+// void libunwind::Registers_mips_n64::jumpto()
+//
+// On entry:
+// thread state pointer is in a0 ($4)
+//
+DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv)
+ .set push
+ .set noat
+ .set noreorder
+ .set nomacro
+ // restore hi and lo
+ ld$8, (8 * 33)($4)
+ mthi $8
+ ld$8, (8 * 34)($4)
+ mtlo $8
+ // r0 is zero
+ ld$1, (8 * 1)($4)
+ ld$2, (8 * 2)($4)
+ ld$3, (8 * 3)($4)
+ // skip a0 for now
+ ld$5, (8 * 5)($4)
+ ld$6, (8 * 6)($4)
+ ld$7, (8 * 7)($4)
+ ld$8, (8 * 8)($4)
+ ld$9, (8 * 9)($4)
+ ld$10, (8 * 10)($4)
+ ld$11, (8 * 11)($4)
+ ld$12, (8 * 12)($4)
+ ld$13, (8 * 13)($4)
+ ld$14, (8 * 14)($4)
+ ld$15, (8 * 15)($4)
+ ld$16, (8 * 16)($4)
+ ld$17, (8 * 17)($4)
+ ld$18, (8 * 18)($4)
+ ld$19, (8 * 19)($4)
+ ld$20, (8 * 20)($4)
+ ld$21, (8 * 21)($4)
+ ld$22, (8 * 22)($4)
+ ld$23, (8 * 23)($4)
+ ld$24, (8 * 24)($4)
+ ld$25, (8 * 25)($4)
+ ld$26, (8 * 26)($4)
+ ld$27, (8 * 27)($4)
+ ld$28, (8 * 28)($4)
+ ld$29, (8 * 29)($4)
+ ld$30, (8 * 30)($4)
+ // load new pc into ra
+ ld$31, (8 * 32)($4)
+ // jump to ra, load a0 in the delay slot
+ jr$31
+ ld$4, (8 * 4)($4)
+ .set pop
+
#endif
#endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
Index: libunwind/trunk/src/Registers.hpp
===
--- libunwind/trunk/src/Registers.hpp
+++ libunwind/trunk/src/Registers.hpp
@@ -2041,6 +2041,418 @@
}
#endif // _LIBUNWIND_TARGET_OR1K
+
+#if defined(_LIBUNWIND_TARGET_MIPS_O32)
+/// Registers_mips_o32 holds the register state of a thread in a 32-bit MIPS
+/// process.
+class _LIBUNWIND_HIDDEN Registers_mips_o32 {
+public:
+ Registers_mips_o32();
+ Registers_mips_o32(const void *registers);
+
+ boolvalidRegister(int num) const;
+ uint32_tgetRegister(int num) const;
+ voidsetRegister(int num, uint32_t value);
+ boolvalidFloatRegister(int num) const;
+ double getFloatRegister(int num) const;
+ voidsetFloatRegister(int num, double value);
+ boolvalidVectorRegister(int num) const;
+ v128getVectorRegister(int num) const;
+ voidsetVectorRegister(int num, v128 value);
+ const char *getRegisterName(int num);
+ voidjumpto();
+ static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS; }
+
+ uint32_t getSP() const { return _registers.__r[29]; }
+ void setSP(uint32_t value) { _registers.__r[29] = value; }
+ uint32_t getIP() const { return _registers.__pc; }
+
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
sdardis accepted this revision. sdardis added a comment. This revision is now accepted and ready to land. LGTM. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
compnerd accepted this revision. compnerd added a comment. LGTM if @sdardis is good with it https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. Ping @compnerd, @sdardis https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
sdardis added a comment. @compnerd, ping? https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. Ping https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 121396. bsdjhb added a comment. - Rebase. - Update O32 cursor size after unw_word_t change. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -59,8 +59,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -67,7 +67,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,6 +116,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -524,6 +524,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +//
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. In https://reviews.llvm.org/D38110#910526, @mstorsjo wrote: > Just a heads up WRT this patch; we're discussing changing the size of > `unw_word_t` to match `uintptr_t` in https://reviews.llvm.org/D39365. Does > that break anything for your case? It shouldn't affect what's stored in the > Register class, only pointers in the unw_proc_info_t struct. Not sure which > patch will get completed/merged first though. Yes, I saw that. It will probably cause some breakage for the cursor size depending on which path (uint64_t always vs uintptr_t). I'm not quite sure which of those approaches is more correct to be honest. I also have an N32 patch in review but will wait until this one is finally committed before updating that further. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
mstorsjo added a comment. Just a heads up WRT this patch; we're discussing changing the size of `unw_word_t` to match `uintptr_t` in https://reviews.llvm.org/D39365. Does that break anything for your case? It shouldn't affect what's stored in the Register class, only pointers in the unw_proc_info_t struct. Not sure which patch will get completed/merged first though. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 120798. bsdjhb marked an inline comment as done. bsdjhb added a comment. - Rebase on more MAX_REGISTER changes. - Use macro for lastDwarfRegisterNumber. - Move MIPS ABI constants under a single #ifdef __mips__. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -59,8 +59,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -67,7 +67,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,6 +116,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -524,6 +524,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
compnerd added inline comments.
Comment at: include/__libunwind_config.h:69
+# define _LIBUNWIND_CURSOR_SIZE 47
+# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 65
# else
Can we sink the two cases into the `__mips__` case? Something like:
#if defined(__mips__)
# if defined(_ABIO32)
# elif defined(_ABIO64)
# elif defined(_ABIN32)
# elif defined(_ABI64)
# else
# error "unknown MIPS ABI"
# endif
#else
Comment at: src/Registers.hpp:2063
+ voidjumpto();
+ static int lastDwarfRegNum() { return 31; }
+
I believe we have a macro for this.
https://reviews.llvm.org/D38110
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[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 120623. bsdjhb added a comment. - Rebase for recent change to MAX_REGISTER meaning. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -59,8 +59,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -67,7 +67,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -116,6 +116,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -524,6 +524,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb marked an inline comment as done. bsdjhb added a comment. Ping? https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb marked 2 inline comments as done. bsdjhb added inline comments. Comment at: src/UnwindRegistersSave.S:100 +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push sdardis wrote: > After looking at another implementation of libunwind and the other platforms > that are supported, it seems to me that we need to save all the registers. I was about to ask if that would be better as well. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 119245. bsdjhb added a comment. - Save all of the general purpose registers. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,118 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sw$1, (4 * 1)($4) + sw$2, (4 * 2)($4) + sw$3, (4 * 3)($4) + sw$4, (4 * 4)($4) + sw$5, (4 * 5)($4) + sw$6, (4 * 6)($4) + sw$7, (4 * 7)($4) + sw$8, (4 * 8)($4) + sw$9, (4 * 9)($4) + sw$10, (4 * 10)($4) + sw$11, (4 * 11)($4) + sw$12, (4 * 12)($4) + sw$13, (4 * 13)($4) + sw$14, (4 * 14)($4) + sw$15, (4 * 15)($4) + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + sw$24, (4 * 24)($4) + sw$25, (4 * 25)($4) + sw$26, (4 * 26)($4) + sw$27, (4 * 27)($4) + sw$28, (4 * 28)($4) + sw$29, (4 * 29)($4) + sw$30, (4 * 30)($4) + sw$31, (4 * 31)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + sd$1, (8 * 1)($4) + sd$2, (8 * 2)($4) + sd$3, (8 * 3)($4) + sd$4, (8 * 4)($4) + sd$5, (8 * 5)($4) + sd$6, (8 * 6)($4) + sd$7, (8 * 7)($4) + sd$8, (8 * 8)($4) + sd$9, (8 * 9)($4) + sd$10, (8 * 10)($4) + sd$11, (8 * 11)($4) + sd$12, (8 * 12)($4) + sd$13, (8 * 13)($4) + sd$14, (8 * 14)($4) + sd$15, (8 * 15)($4) + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + sd$24, (8 * 24)($4) + sd$25, (8 * 25)($4) + sd$26, (8 * 26)($4) + sd$27, (8 * 27)($4) + sd$28, (8 * 28)($4) + sd$29, (8 * 29)($4) + sd$30, (8 * 30)($4) + sd$31, (8 * 31)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
sdardis added a reviewer: compnerd. sdardis added a subscriber: compnerd. sdardis added a comment. Two last inlined comments and I think that's everything. @compnerd Have I missed anything? Comment at: src/UnwindRegistersSave.S:100 +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push After looking at another implementation of libunwind and the other platforms that are supported, it seems to me that we need to save all the registers. Comment at: src/UnwindRegistersSave.S:142 +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push Similarly here as well. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 118960. bsdjhb added a comment. - Check _ABI* rather than _MIPS_SIM. - Save and restore lo/hi. - Expand FIXME comment for more missing registers. - Return UNW_SUCCESS from unw_getcontext(). - Use correct DWARF numbers for hi and lo and put hi first. - Bump highest DWARF number for hi and lo. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,90 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # hi and lo + mfhi $8 + sw$8, (4 * 33)($4) + mflo $8 + sw$8, (4 * 34)($4) + # s0 - s7 + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + # gp + sw$28, (4 * 28)($4) + # sp + sw$29, (4 * 29)($4) + # fp + sw$30, (4 * 30)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + +#elif defined(__mips__) && defined(_ABI64) && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # hi and lo + mfhi $8 + sd$8, (8 * 33)($4) + mflo $8 + sd$8, (8 * 34)($4) + # s0 - s7 + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + # gp + sd$28, (8 * 28)($4) + # sp + sd$29, (8 * 29)($4) + # fp + sd$30, (8 * 30)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + jr $31 + # return UNW_ESUCCESS + or$2, $0, $0 + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,118 @@ l.jr r9 l.nop +#elif defined(__mips__) && defined(_ABIO32) && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set push + .set noat + .set noreorder + .set nomacro + // restore hi and lo + lw$8, (4 * 33)($4) + mthi $8 + lw$8, (4 * 34)($4) + mtlo $8 + // r0 is zero + lw$1, (4 * 1)($4) + lw$2, (4 * 2)($4) + lw$3, (4 * 3)($4) + // skip a0 for now + lw$5, (4 * 5)($4) + lw$6, (4 * 6)($4) + lw$7, (4 * 7)($4) + lw$8, (4 * 8)($4) + lw$9, (4 * 9)($4) + lw$10, (4 * 10)($4) + lw$11, (4 * 11)($4) + lw$12, (4 * 12)($4) + lw$13, (4 * 13)($4) + lw$14, (4 * 14)($4) + lw$15, (4 * 15)($4) + lw$16, (4 * 16)($4) + lw$17, (4 * 17)($4) + lw$18, (4 * 18)($4) + lw$19, (4 *
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
sdardis requested changes to this revision. sdardis added a comment. This revision now requires changes to proceed. Marking this as changes required to clear up my review queue - no further comments. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
sdardis added a comment. I have tested this on one of my machines after removing the checks for soft float (my debian install doesn't have the necessary headers for soft-float). With the patch you've pointed out and my inline comments addressed (bar the HI / LO register comments), it passes the supplied test suite. Can you change the checks for ABI from '_MIPS_SIM == $ABI' to 'defined($ABI)'? I mistakenly assumed they were always defined and that _MIPS_SIM was defined to be one of them but they are only defined when that particular ABI is being used. Comment at: include/libunwind.h:584 + UNW_MIPS_R31 = 31, +}; + Requires HI / LO registers. Comment at: src/Registers.hpp:2014 +uint32_t __pc; + }; + This appears to be missing the HI / LO registers. Comment at: src/Registers.hpp:2039 +return true; + // FIXME: Hard float + return false; FIXME: Hard float, DSP accumulator registers, MSA registers Comment at: src/UnwindRegistersSave.S:120-122 + jr $31 + # fp (in delay slot) + sw$30, (4 * 30)($4) Move the last store out of the delay slot and put 'or $2, $zero, $zero' in the delay slot to return UNW_ESUCCESS. Comment at: src/UnwindRegistersSave.S:155-157 + jr $31 + # fp (in delay slot) + sd$30, (8 * 30)($4) Move the last store out of the delay slot and put 'or $2, $zero, $zero' in the delay slot to return UNW_ESUCCESS. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 118638. bsdjhb added a comment. - Add more soft-float checks. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,76 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + # gp + sw$28, (4 * 28)($4) + # sp + sw$29, (4 * 29)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + jr $31 + # fp (in delay slot) + sw$30, (4 * 30)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + # gp + sd$28, (8 * 28)($4) + # sp + sd$29, (8 * 29)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + jr $31 + # fp (in delay slot) + sd$30, (8 * 30)($4) + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,108 @@ l.jr r9 l.nop +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set push + .set noat + .set noreorder + .set nomacro + // r0 is zero + lw$1, (4 * 1)($4) + lw$2, (4 * 2)($4) + lw$3, (4 * 3)($4) + // skip a0 for now + lw$5, (4 * 5)($4) + lw$6, (4 * 6)($4) + lw$7, (4 * 7)($4) + lw$8, (4 * 8)($4) + lw$9, (4 * 9)($4) + lw$10, (4 * 10)($4) + lw$11, (4 * 11)($4) + lw$12, (4 * 12)($4) + lw$13, (4 * 13)($4) + lw$14, (4 * 14)($4) + lw$15, (4 * 15)($4) + lw$16, (4 * 16)($4) + lw$17, (4 * 17)($4) + lw$18, (4 * 18)($4) + lw$19, (4 * 19)($4) + lw$20, (4 * 20)($4) + lw$21, (4 * 21)($4) + lw$22, (4 * 22)($4) + lw$23, (4 * 23)($4) + lw$24, (4 * 24)($4) + lw$25, (4 * 25)($4) + lw$26, (4 * 26)($4) + lw$27, (4 * 27)($4) + lw$28, (4 * 28)($4) + lw$29, (4 * 29)($4) + lw$30, (4 * 30)($4) + // load new pc into ra + lw$31, (4 * 32)($4) + // jump to ra, load a0 in the delay slot + jr$31 + lw$4, (4 * 4)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) + +// +// void
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
sdardis added a comment. Thanks for the pointer to that patch, I'll take a look tomorrow. Comment at: src/UnwindRegistersRestore.S:492 +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 + Needs checking for soft-float. Comment at: src/UnwindRegistersRestore.S:543 + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 + Needs checking for soft-float. Comment at: src/UnwindRegistersSave.S:90 +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 + Needs checking for soft-float. Comment at: src/UnwindRegistersSave.S:125 + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 + Needs checking for soft-float. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. I keep running into issues trying to cross-build LLVM (it keeps wanting to use /usr/bin/cc or host libraries even though cross-compiling is enabled). I wonder if the failures you saw Simon might be due to https://bugs.llvm.org/show_bug.cgi?id=33858? Could you try applying the patch from https://reviews.llvm.org/D37484 along with this patchset to see if it fixes the test failures for you? https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb added a comment. FYI, I was able to do simple testing (C++ programs throwing exceptions) using GCC 6.3 to compile a FreeBSD userland for both O32 and N64. Still working on cross-compiling LLVM so I can run the tests under qemu. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb marked 14 inline comments as done. bsdjhb added a comment. I have only tested this (test programs as mentioned earlier) with clang 5.0.0 (with a few patches) on o32 and n64. I am in the process of performing the same tests with GCC 6.3.0. I will also spend some time figuring out how to cross-build libunwind tests and run them inside of a qemu instance. https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
bsdjhb updated this revision to Diff 117438. bsdjhb added a comment. - Fixes from review feedback. https://reviews.llvm.org/D38110 Files: include/__libunwind_config.h include/libunwind.h src/Registers.hpp src/UnwindCursor.hpp src/UnwindRegistersRestore.S src/UnwindRegistersSave.S src/config.h src/libunwind.cpp Index: src/libunwind.cpp === --- src/libunwind.cpp +++ src/libunwind.cpp @@ -58,8 +58,12 @@ # define REGISTER_KIND Registers_arm #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_o32 +#elif defined(__mips__) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) +# define REGISTER_KIND Registers_mips_n64 #elif defined(__mips__) -# warning The MIPS architecture is not supported. +# warning The MIPS architecture is not supported with this ABI and environment! #else # error Architecture not supported #endif Index: src/config.h === --- src/config.h +++ src/config.h @@ -65,7 +65,7 @@ defined(__ppc__) || defined(__ppc64__) || \ (!defined(__APPLE__) && defined(__arm__)) || \ (defined(__arm64__) || defined(__aarch64__)) ||\ -(defined(__APPLE__) && defined(__mips__)) +defined(__mips__) #define _LIBUNWIND_BUILD_ZERO_COST_APIS #endif Index: src/UnwindRegistersSave.S === --- src/UnwindRegistersSave.S +++ src/UnwindRegistersSave.S @@ -87,6 +87,76 @@ xorl %eax, %eax# return UNW_ESUCCESS ret +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sw$16, (4 * 16)($4) + sw$17, (4 * 17)($4) + sw$18, (4 * 18)($4) + sw$19, (4 * 19)($4) + sw$20, (4 * 20)($4) + sw$21, (4 * 21)($4) + sw$22, (4 * 22)($4) + sw$23, (4 * 23)($4) + # gp + sw$28, (4 * 28)($4) + # sp + sw$29, (4 * 29)($4) + # Store return address to pc + sw$31, (4 * 32)($4) + jr $31 + # fp (in delay slot) + sw$30, (4 * 30)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 + +# +# extern int unw_getcontext(unw_context_t* thread_state) +# +# On entry: +# thread_state pointer is in a0 ($4) +# +# Only save registers preserved across calls. +# +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set push + .set noat + .set noreorder + .set nomacro + # s0 - s7 + sd$16, (8 * 16)($4) + sd$17, (8 * 17)($4) + sd$18, (8 * 18)($4) + sd$19, (8 * 19)($4) + sd$20, (8 * 20)($4) + sd$21, (8 * 21)($4) + sd$22, (8 * 22)($4) + sd$23, (8 * 23)($4) + # gp + sd$28, (8 * 28)($4) + # sp + sd$29, (8 * 29)($4) + # Store return address to pc + sd$31, (8 * 32)($4) + jr $31 + # fp (in delay slot) + sd$30, (8 * 30)($4) + .set pop + # elif defined(__mips__) # Index: src/UnwindRegistersRestore.S === --- src/UnwindRegistersRestore.S +++ src/UnwindRegistersRestore.S @@ -489,6 +489,108 @@ l.jr r9 l.nop +#elif defined(__mips__) && _MIPS_SIM == _ABIO32 + +// +// void libunwind::Registers_mips_o32::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +// +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv) + .set push + .set noat + .set noreorder + .set nomacro + // r0 is zero + lw$1, (4 * 1)($4) + lw$2, (4 * 2)($4) + lw$3, (4 * 3)($4) + // skip a0 for now + lw$5, (4 * 5)($4) + lw$6, (4 * 6)($4) + lw$7, (4 * 7)($4) + lw$8, (4 * 8)($4) + lw$9, (4 * 9)($4) + lw$10, (4 * 10)($4) + lw$11, (4 * 11)($4) + lw$12, (4 * 12)($4) + lw$13, (4 * 13)($4) + lw$14, (4 * 14)($4) + lw$15, (4 * 15)($4) + lw$16, (4 * 16)($4) + lw$17, (4 * 17)($4) + lw$18, (4 * 18)($4) + lw$19, (4 * 19)($4) + lw$20, (4 * 20)($4) + lw$21, (4 * 21)($4) + lw$22, (4 * 22)($4) + lw$23, (4 * 23)($4) + lw$24, (4 * 24)($4) + lw$25, (4 * 25)($4) + lw$26, (4 * 26)($4) + lw$27, (4 * 27)($4) + lw$28, (4 * 28)($4) + lw$29, (4 * 29)($4) + lw$30, (4 * 30)($4) + // load new pc into ra + lw$31, (4 * 32)($4) + // jump to ra, load a0 in the delay slot + jr$31 + lw$4, (4 * 4)($4) + .set pop + +#elif defined(__mips__) && _MIPS_SIM == _ABI64 + +// +// void libunwind::Registers_mips_n64::jumpto() +// +// On entry: +// thread state pointer is in a0 ($4) +//
[PATCH] D38110: [libunwind][MIPS]: Add support for unwinding in O32 and N64 processes.
sdardis edited subscribers, added: cfe-commits; removed: llvm-commits. sdardis added a comment. +CC cfe-commits, -CC llvm-commits. Some comments inlined. I've managed to run the test-suite on one of my machines here and I'm seeing 3 failures: libunwind :: libunwind_01.pass.cpp libunwind :: libunwind_02.pass.cpp libunwind :: unw_getcontext.pass.cpp This is with a GCC toolchain, 6.3. Did you test with clang? Comment at: include/__libunwind_config.h:54 # define _LIBUNWIND_HIGHEST_DWARF_REGISTER 32 +# elif defined(__mips_o32) +# define _LIBUNWIND_TARGET_MIPS_O32 1 Can you avoid using the __mips_o32 macro and instead use defined(__mips__) && _MIPS_SIM == _ABIO32 ? It appears the __mips_o32 is a FreeBSD specific macro. Also, test for __mips_soft_float . Comment at: include/__libunwind_config.h:59 +# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 32 +# elif defined(__mips_n64) +# define _LIBUNWIND_TARGET_MIPS_N64 1 Likewise "defined(__mips__) && _MIPS_SIM == _ABI64 && __mips_soft_float" Comment at: src/UnwindRegistersRestore.S:492 +#elif defined(__mips_o32) + defined(__mips_o32) -> defined(__mips__) && _MIPS_SIM == _ABIO32 Comment at: src/UnwindRegistersRestore.S:500 +// + .set noreorder + .set noat Prefix this with: .set push .set nomacro Also, the assembler directives should come after the function declaration / defines. Comment at: src/UnwindRegistersRestore.S:539 + lw$4, (4 * 4)($4) + +#elif defined(__mips_n64) .set pop Comment at: src/UnwindRegistersRestore.S:540 + +#elif defined(__mips_n64) + defined(__mips__) && _MIPS_SIM == _ABI64 Comment at: src/UnwindRegistersRestore.S:550 + .set noat +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_n646jumptoEv) + // r0 is zero See my comments on the o32 assembly. Comment at: src/UnwindRegistersSave.S:90 +#elif defined(__mips_o32) + See my previous comments about this preprocessor macro. Comment at: src/UnwindRegistersSave.S:101 +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set noreorder + # s0 - s7 Wrap this with .set push .set noat .set nomacro Comment at: src/UnwindRegistersSave.S:120 + sw$30, (4 * 30)($4) + +#elif defined(__mips_n64) and: .set pop Comment at: src/UnwindRegistersSave.S:121 + +#elif defined(__mips_n64) + Again, see my previous comments on this preprocessor define. Comment at: src/UnwindRegistersSave.S:132 +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set noreorder + # s0 - s7 Wrap this with .set push .set noat .set nomacro Comment at: src/UnwindRegistersSave.S:151 + sd$30, (8 * 30)($4) + # elif defined(__mips__) .set pop Comment at: src/libunwind.cpp:66 #elif defined(__mips__) # warning The MIPS architecture is not supported. #else The MIPS architecture is not supported with this ABI and environment! https://reviews.llvm.org/D38110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
