[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux abandoned this revision.
yroux added a comment.

All patches are now committed.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux marked an inline comment as done.
yroux added inline comments.



Comment at: llvm/lib/CodeGen/MachineOutliner.cpp:1159
+  MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
+  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);

yroux wrote:
> samparker wrote:
> > Looks like these should these be set in getRequiredProperties.
> Maybe @paquette can comment on that
Just to clarify, these are properties which are given to the created outlined 
functions and are required by the next passes (such as Constant Island), thus 
this is not part of getRequiredProperties


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux marked 2 inline comments as done.
yroux added a comment.

Thanks for the comments Sam,

Thumb1 is disabled in this version (see inline comment).

The is to bundle Machine Outliner to -Oz like it was done for AArch64, but here 
it just run when the flags are used (-moutline for clang or 
-enable-machine-outliner for llc) and not all the time.

Ok I'll try see if I can split it on the  outlining kind as you suggest.




Comment at: llvm/lib/CodeGen/MachineOutliner.cpp:1159
+  MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
+  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);

samparker wrote:
> Looks like these should these be set in getRequiredProperties.
Maybe @paquette can comment on that



Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5800-5802
+  // FIXME: Thumb1 outlining is not handled
+  if (MF.getInfo()->isThumb1OnlyFunction())
+return false;

Thumb1 is disabled here.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Sam Parker via Phabricator via cfe-commits]

samparker added a comment.

How about removing Thumb-1 support until it's properly handled? I also suggest 
that this gets broken down a bit too, by handling the different types of 
function call in different patches, like getting tail-call support in first or 
something. Also, is this currently set to run all the time and not just when 
optimising for size?




Comment at: llvm/lib/CodeGen/MachineOutliner.cpp:1159
+  MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
+  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);

Looks like these should these be set in getRequiredProperties.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux added a comment.

Ping


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux updated this revision to Diff 241188.
yroux added a comment.

Here is a new version, which disables ARM Low Overhead Loops pass when the 
Machine Outliner is enabled.


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Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  llvm/include/llvm/CodeGen/TargetPassConfig.h
  llvm/lib/CodeGen/MachineOutliner.cpp
  llvm/lib/CodeGen/TargetPassConfig.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMTargetMachine.cpp
  llvm/test/CodeGen/ARM/O3-pipeline.ll
  llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
  llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
  llvm/test/CodeGen/ARM/machine-outliner-tail.ll
  llvm/test/CodeGen/ARM/machine-outliner-thunk.ll
  llvm/test/CodeGen/ARM/machine-outliner.ll
  llvm/test/CodeGen/ARM/machine-outliner.mir

Index: llvm/test/CodeGen/ARM/machine-outliner.mir
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/machine-outliner.mir
@@ -0,0 +1,72 @@
+# RUN: llc -mtriple=arm-- -run-pass=machine-outliner -verify-machineinstrs \
+# RUN: %s -o - | FileCheck %s
+# RUN: llc -mtriple=thumbv7-- -run-pass=machine-outliner -verify-machineinstrs \
+# RUN: %s -o - | FileCheck %s
+
+--- |
+  define void @outline_1() #0 { ret void }
+  define void @outline_2() #0 { ret void }
+  define void @outline_3() #0 { ret void }
+  define void @dont_outline() { ret void }
+
+  attributes #0 = { minsize optsize }
+...
+---
+
+name:   outline_1
+tracksRegLiveness: true
+body: |
+  bb.0:
+; CHECK-LABEL: bb.0:
+; CHECK: OUTLINED
+liveins: $r2
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+BX_RET 14, $noreg
+...
+---
+
+name:   outline_2
+tracksRegLiveness: true
+body: |
+  bb.0:
+; CHECK-LABEL: bb.0:
+; CHECK: OUTLINED
+liveins: $r2
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+BX_RET 14, $noreg
+...
+---
+
+name:   outline_3
+tracksRegLiveness: true
+body: |
+  bb.0:
+; CHECK-LABEL: bb.0:
+; CHECK: OUTLINED
+liveins: $r2
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+BX_RET 14, $noreg
+...
+---
+
+name:   dont_outline
+tracksRegLiveness: true
+body: |
+  bb.0:
+; CHECK-LABEL: bb.0:
+; CHECK-NOT: BL
+liveins: $lr, $r2
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+$r2 = MOVi 1, 14, $noreg, $noreg
+BX_RET 14, $noreg
Index: llvm/test/CodeGen/ARM/machine-outliner.ll
===
--- /dev/null
+++ llvm/test/CodeGen/ARM/machine-outliner.ll
@@ -0,0 +1,135 @@
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=arm-- \
+; RUN: < %s | FileCheck %s --check-prefixes=CHECK,ARM
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=thumbv7-- \
+; RUN: < %s | FileCheck %s --check-prefixes=CHECK,THUMB
+; RUN: llc -verify-machineinstrs -enable-machine-outliner \
+; RUN: -enable-linkonceodr-outlining -mtriple=arm-- < %s | FileCheck %s \
+; RUN: --check-prefix=ODR
+; RUN: llc -verify-machineinstrs -enable-machine-outliner \
+; RUN: -enable-linkonceodr-outlining -mtriple=thumbv7-- < %s | FileCheck %s \
+; RUN: --check-prefix=ODR
+; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple=arm-- \
+; RUN: -stop-after=machine-outliner < %s | FileCheck %s \
+; RUN: --check-prefix=TARGET_FEATURES
+
+
+; Make sure that we inherit target features from functions and make sure we have
+; the right function attributes.
+; TARGET_FEATURES: define internal void @OUTLINED_FUNCTION_{{[0-9]+}}()
+; TARGET_FEATURES-SAME: #[[ATTR_NUM:[0-9]+]]
+; TARGET_FEATURES-DAG: attributes #[[ATTR_NUM]] = {
+; TARGET_FEATURES-SAME: minsize
+; TARGET_FEATURES-SAME: optsize
+; TARGET_FEATURES-SAME: "target-features"="+neon"
+
+define linkonce_odr void @fish() #0 {
+  ; CHECK-LABEL: fish:
+  ; CHECK-NOT: OUTLINED
+  ; ODR: [[OUTLINED:OUTLINED_FUNCTION_[0-9]+]]
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  %6 = alloca i32, align 4
+  store i32 1, i32* %1, align 4
+  store i32 2, i32* %2, align 4
+  store i32 3, i32* %3, align 4
+  store i32 4, i32* %4, align 4
+  store i32 5, i32* %5, align 4
+  store i32 6, i32* %6, align 4
+  ret void
+}
+
+define void @turtle() section "TURTLE,turtle" {
+  ; CHECK-LABEL: turtle:
+  ; ODR-LABEL: turtle:
+  ; CHECK-NOT: OUTLINED
+  %1 = alloca i32,

[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Sam Parker via Phabricator via cfe-commits]

samparker added a comment.

> Even if you only decrease the size you can have a distance increase due to 
> aligment constraints

Ah... thanks for raising this. I'll look into it.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux added a comment.

> ! In D57054#1811740 , @samparker 
> wrote:
>  Hmm, would it be possible to pass a bool to the pass which will control 
> whether liveness is updated? The other, suboptimal, option would be to not do 
> outlining when we have the LOB extension.

Ok maybe, at least in a first keeping the current pass order and disabling 
outliner when LOB is turned on is the thing to do, and we can move to more 
optimized version later.

> Yes, but LowOverheadLoops does not increase block size or change the CFG. We 
> mainly remove instructions but in the cases where we add instructions, 
> they're replacing pseudos with a size that represents the maximum number of 
> instructions that could be inserted.

Even if you only decrease the size you can have a distance increase due to 
aligment constraints, for instance if LOB removes some instructions before a 
load of a constant, then we have .align directive before a constant island, the 
load is moved upward and the distance between the load and the constant has 
increased


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Sam Parker via Phabricator via cfe-commits]

samparker added a comment.

> I can add liveness info into the outlined function, but we will need to do 
> the same on AArch64 even if is not necessary.

Hmm, would it be possible to pass a bool to the pass which will control whether 
liveness is updated? The other, suboptimal, option would be to not do outlining 
when we have the LOB extension.

> On the other hand isn't it the same for the ConstantIslands pass, I mean 
> isn't the size of blocks modified by the LowOverheadLoops pass which can 
> potentially break the accesses to some constant ?

Yes, but LowOverheadLoops does not increase block size or change the CFG. We 
mainly remove instructions but in the cases where we add instructions, they're 
replacing pseudos with a size that represents the maximum number of 
instructions that could be inserted.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux added a comment.

In D57054#1811486 , @samparker wrote:

> This, and the fact that LowOverheadLoops is dependent upon block sizes and 
> placement (I need to add a comment in the header on that pass). So, 
> ConstantIslands would have to guarantee not to change branch targets or 
> change the distance between blocks around the low-overhead loop constructs. I 
> think updating liveness information would be the easier option.


I can add liveness info into the outlined function, but we will need to do the 
same on AArch64 even if is not necessary.  On the other hand isn't it the same 
for the ConstantIslands pass, I mean isn't the size of blocks modified by the 
LowOverheadLoops pass which can potentially break the accesses to some constant 
? The experiment also shows that the optmization of cmp/beq into cbz made by 
ConstantIsland place is unleashed when the LowOverheadLoops is made before.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Sam Parker via Phabricator via cfe-commits]

samparker added a comment.

> It might be possible to rearrange Low Overhead Loops to run before 
> ConstantIslands, but you'd probably need to do more to make it work properly. 
> I don't think ConstantIslands knows how to handle the branches generated by 
> LowOverheadLoop.

This, and the fact that LowOverheadLoops is dependent upon block sizes and 
placement (I need to add a comment in the header on that pass). So, 
ConstantIslands would have to guarantee not to change branch targets or change 
the distance between blocks around the low-overhead loop constructs. I think 
updating liveness information would be the easier option.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux added a comment.

Ah right, let's wait for Sam comments/advises and I'll prepare a proper patch 
for that.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Sjoerd Meijer via Phabricator via cfe-commits]

SjoerdMeijer added a subscriber: samparker.
SjoerdMeijer added a comment.

Just a quick message, linking in @samparker, and I guess moving Low Overhead 
Loops to run before ConstantIslands could be problematic, but we can/should 
have a proper look tomorrow.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Eli Friedman via Phabricator via cfe-commits]

efriedma added a comment.

It might be possible to rearrange Low Overhead Loops to run before 
ConstantIslands, but you'd probably need to do more to make it work properly.  
I don't think ConstantIslands knows how to handle the branches generated by 
LowOverheadLoop.  If you think it's necessary, please split it into a separate 
patch with proper tests.


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[PATCH] D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM

[Yvan Roux via Phabricator via cfe-commits]

yroux updated this revision to Diff 236838.
yroux added a comment.
Herald added subscribers: cfe-commits, hiraditya.
Herald added a project: clang.

Hi,

here is an update for the Machine Outliner support on ARM targets.
It addresses the comments received on the initial version and is rebased on 
current trunk. 
Among the modifications needed by this rebase, this patch propose to move the 
ARM Low Overhead Loops pass before the Outliner and the Constant Island ones, 
because it requires the function to track the liveness (which is not the case 
of the outlined ones) and moving the Constant Island at the end seems more 
appropriate. If it is ok I'll split the patch and propose the move in a 
different review, but here is the whole thing such that you can test it.

Thanks


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Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  llvm/lib/CodeGen/MachineOutliner.cpp
  llvm/lib/CodeGen/ReachingDefAnalysis.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMTargetMachine.cpp
  llvm/test/CodeGen/ARM/O3-pipeline.ll
  llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
  llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
  llvm/test/CodeGen/ARM/machine-outliner-tail.ll
  llvm/test/CodeGen/ARM/machine-outliner-thunk.ll
  llvm/test/CodeGen/ARM/machine-outliner.ll
  llvm/test/CodeGen/ARM/machine-outliner.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll

Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
===
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
@@ -350,7 +350,7 @@
 ; CHECK-NEXT:push.w {r4, r5, r6, r7, r8, r9, lr}
 ; CHECK-NEXT:ldr.w r12, [sp, #28]
 ; CHECK-NEXT:cmp.w r12, #0
-; CHECK-NEXT:beq.w .LBB5_12
+; CHECK-NEXT:beq .LBB5_12
 ; CHECK-NEXT:  @ %bb.1: @ %for.body.lr.ph
 ; CHECK-NEXT:add.w r5, r3, r12, lsl #2
 ; CHECK-NEXT:add.w r6, r1, r12
@@ -647,7 +647,7 @@
 ; CHECK-NEXT:push.w {r4, r5, r6, r7, r8, r9, lr}
 ; CHECK-NEXT:ldr.w r12, [sp, #28]
 ; CHECK-NEXT:cmp.w r12, #0
-; CHECK-NEXT:beq.w .LBB7_12
+; CHECK-NEXT:beq .LBB7_12
 ; CHECK-NEXT:  @ %bb.1: @ %for.body.lr.ph
 ; CHECK-NEXT:add.w r5, r3, r12, lsl #2
 ; CHECK-NEXT:add.w r6, r1, r12
@@ -944,7 +944,7 @@
 ; CHECK-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, lr}
 ; CHECK-NEXT:ldr.w r12, [sp, #32]
 ; CHECK-NEXT:cmp.w r12, #0
-; CHECK-NEXT:beq.w .LBB9_11
+; CHECK-NEXT:beq .LBB9_11
 ; CHECK-NEXT:  @ %bb.1: @ %vector.memcheck
 ; CHECK-NEXT:add.w r4, r3, r12, lsl #2
 ; CHECK-NEXT:add.w r5, r1, r12, lsl #2
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
===
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
@@ -930,8 +930,7 @@
 ; CHECK-LABEL: float_int_int_mul:
 ; CHECK:   @ %bb.0: @ %entry
 ; CHECK-NEXT:push {r4, r5, r6, lr}
-; CHECK-NEXT:cmp r3, #0
-; CHECK-NEXT:beq .LBB4_8
+; CHECK-NEXT:cbz r3, .LBB4_8
 ; CHECK-NEXT:  @ %bb.1: @ %for.body.preheader
 ; CHECK-NEXT:cmp r3, #3
 ; CHECK-NEXT:bhi .LBB4_3
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
===
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
@@ -16,7 +16,7 @@
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
-; CHECK:   tBcc %bb.3
+; CHECK:   t2Bcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
 ; CHECK:   $lr = t2DLS renamable $lr
 ; CHECK: bb.2.while.body:
@@ -49,7 +49,7 @@
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
-; CHECK:   tBcc %bb.3
+; CHECK:   t2Bcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
 ; CHECK:   $lr = t2DLS renamable $lr
 ; CHECK: bb.2.while.body:
@@ -84,7 +84,7 @@
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
-; CHECK:   tBcc %bb.3
+; CHECK:   t2Bcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
 ; CHECK:   $lr = t2DLS renamable $lr
 ; CHECK: bb.2.while.body:
@@ -119,7 +119,7 @@
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
-; CHECK:   tBcc %bb.3
+; CHECK:   t2Bcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
 ; CHECK:   $lr = t2DLS renamable $lr