[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch
This revision was automatically updated to reflect the committed changes.
Closed by commit rL354897: [X86] AMD znver2 enablement (authored by ggopala,
committed by ).
Changed prior to commit:
https://reviews.llvm.org/D58343?vs=187389=188391#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D58343/new/
https://reviews.llvm.org/D58343
Files:
llvm/trunk/include/llvm/Support/X86TargetParser.def
llvm/trunk/lib/Support/Host.cpp
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/test/CodeGen/X86/cpus-amd.ll
llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll
llvm/trunk/test/CodeGen/X86/slow-unaligned-mem.ll
llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll
Index: llvm/trunk/include/llvm/Support/X86TargetParser.def
===
--- llvm/trunk/include/llvm/Support/X86TargetParser.def
+++ llvm/trunk/include/llvm/Support/X86TargetParser.def
@@ -98,6 +98,7 @@
X86_CPU_SUBTYPE_COMPAT("cannonlake", INTEL_COREI7_CANNONLAKE, "cannonlake")
X86_CPU_SUBTYPE_COMPAT("icelake-client", INTEL_COREI7_ICELAKE_CLIENT, "icelake-client")
X86_CPU_SUBTYPE_COMPAT("icelake-server", INTEL_COREI7_ICELAKE_SERVER, "icelake-server")
+X86_CPU_SUBTYPE_COMPAT("znver2", AMDFAM17H_ZNVER2,"znver2")
// Entries below this are not in libgcc/compiler-rt.
X86_CPU_SUBTYPE ("core2", INTEL_CORE2_65)
X86_CPU_SUBTYPE ("penryn", INTEL_CORE2_45)
Index: llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll
===
--- llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll
+++ llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll
@@ -13,8 +13,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s
-; Verify that for the X86_64 processors that are known to have poor latency
+; Verify that for the X86_64 processors that are known to have poor latency
; double precision shift instructions we do not generate 'shld' or 'shrd'
; instructions.
@@ -25,7 +26,7 @@
define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
entry:
-; CHECK-NOT: shld
+; CHECK-NOT: shld
%sh_prom = zext i32 %c to i64
%shl = shl i64 %a, %sh_prom
%sub = sub nsw i32 64, %c
Index: llvm/trunk/test/CodeGen/X86/cpus-amd.ll
===
--- llvm/trunk/test/CodeGen/X86/cpus-amd.ll
+++ llvm/trunk/test/CodeGen/X86/cpus-amd.ll
@@ -26,6 +26,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
define void @foo() {
ret void
Index: llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll
===
--- llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll
+++ llvm/trunk/test/CodeGen/X86/lzcnt-zext-cmp.ll
@@ -5,6 +5,8 @@
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver2 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
; Test one 32-bit input, output is 32-bit, no transformations expected.
define i32 @test_zext_cmp0(i32 %a) {
Index: llvm/trunk/test/CodeGen/X86/slow-unaligned-mem.ll
===
--- llvm/trunk/test/CodeGen/X86/slow-unaligned-mem.ll
+++ llvm/trunk/test/CodeGen/X86/slow-unaligned-mem.ll
@@ -47,6 +47,7 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver32>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver42>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver12>&1 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver22>&1 | FileCheck %s --check-prefix=FAST
; Other chips with slow unaligned memory accesses
[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch
craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/ https://reviews.llvm.org/D58343 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch
GGanesh updated this revision to Diff 187389.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D58343/new/
https://reviews.llvm.org/D58343
Files:
include/llvm/Support/X86TargetParser.def
lib/Support/Host.cpp
lib/Target/X86/X86.td
test/CodeGen/X86/cpus-amd.ll
test/CodeGen/X86/lzcnt-zext-cmp.ll
test/CodeGen/X86/slow-unaligned-mem.ll
test/CodeGen/X86/x86-64-double-shifts-var.ll
Index: test/CodeGen/X86/x86-64-double-shifts-var.ll
===
--- test/CodeGen/X86/x86-64-double-shifts-var.ll
+++ test/CodeGen/X86/x86-64-double-shifts-var.ll
@@ -13,8 +13,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s
-; Verify that for the X86_64 processors that are known to have poor latency
+; Verify that for the X86_64 processors that are known to have poor latency
; double precision shift instructions we do not generate 'shld' or 'shrd'
; instructions.
@@ -25,7 +26,7 @@
define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
entry:
-; CHECK-NOT: shld
+; CHECK-NOT: shld
%sh_prom = zext i32 %c to i64
%shl = shl i64 %a, %sh_prom
%sub = sub nsw i32 64, %c
Index: test/CodeGen/X86/slow-unaligned-mem.ll
===
--- test/CodeGen/X86/slow-unaligned-mem.ll
+++ test/CodeGen/X86/slow-unaligned-mem.ll
@@ -47,6 +47,7 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver32>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver42>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver12>&1 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver22>&1 | FileCheck %s --check-prefix=FAST
; Other chips with slow unaligned memory accesses
Index: test/CodeGen/X86/lzcnt-zext-cmp.ll
===
--- test/CodeGen/X86/lzcnt-zext-cmp.ll
+++ test/CodeGen/X86/lzcnt-zext-cmp.ll
@@ -5,6 +5,8 @@
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver2 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
; Test one 32-bit input, output is 32-bit, no transformations expected.
define i32 @test_zext_cmp0(i32 %a) {
Index: test/CodeGen/X86/cpus-amd.ll
===
--- test/CodeGen/X86/cpus-amd.ll
+++ test/CodeGen/X86/cpus-amd.ll
@@ -26,6 +26,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
define void @foo() {
ret void
Index: lib/Target/X86/X86.td
===
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -1144,8 +1144,8 @@
FeatureMacroFusion
]>;
-// Znver1
-def: ProcessorModel<"znver1", Znver1Model, [
+// AMD Zen Processors common ISAs
+def ZNFeatures : ProcessorFeatures<[], [
FeatureADX,
FeatureAES,
FeatureAVX2,
@@ -1184,6 +1184,19 @@
FeatureXSAVEOPT,
FeatureXSAVES]>;
+class Znver1Proc : ProcModel;
+def : Znver1Proc<"znver1">;
+
+class Znver2Proc : ProcModel;
+def : Znver2Proc<"znver2">;
+
def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
Index: lib/Support/Host.cpp
===
--- lib/Support/Host.cpp
+++ lib/Support/Host.cpp
@@ -916,7 +916,14 @@
break; // "btver2"
case 23:
*Type = X86::AMDFAM17H;
-*Subtype = X86::AMDFAM17H_ZNVER1;
+if (Model >= 0x30 && Model <= 0x3f) {
+ *Subtype = X86::AMDFAM17H_ZNVER2;
+ break; // "znver2"; 30h-3fh: Zen2
+}
+if (Model <= 0x0f) {
+ *Subtype =
[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch
GGanesh updated this revision to Diff 187386.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D58343/new/
https://reviews.llvm.org/D58343
Files:
include/llvm/Support/X86TargetParser.def
lib/Support/Host.cpp
lib/Target/X86/X86.td
test/CodeGen/X86/cpus-amd.ll
test/CodeGen/X86/lzcnt-zext-cmp.ll
test/CodeGen/X86/slow-unaligned-mem.ll
test/CodeGen/X86/x86-64-double-shifts-var.ll
Index: test/CodeGen/X86/x86-64-double-shifts-var.ll
===
--- test/CodeGen/X86/x86-64-double-shifts-var.ll
+++ test/CodeGen/X86/x86-64-double-shifts-var.ll
@@ -13,8 +13,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s
-; Verify that for the X86_64 processors that are known to have poor latency
+; Verify that for the X86_64 processors that are known to have poor latency
; double precision shift instructions we do not generate 'shld' or 'shrd'
; instructions.
@@ -25,7 +26,7 @@
define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
entry:
-; CHECK-NOT: shld
+; CHECK-NOT: shld
%sh_prom = zext i32 %c to i64
%shl = shl i64 %a, %sh_prom
%sub = sub nsw i32 64, %c
Index: test/CodeGen/X86/slow-unaligned-mem.ll
===
--- test/CodeGen/X86/slow-unaligned-mem.ll
+++ test/CodeGen/X86/slow-unaligned-mem.ll
@@ -47,6 +47,7 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver32>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver42>&1 | FileCheck %s --check-prefix=FAST
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver12>&1 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver22>&1 | FileCheck %s --check-prefix=FAST
; Other chips with slow unaligned memory accesses
Index: test/CodeGen/X86/lzcnt-zext-cmp.ll
===
--- test/CodeGen/X86/lzcnt-zext-cmp.ll
+++ test/CodeGen/X86/lzcnt-zext-cmp.ll
@@ -5,6 +5,8 @@
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver2 | FileCheck --check-prefix=ALL --check-prefix=FASTLZCNT %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=ALL --check-prefix=NOFASTLZCNT %s
; Test one 32-bit input, output is 32-bit, no transformations expected.
define i32 @test_zext_cmp0(i32 %a) {
Index: test/CodeGen/X86/cpus-amd.ll
===
--- test/CodeGen/X86/cpus-amd.ll
+++ test/CodeGen/X86/cpus-amd.ll
@@ -26,6 +26,7 @@
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
define void @foo() {
ret void
Index: lib/Target/X86/X86.td
===
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -1144,15 +1144,14 @@
FeatureMacroFusion
]>;
-// Znver1
-def: ProcessorModel<"znver1", Znver1Model, [
+// AMD Zen Processors common ISAs
+def ZNFeatures : ProcessorFeatures<[], [
FeatureADX,
FeatureAES,
FeatureAVX2,
FeatureBMI,
FeatureBMI2,
FeatureCLFLUSHOPT,
- FeatureCLZERO,
FeatureCMOV,
Feature64Bit,
FeatureCMPXCHG16B,
@@ -1184,6 +1183,21 @@
FeatureXSAVEOPT,
FeatureXSAVES]>;
+class Znver1Proc : ProcModel;
+def : Znver1Proc<"znver1">;
+
+class Znver2Proc : ProcModel;
+def : Znver2Proc<"znver2">;
+
def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
Index: lib/Support/Host.cpp
===
--- lib/Support/Host.cpp
+++ lib/Support/Host.cpp
@@ -916,7 +916,14 @@
break; // "btver2"
case 23:
*Type = X86::AMDFAM17H;
-*Subtype = X86::AMDFAM17H_ZNVER1;
+if (Model >= 0x30 && Model <= 0x3f) {
+
[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch
craig.topper added a comment. I think you uploaded the clang patch into the llvm review? Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/ https://reviews.llvm.org/D58343 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch
GGanesh updated this revision to Diff 187340. GGanesh added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Addressed the comments from Craig Topper Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D58343/new/ https://reviews.llvm.org/D58343 Files: include/clang/Basic/X86Target.def lib/Basic/Targets/X86.cpp test/CodeGen/target-builtin-noerror.c test/Driver/x86-march.c test/Frontend/x86-target-cpu.c test/Misc/target-invalid-cpu-note.c test/Preprocessor/predefined-arch-macros.c Index: test/Preprocessor/predefined-arch-macros.c === --- test/Preprocessor/predefined-arch-macros.c +++ test/Preprocessor/predefined-arch-macros.c @@ -2676,6 +2676,100 @@ // CHECK_ZNVER1_M64: #define __znver1 1 // CHECK_ZNVER1_M64: #define __znver1__ 1 +// RUN: %clang -march=znver2 -m32 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER2_M32 +// CHECK_ZNVER2_M32-NOT: #define __3dNOW_A__ 1 +// CHECK_ZNVER2_M32-NOT: #define __3dNOW__ 1 +// CHECK_ZNVER2_M32: #define __ADX__ 1 +// CHECK_ZNVER2_M32: #define __AES__ 1 +// CHECK_ZNVER2_M32: #define __AVX2__ 1 +// CHECK_ZNVER2_M32: #define __AVX__ 1 +// CHECK_ZNVER2_M32: #define __BMI2__ 1 +// CHECK_ZNVER2_M32: #define __BMI__ 1 +// CHECK_ZNVER2_M32: #define __CLFLUSHOPT__ 1 +// CHECK_ZNVER2_M32: #define __CLWB__ 1 +// CHECK_ZNVER2_M32: #define __CLZERO__ 1 +// CHECK_ZNVER2_M32: #define __F16C__ 1 +// CHECK_ZNVER2_M32: #define __FMA__ 1 +// CHECK_ZNVER2_M32: #define __FSGSBASE__ 1 +// CHECK_ZNVER2_M32: #define __LZCNT__ 1 +// CHECK_ZNVER2_M32: #define __MMX__ 1 +// CHECK_ZNVER2_M32: #define __PCLMUL__ 1 +// CHECK_ZNVER2_M32: #define __POPCNT__ 1 +// CHECK_ZNVER2_M32: #define __PRFCHW__ 1 +// CHECK_ZNVER2_M32: #define __RDPID__ 1 +// CHECK_ZNVER2_M32: #define __RDRND__ 1 +// CHECK_ZNVER2_M32: #define __RDSEED__ 1 +// CHECK_ZNVER2_M32: #define __SHA__ 1 +// CHECK_ZNVER2_M32: #define __SSE2_MATH__ 1 +// CHECK_ZNVER2_M32: #define __SSE2__ 1 +// CHECK_ZNVER2_M32: #define __SSE3__ 1 +// CHECK_ZNVER2_M32: #define __SSE4A__ 1 +// CHECK_ZNVER2_M32: #define __SSE4_1__ 1 +// CHECK_ZNVER2_M32: #define __SSE4_2__ 1 +// CHECK_ZNVER2_M32: #define __SSE_MATH__ 1 +// CHECK_ZNVER2_M32: #define __SSE__ 1 +// CHECK_ZNVER2_M32: #define __SSSE3__ 1 +// CHECK_ZNVER2_M32: #define __WBNOINVD__ 1 +// CHECK_ZNVER2_M32: #define __XSAVEC__ 1 +// CHECK_ZNVER2_M32: #define __XSAVEOPT__ 1 +// CHECK_ZNVER2_M32: #define __XSAVES__ 1 +// CHECK_ZNVER2_M32: #define __XSAVE__ 1 +// CHECK_ZNVER2_M32: #define __i386 1 +// CHECK_ZNVER2_M32: #define __i386__ 1 +// CHECK_ZNVER2_M32: #define __tune_znver2__ 1 +// CHECK_ZNVER2_M32: #define __znver2 1 +// CHECK_ZNVER2_M32: #define __znver2__ 1 + +// RUN: %clang -march=znver2 -m64 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER2_M64 +// CHECK_ZNVER2_M64-NOT: #define __3dNOW_A__ 1 +// CHECK_ZNVER2_M64-NOT: #define __3dNOW__ 1 +// CHECK_ZNVER2_M64: #define __ADX__ 1 +// CHECK_ZNVER2_M64: #define __AES__ 1 +// CHECK_ZNVER2_M64: #define __AVX2__ 1 +// CHECK_ZNVER2_M64: #define __AVX__ 1 +// CHECK_ZNVER2_M64: #define __BMI2__ 1 +// CHECK_ZNVER2_M64: #define __BMI__ 1 +// CHECK_ZNVER2_M64: #define __CLFLUSHOPT__ 1 +// CHECK_ZNVER2_M64: #define __CLWB__ 1 +// CHECK_ZNVER2_M64: #define __CLZERO__ 1 +// CHECK_ZNVER2_M64: #define __F16C__ 1 +// CHECK_ZNVER2_M64: #define __FMA__ 1 +// CHECK_ZNVER2_M64: #define __FSGSBASE__ 1 +// CHECK_ZNVER2_M64: #define __LZCNT__ 1 +// CHECK_ZNVER2_M64: #define __MMX__ 1 +// CHECK_ZNVER2_M64: #define __PCLMUL__ 1 +// CHECK_ZNVER2_M64: #define __POPCNT__ 1 +// CHECK_ZNVER2_M64: #define __PRFCHW__ 1 +// CHECK_ZNVER2_M64: #define __RDPID__ 1 +// CHECK_ZNVER2_M64: #define __RDRND__ 1 +// CHECK_ZNVER2_M64: #define __RDSEED__ 1 +// CHECK_ZNVER2_M64: #define __SHA__ 1 +// CHECK_ZNVER2_M64: #define __SSE2_MATH__ 1 +// CHECK_ZNVER2_M64: #define __SSE2__ 1 +// CHECK_ZNVER2_M64: #define __SSE3__ 1 +// CHECK_ZNVER2_M64: #define __SSE4A__ 1 +// CHECK_ZNVER2_M64: #define __SSE4_1__ 1 +// CHECK_ZNVER2_M64: #define __SSE4_2__ 1 +// CHECK_ZNVER2_M64: #define __SSE_MATH__ 1 +// CHECK_ZNVER2_M64: #define __SSE__ 1 +// CHECK_ZNVER2_M64: #define __SSSE3__ 1 +// CHECK_ZNVER2_M64: #define __WBNOINVD__ 1 +// CHECK_ZNVER2_M64: #define __XSAVEC__ 1 +// CHECK_ZNVER2_M64: #define __XSAVEOPT__ 1 +// CHECK_ZNVER2_M64: #define __XSAVES__ 1 +// CHECK_ZNVER2_M64: #define __XSAVE__ 1 +// CHECK_ZNVER2_M64: #define __amd64 1 +// CHECK_ZNVER2_M64: #define __amd64__ 1 +// CHECK_ZNVER2_M64: #define __tune_znver2__ 1 +// CHECK_ZNVER2_M64: #define __x86_64 1 +// CHECK_ZNVER2_M64: #define __x86_64__ 1 +// CHECK_ZNVER2_M64: #define __znver2 1 +// CHECK_ZNVER2_M64: #define __znver2__ 1 + // End X86/GCC/Linux tests -- // Begin PPC/GCC/Linux tests Index:
