subject:"\[PATCH\] D62368\: Add support for Hygon Dhyana processor"

[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-28 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke marked an inline comment as done.
fanjinke added inline comments.



Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;

craig.topper wrote:
> fanjinke wrote:
> > craig.topper wrote:
> > > What's the rationale for the vendor check here anyway? Why isn't the bit 
> > > in ecx sufficient?
> > Using the cpuid instruction to get the vendor id will return the ASCII code 
> > of the vendor id, which is stored in the ebx,ecx,edx registers.
> > The ASCII code in the Hygon CPU is "HygonGenuine",  the ecx = "eniu".
> > For better differentiation from other cpus in the future,  by following 
> > AMD/Intel way, we use full ASCII code to identify Hygon CPU.
> > 
> Sorry, my question was about why this was restricted to Intel/AMD in the 
> first place. Why should this code need to be updated every time a new vendor 
> comes along? Why isn’t checking for sse4.2 regardless of vendor sufficient.
For this question, original author[1] may be more appropriate to reply.
From CPU specification, Bit20 of CPUID Fn_0001_ecx is SSE42 on Intel, AMD, 
and Hygon CPUs, but we are not sure that this is true for all x86 vendors.

Cryptoad, Any comments?

[1]: https://reviews.llvm.org/D40322


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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-27 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added inline comments.



Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;

fanjinke wrote:
> craig.topper wrote:
> > What's the rationale for the vendor check here anyway? Why isn't the bit in 
> > ecx sufficient?
> Using the cpuid instruction to get the vendor id will return the ASCII code 
> of the vendor id, which is stored in the ebx,ecx,edx registers.
> The ASCII code in the Hygon CPU is "HygonGenuine",  the ecx = "eniu".
> For better differentiation from other cpus in the future,  by following 
> AMD/Intel way, we use full ASCII code to identify Hygon CPU.
> 
Sorry, my question was about why this was restricted to Intel/AMD in the first 
place. Why should this code need to be updated every time a new vendor comes 
along? Why isn’t checking for sse4.2 regardless of vendor sufficient.


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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-27 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke marked an inline comment as done.
fanjinke added inline comments.



Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;

craig.topper wrote:
> What's the rationale for the vendor check here anyway? Why isn't the bit in 
> ecx sufficient?
Using the cpuid instruction to get the vendor id will return the ASCII code of 
the vendor id, which is stored in the ebx,ecx,edx registers.
The ASCII code in the Hygon CPU is "HygonGenuine",  the ecx = "eniu".
For better differentiation from other cpus in the future,  by following 
AMD/Intel way, we use full ASCII code to identify Hygon CPU.



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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-26 Thread Craig Topper via Phabricator via cfe-commits

craig.topper added inline comments.



Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;

What's the rationale for the vendor check here anyway? Why isn't the bit in ecx 
sufficient?


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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-22 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke added a comment.

Hi Cryptoad,

  Thank you so much for your comment. I will divide it into two patches 
according to your suggestion.

Best regards.


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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-22 Thread Kostya Kortchinsky via Phabricator via cfe-commits

cryptoad added a comment.

Hey,

`clang/lib/Headers/cpuid.h` would have to be in its own CL that would have to 
be sent separately from the Scudo one.
It would have to be reviewed by clang people and likely some tests added.

Once this is done and landed, then the Scudo part can happen.

Thanks!


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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-21 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke updated this revision to Diff 259150.
fanjinke edited the summary of this revision.
fanjinke added a comment.

1，Update patch base on lastest commit e90fb82f0f760703c14eafbad96c08b6019a2f0f 
.
2，Format the patch with “git clang-format-6.0 HEAD~1“.


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Files:
  clang/lib/Headers/cpuid.h
  compiler-rt/lib/scudo/scudo_utils.cpp
  compiler-rt/lib/scudo/standalone/checksum.cpp


Index: compiler-rt/lib/scudo/standalone/checksum.cpp
===
--- compiler-rt/lib/scudo/standalone/checksum.cpp
+++ compiler-rt/lib/scudo/standalone/checksum.cpp
@@ -31,6 +31,13 @@
 #define bit_SSE4_2 bit_SSE42 // clang and gcc have different defines.
 #endif
 
+#ifndef signature_HYGON_ebx // They are not defined in the gcc.
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
+#endif
+
 bool hasHardwareCRC32() {
   u32 Eax, Ebx = 0, Ecx = 0, Edx = 0;
   __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
@@ -39,7 +46,10 @@
(Ecx == signature_INTEL_ecx);
   const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) 
&&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) &&
+   (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: compiler-rt/lib/scudo/scudo_utils.cpp
===
--- compiler-rt/lib/scudo/scudo_utils.cpp
+++ compiler-rt/lib/scudo/scudo_utils.cpp
@@ -62,6 +62,14 @@
 # ifndef bit_SSE4_2
 #  define bit_SSE4_2 bit_SSE42  // clang and gcc have different defines.
 # endif
+
+#ifndef signature_HYGON_ebx // They are not defined in the gcc.
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
+#endif
+
 bool hasHardwareCRC32() {
   u32 Eax, Ebx, Ecx, Edx;
   __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
@@ -71,7 +79,10 @@
   const bool IsAMD = (Ebx == signature_AMD_ebx) &&
  (Edx == signature_AMD_edx) &&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) &&
+   (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: clang/lib/Headers/cpuid.h
===
--- clang/lib/Headers/cpuid.h
+++ clang/lib/Headers/cpuid.h
@@ -24,6 +24,10 @@
 #define signature_CYRIX_ebx 0x69727943
 #define signature_CYRIX_edx 0x736e4978
 #define signature_CYRIX_ecx 0x64616574
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
 /* INTEL:   "GenuineIntel" */
 #define signature_INTEL_ebx 0x756e6547
 #define signature_INTEL_edx 0x49656e69


Index: compiler-rt/lib/scudo/standalone/checksum.cpp
===
--- compiler-rt/lib/scudo/standalone/checksum.cpp
+++ compiler-rt/lib/scudo/standalone/checksum.cpp
@@ -31,6 +31,13 @@
 #define bit_SSE4_2 bit_SSE42 // clang and gcc have different defines.
 #endif
 
+#ifndef signature_HYGON_ebx // They are not defined in the gcc.
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
+#endif
+
 bool hasHardwareCRC32() {
   u32 Eax, Ebx = 0, Ecx = 0, Edx = 0;
   __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
@@ -39,7 +46,10 @@
(Ecx == signature_INTEL_ecx);
   const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) &&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) &&
+   (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: compiler-rt/lib/scudo/scudo_utils.cpp
===
--- compiler-rt/lib/scudo/scudo_utils.cpp
+++ compiler-rt/lib/scudo/scudo_utils.cpp
@@ -62,6 +62,14 @@
 # ifndef bit_SSE4_2
 #  define bit_SSE4_2 bit_SSE42  // clang and gcc have different defines.
 # endif
+
+#i

[PATCH] D62368: Add support for Hygon Dhyana processor

2020-04-07 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke added a comment.

Hi cryptoad，

  Any suggestions?


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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-03-17 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke edited reviewers, added: cryptoad; removed: 01alchemist, 4tXJ7f.
fanjinke added a comment.

Hi Cryptoad,

  Thanks for your reminds, and I get the points now. Then updated the scudo 
part of the patch.
  After patch update，compiler-rt can be successfully compiled using gcc.

Thanks again!


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[PATCH] D62368: Add support for Hygon Dhyana processor

2020-03-17 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke updated this revision to Diff 250996.
fanjinke added a comment.

Results of "make check":

  Testing Time: 1153.40s
Expected Passes: 36042
Expected Failures  : 163
Unsupported Tests  : 340
  [100%] Built target check-llvm
  Scanning dependencies of target check
  [100%] Built target check

The compiler-rt directory can be compiled using gcc.

ChangeLog:
v2:

- Updated the scudo part of the patch,  Thanks Cryptoad!


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Files:
  clang/lib/Headers/cpuid.h
  compiler-rt/lib/scudo/scudo_utils.cpp
  compiler-rt/lib/scudo/standalone/checksum.cpp


Index: compiler-rt/lib/scudo/standalone/checksum.cpp
===
--- compiler-rt/lib/scudo/standalone/checksum.cpp
+++ compiler-rt/lib/scudo/standalone/checksum.cpp
@@ -31,6 +31,13 @@
 #define bit_SSE4_2 bit_SSE42 // clang and gcc have different defines.
 #endif
 
+# ifndef signature_HYGON_ebx   // They are not defined in the gcc.
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
+# endif
+
 bool hasHardwareCRC32() {
   u32 Eax, Ebx = 0, Ecx = 0, Edx = 0;
   __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
@@ -39,7 +46,9 @@
(Ecx == signature_INTEL_ecx);
   const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) 
&&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) && (Edx == 
signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: compiler-rt/lib/scudo/scudo_utils.cpp
===
--- compiler-rt/lib/scudo/scudo_utils.cpp
+++ compiler-rt/lib/scudo/scudo_utils.cpp
@@ -62,6 +62,14 @@
 # ifndef bit_SSE4_2
 #  define bit_SSE4_2 bit_SSE42  // clang and gcc have different defines.
 # endif
+
+# ifndef signature_HYGON_ebx   // They are not defined in the gcc.
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
+# endif
+
 bool hasHardwareCRC32() {
   u32 Eax, Ebx, Ecx, Edx;
   __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
@@ -71,7 +79,10 @@
   const bool IsAMD = (Ebx == signature_AMD_ebx) &&
  (Edx == signature_AMD_edx) &&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) &&
+   (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: clang/lib/Headers/cpuid.h
===
--- clang/lib/Headers/cpuid.h
+++ clang/lib/Headers/cpuid.h
@@ -24,6 +24,10 @@
 #define signature_CYRIX_ebx 0x69727943
 #define signature_CYRIX_edx 0x736e4978
 #define signature_CYRIX_ecx 0x64616574
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
 /* INTEL:   "GenuineIntel" */
 #define signature_INTEL_ebx 0x756e6547
 #define signature_INTEL_edx 0x49656e69


Index: compiler-rt/lib/scudo/standalone/checksum.cpp
===
--- compiler-rt/lib/scudo/standalone/checksum.cpp
+++ compiler-rt/lib/scudo/standalone/checksum.cpp
@@ -31,6 +31,13 @@
 #define bit_SSE4_2 bit_SSE42 // clang and gcc have different defines.
 #endif
 
+# ifndef signature_HYGON_ebx	// They are not defined in the gcc.
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
+# endif
+
 bool hasHardwareCRC32() {
   u32 Eax, Ebx = 0, Ecx = 0, Edx = 0;
   __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx);
@@ -39,7 +46,9 @@
(Ecx == signature_INTEL_ecx);
   const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) &&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) && (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: compiler-rt/lib/scudo/scudo_utils.cpp
===
--- compiler-rt/lib/scudo/scudo_utils.cpp
+++ compiler-rt/lib/scudo/scudo_utils.cpp
@@ -62,6 +62,14 @@
 # ifndef bit_SSE4_2
 #  define bit_SSE4_2 bit_SSE42  // clang and gcc

[PATCH] D62368: Add support for Hygon Dhyana processor

2019-06-20 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke added reviewers: 01alchemist, 4tXJ7f.
fanjinke added a comment.

Hi,

  Please help with the patch reveiw.

Hi cryptoad,
@cryptoad  IS there anything incorrectly?


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[PATCH] D62368: Add support for Hygon Dhyana processor

2019-05-24 Thread Kostya Kortchinsky via Phabricator via cfe-commits

cryptoad added a comment.

Regarding the Scudo side of the patch: the code has to be able to compile with 
gcc as well, and not necessarily the latest version.
This won't compile on systems without a `signature_HYGON_*`.


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[PATCH] D62368: Add support for Hygon Dhyana processor

2019-05-24 Thread Jinke Fan via Phabricator via cfe-commits

fanjinke created this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

This patch adds vendor id detection for Hygon Dhyana CPUs.

More details can be found on:

  
http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.pu...@hygon.cn

Result of "make check":
[100%] Running the LLVM regression tests
Testing Time: 671.13s

  Expected Passes: 30229
  Expected Failures  : 149
  Unsupported Tests  : 673

[100%] Built target check-llvm
Scanning dependencies of target check
[100%] Built target check


Repository:
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Files:
  clang/lib/Headers/cpuid.h
  compiler-rt/lib/scudo/scudo_utils.cpp
  compiler-rt/lib/scudo/standalone/checksum.cc


Index: compiler-rt/lib/scudo/standalone/checksum.cc
===
--- compiler-rt/lib/scudo/standalone/checksum.cc
+++ compiler-rt/lib/scudo/standalone/checksum.cc
@@ -39,7 +39,9 @@
(Ecx == signature_INTEL_ecx);
   const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) 
&&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) && (Edx == 
signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: compiler-rt/lib/scudo/scudo_utils.cpp
===
--- compiler-rt/lib/scudo/scudo_utils.cpp
+++ compiler-rt/lib/scudo/scudo_utils.cpp
@@ -71,7 +71,10 @@
   const bool IsAMD = (Ebx == signature_AMD_ebx) &&
  (Edx == signature_AMD_edx) &&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) &&
+   (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: clang/lib/Headers/cpuid.h
===
--- clang/lib/Headers/cpuid.h
+++ clang/lib/Headers/cpuid.h
@@ -24,6 +24,10 @@
 #define signature_CYRIX_ebx 0x69727943
 #define signature_CYRIX_edx 0x736e4978
 #define signature_CYRIX_ecx 0x64616574
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
 /* INTEL:   "GenuineIntel" */
 #define signature_INTEL_ebx 0x756e6547
 #define signature_INTEL_edx 0x49656e69


Index: compiler-rt/lib/scudo/standalone/checksum.cc
===
--- compiler-rt/lib/scudo/standalone/checksum.cc
+++ compiler-rt/lib/scudo/standalone/checksum.cc
@@ -39,7 +39,9 @@
(Ecx == signature_INTEL_ecx);
   const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) &&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) && (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: compiler-rt/lib/scudo/scudo_utils.cpp
===
--- compiler-rt/lib/scudo/scudo_utils.cpp
+++ compiler-rt/lib/scudo/scudo_utils.cpp
@@ -71,7 +71,10 @@
   const bool IsAMD = (Ebx == signature_AMD_ebx) &&
  (Edx == signature_AMD_edx) &&
  (Ecx == signature_AMD_ecx);
-  if (!IsIntel && !IsAMD)
+  const bool IsHygon = (Ebx == signature_HYGON_ebx) &&
+   (Edx == signature_HYGON_edx) &&
+   (Ecx == signature_HYGON_ecx);
+  if (!IsIntel && !IsAMD && !IsHygon)
 return false;
   __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx);
   return !!(Ecx & bit_SSE4_2);
Index: clang/lib/Headers/cpuid.h
===
--- clang/lib/Headers/cpuid.h
+++ clang/lib/Headers/cpuid.h
@@ -24,6 +24,10 @@
 #define signature_CYRIX_ebx 0x69727943
 #define signature_CYRIX_edx 0x736e4978
 #define signature_CYRIX_ecx 0x64616574
+/* HYGON:   "HygonGenuine" */
+#define signature_HYGON_ebx 0x6f677948
+#define signature_HYGON_edx 0x6e65476e
+#define signature_HYGON_ecx 0x656e6975
 /* INTEL:   "GenuineIntel" */
 #define signature_INTEL_ebx 0x756e6547
 #define signature_INTEL_edx 0x49656e69
___
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[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

[PATCH] D62368: Add support for Hygon Dhyana processor

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