[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Amy Kwan via Phabricator via cfe-commits]

amyk marked 2 inline comments as done.
amyk added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:79
+vector signed int test_vec_dive_si(void) {
+  // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32>
+  // CHECK-NEXT: ret <4 x i32>

lei wrote:
> why does the ck stops matching at the first param?  Shouldn't we check the 
> remaining param type and number of param are correct as well?
Yes, thanks for pointing that out. Will be fixing the CHECKs.



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:854
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vdivesw v4i32:$vA, v4i32:$vB))]>;
   def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),

lei wrote:
> nit: indent to match up with `v4i32` on the previous line.
I will update with the proper indentation. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82609/new/

https://reviews.llvm.org/D82609



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:79
+vector signed int test_vec_dive_si(void) {
+  // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32>
+  // CHECK-NEXT: ret <4 x i32>

why does the ck stops matching at the first param?  Shouldn't we check the 
remaining param type and number of param are correct as well?



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:854
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vdivesw v4i32:$vA, v4i32:$vB))]>;
   def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),

nit: indent to match up with `v4i32` on the previous line.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82609/new/

https://reviews.llvm.org/D82609



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Amy Kwan via Phabricator via cfe-commits]

amyk updated this revision to Diff 274680.
amyk edited the summary of this revision.
amyk added a parent revision: D82576: [PowerPC][Power10] Implement low-order 
Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests.
amyk added a comment.

Rebase patch, remove MC tests from this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82609/new/

https://reviews.llvm.org/D82609

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
  llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll

Index: llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
===
--- llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
+++ llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
@@ -73,3 +73,49 @@
   %tr = trunc <4 x i64> %shr to <4 x i32>
   ret <4 x i32> %tr
 }
+
+; Test the vector multiply high intrinsics.
+declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.ppc.altivec.vmulhud(<2 x i64>, <2 x i64>)
+
+define <4 x i32> @test_vmulhsw_intrinsic(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhsw_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhsw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %mulh
+}
+
+define <4 x i32> @test_vmulhuw_intrinsic(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhuw_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhuw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %mulh
+}
+
+define <2 x i64> @test_vmulhsd_intrinsic(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhsd_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhsd v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %mulh
+}
+
+define <2 x i64> @test_vmulhud_intrinsic(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhud_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhud v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <2 x i64> @llvm.ppc.altivec.vmulhud(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %mulh
+}
Index: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
===
--- llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
+++ llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
@@ -46,3 +46,49 @@
   %div = sdiv <4 x i32> %a, %b
   ret <4 x i32> %div
 }
+
+; Test the vector divide extended intrinsics.
+declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64>, <2 x i64>)
+
+define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vdivesw:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vdivesw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %div = tail call <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %div
+}
+
+define <4 x i32> @test_vdiveuw(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vdiveuw:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vdiveuw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %div = tail call <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %div
+}
+
+define <2 x i64> @test_vdivesd(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vdivesd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vdivesd v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %div = tail call <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %div
+}
+
+define <2 x i64> @test_vdiveud(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vdiveud:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vdiveud v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %div = tail call <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %div
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -849,13 +849,21 @@
 "vdivud $vD, $vA, $vB", IIC_VecGeneral,
 [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>;
   def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
- 

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Amy Kwan via Phabricator via cfe-commits]

amyk updated this revision to Diff 273578.
amyk added a comment.

Addressed Anil's comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82609/new/

https://reviews.llvm.org/D82609

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
  llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -84,3 +84,15 @@
 # CHECK-BE: vmulhud 1, 2, 3   # encoding: [0x10,0x22,0x1a,0xc9]
 # CHECK-LE: vmulhud 1, 2, 3   # encoding: [0xc9,0x1a,0x22,0x10]
 vmulhud 1, 2, 3
+# CHECK-BE: vdivesw 21, 11, 10# encoding: [0x12,0xab,0x53,0x8b]
+# CHECK-LE: vdivesw 21, 11, 10# encoding: [0x8b,0x53,0xab,0x12]
+vdivesw 21, 11, 10
+# CHECK-BE: vdiveuw 21, 11, 10# encoding: [0x12,0xab,0x52,0x8b]
+# CHECK-LE: vdiveuw 21, 11, 10# encoding: [0x8b,0x52,0xab,0x12]
+vdiveuw 21, 11, 10
+# CHECK-BE: vdivesd 21, 11, 10# encoding: [0x12,0xab,0x53,0xcb]
+# CHECK-LE: vdivesd 21, 11, 10# encoding: [0xcb,0x53,0xab,0x12]
+vdivesd 21, 11, 10
+# CHECK-BE: vdiveud 21, 11, 10# encoding: [0x12,0xab,0x52,0xcb]
+# CHECK-LE: vdiveud 21, 11, 10# encoding: [0xcb,0x52,0xab,0x12]
+vdiveud 21, 11, 10
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -81,3 +81,15 @@
 
 # CHECK: vmulhud 1, 2, 3
 0x10 0x22 0x1a 0xc9
+
+# CHECK: vdivesw 21, 11, 10
+0x12 0xab 0x53 0x8b
+
+# CHECK: vdiveuw 21, 11, 10
+0x12 0xab 0x52 0x8b
+
+# CHECK: vdivesd 21, 11, 10
+0x12 0xab 0x53 0xcb
+
+# CHECK: vdiveud 21, 11, 10
+0x12 0xab 0x52 0xcb
Index: llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
===
--- llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
+++ llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
@@ -72,3 +72,49 @@
   %tr = trunc <4 x i64> %shr to <4 x i32>
   ret <4 x i32> %tr
 }
+
+; Test the vector multiply high intrinsics.
+declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.ppc.altivec.vmulhud(<2 x i64>, <2 x i64>)
+
+define <4 x i32> @test_vmulhsw_intrinsic(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhsw_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhsw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %mulh
+}
+
+define <4 x i32> @test_vmulhuw_intrinsic(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhuw_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhuw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %mulh
+}
+
+define <2 x i64> @test_vmulhsd_intrinsic(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhsd_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhsd v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %mulh
+}
+
+define <2 x i64> @test_vmulhud_intrinsic(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhud_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhud v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <2 x i64> @llvm.ppc.altivec.vmulhud(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %mulh
+}
Index: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
===
--- llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
+++ llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
@@ -46,3 +46,49 @@
   %div = sdiv <4 x i32> %a, %b
   ret <4 x i32> %div
 }
+
+; Test the vector divide extended intrinsics.
+declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64>, <2 x i64>)
+
+define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vdivesw:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vdivesw v2, v2, v3
+; 

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Amy Kwan via Phabricator via cfe-commits]

amyk marked 2 inline comments as done.
amyk added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:18
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_dive(vsia, vsib);
+}

anil9 wrote:
> I may be wrong but where are the variables declared ? I do not see the 
> variables delclared above in the file, i mean many of them.
I accidentally uploaded the wrong diff, I will update this. 



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll:49
 }
+
+declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>)

anil9 wrote:
> nit : you put a comment right at this position in the multiply.ll file, for 
> consistency you could add one here or remove the one there. 
Will fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82609/new/

https://reviews.llvm.org/D82609



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Anil Mahmud via Phabricator via cfe-commits]

anil9 added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:18
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_dive(vsia, vsib);
+}

I may be wrong but where are the variables declared ? I do not see the 
variables delclared above in the file, i mean many of them.



Comment at: llvm/test/CodeGen/PowerPC/p10-vector-divide.ll:49
 }
+
+declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>)

nit : you put a comment right at this position in the multiply.ll file, for 
consistency you could add one here or remove the one there. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82609/new/

https://reviews.llvm.org/D82609



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

[Amy Kwan via Phabricator via cfe-commits]

amyk created this revision.
amyk added reviewers: power-llvm-team, PowerPC, nemanjai, lei, saghir.
amyk added projects: LLVM, clang, PowerPC.
Herald added subscribers: shchenz, hiraditya.

This patch implements the following function prototypes to utilize the 
`vmulh[s|u][w|d]` and `vdive[s|u][w|d]` instructions:

  vector signed int vec_mulh (vector signed int a, vector signed int b);  
  vector unsigned int vec_mulh (vector unsigned int a, vector unsigned int b); 
  vector signed long long vec_mulh (vector signed long long a, vector signed 
long long b); 
  vector unsigned long long vec_mulh (vector unsigned long long a, vector 
unsigned long long b);
  
  vector signed int vec_dive (vector signed int a, vector signed int b);
  vector unsigned int vec_dive (vector unsigned int a, vector unsigned int b);
  vector signed long long vec_dive (vector signed long long a, vector signed 
long long b);
  vector unsigned long long vec_dive (vector unsigned long long a, vector 
unsigned long long b);

Depends on D82584 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82609

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
  llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -84,3 +84,15 @@
 # CHECK-BE: vmulhud 1, 2, 3   # encoding: [0x10,0x22,0x1a,0xc9]
 # CHECK-LE: vmulhud 1, 2, 3   # encoding: [0xc9,0x1a,0x22,0x10]
 vmulhud 1, 2, 3
+# CHECK-BE: vdivesw 21, 11, 10# encoding: [0x12,0xab,0x53,0x8b]
+# CHECK-LE: vdivesw 21, 11, 10# encoding: [0x8b,0x53,0xab,0x12]
+vdivesw 21, 11, 10
+# CHECK-BE: vdiveuw 21, 11, 10# encoding: [0x12,0xab,0x52,0x8b]
+# CHECK-LE: vdiveuw 21, 11, 10# encoding: [0x8b,0x52,0xab,0x12]
+vdiveuw 21, 11, 10
+# CHECK-BE: vdivesd 21, 11, 10# encoding: [0x12,0xab,0x53,0xcb]
+# CHECK-LE: vdivesd 21, 11, 10# encoding: [0xcb,0x53,0xab,0x12]
+vdivesd 21, 11, 10
+# CHECK-BE: vdiveud 21, 11, 10# encoding: [0x12,0xab,0x52,0xcb]
+# CHECK-LE: vdiveud 21, 11, 10# encoding: [0xcb,0x52,0xab,0x12]
+vdiveud 21, 11, 10
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -81,3 +81,15 @@
 
 # CHECK: vmulhud 1, 2, 3
 0x10 0x22 0x1a 0xc9
+
+# CHECK: vdivesw 21, 11, 10
+0x12 0xab 0x53 0x8b
+
+# CHECK: vdiveuw 21, 11, 10
+0x12 0xab 0x52 0x8b
+
+# CHECK: vdivesd 21, 11, 10
+0x12 0xab 0x53 0xcb
+
+# CHECK: vdiveud 21, 11, 10
+0x12 0xab 0x52 0xcb
Index: llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
===
--- llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
+++ llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
@@ -72,3 +72,49 @@
   %tr = trunc <4 x i64> %shr to <4 x i32>
   ret <4 x i32> %tr
 }
+
+; Test the vector multiply high intrinsics.
+declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.ppc.altivec.vmulhud(<2 x i64>, <2 x i64>)
+
+define <4 x i32> @test_vmulhsw_intrinsic(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhsw_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhsw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %mulh
+}
+
+define <4 x i32> @test_vmulhuw_intrinsic(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vmulhuw_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhuw v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %mulh
+}
+
+define <2 x i64> @test_vmulhsd_intrinsic(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhsd_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vmulhsd v2, v2, v3
+; CHECK-NEXT:blr
+entry:
+  %mulh = tail call <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %mulh
+}
+
+define <2 x i64> @test_vmulhud_intrinsic(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_vmulhud_intrinsic:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT: