[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
hubert.reinterpretcast added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1006 "vexpandbm $vD, $vB", IIC_VecGeneral, - []>; + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; The commit added "physical" tab characters instead of spaces here. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGefa57f9a7adb: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang (authored by amyk). Changed prior to commit: https://reviews.llvm.org/D82727?vs=287434&id=290152#toc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Headers/altivec.h clang/test/CodeGen/builtins-ppc-p10vector.c llvm/include/llvm/IR/IntrinsicsPowerPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll Index: llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll === --- llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll +++ llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll @@ -64,3 +64,59 @@ %ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a) ret i32 %ext } + +declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>) +declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>) +declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>) +declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>) +declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>) + +define <16 x i8> @test_vexpandbm(<16 x i8> %a) { +; CHECK-LABEL: test_vexpandbm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandbm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a) + ret <16 x i8> %exp +} + +define <8 x i16> @test_vexpandhm(<8 x i16> %a) { +; CHECK-LABEL: test_vexpandhm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandhm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a) + ret <8 x i16> %exp +} + +define <4 x i32> @test_vexpandwm(<4 x i32> %a) { +; CHECK-LABEL: test_vexpandwm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandwm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a) + ret <4 x i32> %exp +} + +define <2 x i64> @test_vexpanddm(<2 x i64> %a) { +; CHECK-LABEL: test_vexpanddm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpanddm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a) + ret <2 x i64> %exp +} + +define <1 x i128> @test_vexpandqm(<1 x i128> %a) { +; CHECK-LABEL: test_vexpandqm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandqm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a) + ret <1 x i128> %exp +} Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td === --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -1003,19 +1003,24 @@ (int_ppc_altivec_vextractqm v1i128:$vB))]>; def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandbm $vD, $vB", IIC_VecGeneral, - []>; + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandhm $vD, $vB", IIC_VecGeneral, - []>; + [(set v8i16:$vD, (int_ppc_altivec_vexpandhm + v8i16:$vB))]>; def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandwm $vD, $vB", IIC_VecGeneral, - []>; + [(set v4i32:$vD, (int_ppc_altivec_vexpandwm + v4i32:$vB))]>; def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), "vexpanddm $vD, $vB", IIC_VecGeneral, - []>; + [(set v2i64:$vD, (int_ppc_altivec_vexpanddm + v2i64:$vB))]>; def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandqm $vD, $vB", IIC_VecGeneral, - []>; + [(set v1i128:$vD, (int_ppc_altivec_vexpandqm + v1i128:$vB))]>; def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), "mtvsrbm $vD, $rB", IIC_VecGeneral, []>; Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
Conanap accepted this revision. Conanap added a comment. This revision is now accepted and ready to land. Minor nit, okay if changed for commit Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
Conanap added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:993 + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), Nit: Please make this indentation inline with the others Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
amyk updated this revision to Diff 287434. amyk added a comment. Update clang test names for `vec_expandm`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Headers/altivec.h clang/test/CodeGen/builtins-ppc-p10vector.c llvm/include/llvm/IR/IntrinsicsPowerPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll Index: llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll === --- llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll +++ llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll @@ -64,3 +64,59 @@ %ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a) ret i32 %ext } + +declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>) +declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>) +declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>) +declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>) +declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>) + +define <16 x i8> @test_vexpandbm(<16 x i8> %a) { +; CHECK-LABEL: test_vexpandbm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandbm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a) + ret <16 x i8> %exp +} + +define <8 x i16> @test_vexpandhm(<8 x i16> %a) { +; CHECK-LABEL: test_vexpandhm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandhm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a) + ret <8 x i16> %exp +} + +define <4 x i32> @test_vexpandwm(<4 x i32> %a) { +; CHECK-LABEL: test_vexpandwm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandwm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a) + ret <4 x i32> %exp +} + +define <2 x i64> @test_vexpanddm(<2 x i64> %a) { +; CHECK-LABEL: test_vexpanddm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpanddm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a) + ret <2 x i64> %exp +} + +define <1 x i128> @test_vexpandqm(<1 x i128> %a) { +; CHECK-LABEL: test_vexpandqm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandqm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a) + ret <1 x i128> %exp +} Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td === --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -989,19 +989,24 @@ (int_ppc_altivec_vextractqm v1i128:$vB))]>; def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandbm $vD, $vB", IIC_VecGeneral, - []>; + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandhm $vD, $vB", IIC_VecGeneral, - []>; + [(set v8i16:$vD, (int_ppc_altivec_vexpandhm + v8i16:$vB))]>; def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandwm $vD, $vB", IIC_VecGeneral, - []>; + [(set v4i32:$vD, (int_ppc_altivec_vexpandwm + v4i32:$vB))]>; def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), "vexpanddm $vD, $vB", IIC_VecGeneral, - []>; + [(set v2i64:$vD, (int_ppc_altivec_vexpanddm + v2i64:$vB))]>; def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandqm $vD, $vB", IIC_VecGeneral, - []>; + [(set v1i128:$vD, (int_ppc_altivec_vexpandqm + v1i128:$vB))]>; def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), "mtvsrbm $vD, $rB", IIC_VecGeneral, []>; Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td === --- llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -448,6 +448,18 @@ def int_ppc_altivec_vextractqm : GCCBuilti
[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
NeHuang added a comment. Overall LGTM. I only have some nits comment. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:136 +vector unsigned char test_vexpandm_uc(void) { + // CHECK: @llvm.ppc.altivec.vexpandbm(<16 x i8> %{{.+}}) nit: can we change the naming convention to be consistent as above? (e.g. "test_vec_expandm_uc") I do not have a strong preference for either way since we did have different naming conventions in `builtins-ppc-p10vector.c` and `p10-vector-mask-ops.ll` for the vector extract cases. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:142 + +vector unsigned short test_vexpandm_us(void) { + // CHECK: @llvm.ppc.altivec.vexpandhm(<8 x i16> %{{.+}}) ditto Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:148 + +vector unsigned int test_vexpandm_ui(void) { + // CHECK: @llvm.ppc.altivec.vexpandwm(<4 x i32> %{{.+}}) ditto Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:154 + +vector unsigned long long test_vexpandm_ull(void) { + // CHECK: @llvm.ppc.altivec.vexpanddm(<2 x i64> %{{.+}}) ditto Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:160 + +vector unsigned __int128 test_vexpandm_u128(void) { + // CHECK: @llvm.ppc.altivec.vexpandqm(<1 x i128> %{{.+}}) ditto Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:881 + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), amyk wrote: > I have no idea why this indentation is off, since it did not appear like that > previously. In any case, I can address this during the commit if it is OK. This seems does not cause any clang-format check error during phabricator pre-merge check. I tried downloading this patch and found the indentation is as expected. It seems like a display issue from phabricator. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:881 + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), I have no idea why this indentation is off, since it did not appear like that previously. In any case, I can address this during the commit if it is OK. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang
amyk updated this revision to Diff 283065. amyk added a comment. Rebased the patch and removed MC tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82727/new/ https://reviews.llvm.org/D82727 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Headers/altivec.h clang/test/CodeGen/builtins-ppc-p10vector.c llvm/include/llvm/IR/IntrinsicsPowerPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll Index: llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll === --- llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll +++ llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll @@ -64,3 +64,59 @@ %ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a) ret i32 %ext } + +declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>) +declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>) +declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>) +declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>) +declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>) + +define <16 x i8> @test_vexpandbm(<16 x i8> %a) { +; CHECK-LABEL: test_vexpandbm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandbm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a) + ret <16 x i8> %exp +} + +define <8 x i16> @test_vexpandhm(<8 x i16> %a) { +; CHECK-LABEL: test_vexpandhm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandhm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a) + ret <8 x i16> %exp +} + +define <4 x i32> @test_vexpandwm(<4 x i32> %a) { +; CHECK-LABEL: test_vexpandwm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandwm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a) + ret <4 x i32> %exp +} + +define <2 x i64> @test_vexpanddm(<2 x i64> %a) { +; CHECK-LABEL: test_vexpanddm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpanddm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a) + ret <2 x i64> %exp +} + +define <1 x i128> @test_vexpandqm(<1 x i128> %a) { +; CHECK-LABEL: test_vexpandqm: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT:vexpandqm v2, v2 +; CHECK-NEXT:blr +entry: + %exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a) + ret <1 x i128> %exp +} Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td === --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -877,19 +877,24 @@ (int_ppc_altivec_vextractqm v1i128:$vB))]>; def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandbm $vD, $vB", IIC_VecGeneral, - []>; + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandhm $vD, $vB", IIC_VecGeneral, - []>; + [(set v8i16:$vD, (int_ppc_altivec_vexpandhm + v8i16:$vB))]>; def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandwm $vD, $vB", IIC_VecGeneral, - []>; + [(set v4i32:$vD, (int_ppc_altivec_vexpandwm + v4i32:$vB))]>; def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), "vexpanddm $vD, $vB", IIC_VecGeneral, - []>; + [(set v2i64:$vD, (int_ppc_altivec_vexpanddm + v2i64:$vB))]>; def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), "vexpandqm $vD, $vB", IIC_VecGeneral, - []>; + [(set v1i128:$vD, (int_ppc_altivec_vexpandqm + v1i128:$vB))]>; def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), "mtvsrbm $vD, $rB", IIC_VecGeneral, []>; Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td === --- llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -441,6 +441,18 @@ def int_ppc_altivec_vextractqm : GCCBuiltin<"