subject:"\[PATCH\] D89025\: \[RISCV\] Add \-mtune support"

[PATCH] D89025: [RISCV] Add -mtune support

2020-10-07 Thread Kito Cheng via Phabricator via cfe-commits

kito-cheng created this revision.
kito-cheng added reviewers: asb, evandro, lenary, khchen.
kito-cheng added projects: LLVM, clang.
Herald added subscribers: llvm-commits, cfe-commits, dang, luismarques, apazos, 
sameer.abuasal, pzheng, pengfei, s.egerton, Jim, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
kito-cheng requested review of this revision.
Herald added a subscriber: MaskRay.

- The goal of this patch is improve option compatible with RISCV-V GCC, -mcpu 
support on GCC side will sent patch in next few days.
- -mtune only affect the pipeline model and non-arch/extension related target 
feature, e.g. instruction fusion; in td file it called TuneFeatures, which is 
introduced by X86 back-end[1].
- -mtune accept all valid option for -mcpu and extra alias processor option, 
e.g. `generic`, `rocket` and `sifive-7-series`, the purpose is option 
compatible with RISCV-V GCC.
- Processor alias for -mtune will resolve according the current target arch, 
rv32 or rv64, e.g. `rocket` will resolve to `rocket-rv32` or `rocket-rv64`.
- Interaction between -mcpu and -mtune:
  - -mtune has higher priority than -mcpu for pipeline model and  
TuneFeatures.

[1] https://reviews.llvm.org/D85165


Repository:
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https://reviews.llvm.org/D89025

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -75,13 +75,16 @@
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU =
   CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+  std::string TuneCPU =
+  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
   FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
-  std::string Key = CPU + FS;
+  std::string Key = CPU + TuneCPU + FS;
   auto &I = SubtargetMap[Key];
   if (!I) {
 // This needs to be done before we create a new subtarget since any
@@ -98,7 +101,7 @@
   }
   ABIName = ModuleTargetABI->getString();
 }
-I = std::make_unique(TargetTriple, CPU, FS, ABIName, *this);
+I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
   }
   return I.get();
 }
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -71,13 +71,15 @@
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
-  StringRef CPU, StringRef FS,
+  StringRef CPU,
+  StringRef TuneCPU,
+  StringRef FS,
   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
-  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
- StringRef ABIName, const TargetMachine &TM);
+  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
+ StringRef FS, StringRef ABIName, const TargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -30,13 +30,16 @@
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
-const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
+const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is6

[PATCH] D89025: [RISCV] Add -mtune support

2020-10-12 Thread Kuan Hsu Chen (Zakk) via Phabricator via cfe-commits

khchen added a comment.

RISCV supports `-mcpu` with default empty arch to align gcc's `-mtune` behavior 
since clang didn't support `-mtune` before. But now clang has `-mtune`, is it a 
good idea to remove those options? (ex. `rocket-rv32/rv64`, `sifive-7-rv32/64`)




Comment at: clang/test/Driver/riscv-cpus.c:82
+// Check interaction between mcpu and mtune.
+//
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 
-mtune=sifive-e76 | FileCheck -check-prefix=MTUNE-E31-MCPU-E76 %s

maybe we can describe what is expected interaction behavior somewhere.


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[PATCH] D89025: [RISCV] Add -mtune support

2020-10-13 Thread Luís Marques via Phabricator via cfe-commits

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM, but I would like other people to also review this, if possible.
(Just be sure to check/fix the clang-format warnings and the inline comments).




Comment at: clang/test/Driver/riscv-cpus.c:29
+
+// Check mtune alias CPU has resolve to the right CPU according XLEN.
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck 
-check-prefix=MTUNE-GENERIC-32 %s

Nit: resolve -> resolved.



Comment at: clang/test/Driver/riscv-cpus.c:82
+// Check interaction between mcpu and mtune.
+//
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 
-mtune=sifive-e76 | FileCheck -check-prefix=MTUNE-E31-MCPU-E76 %s

khchen wrote:
> maybe we can describe what is expected interaction behavior somewhere.
+1



Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:201
   const RISCVTargetMachine &RTM = static_cast(TM);
-  const RISCVSubtarget STI(TT, CPU, FS, /*ABIName=*/"", RTM);
+  /* TuneCPU don't impact emission for ELF attributes, ELF attribute only
+ care about arch related features, so we can set TuneCPU as CPU.  */

Nit: don't -> doesn't; for -> of; attribute -> attributes.


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[PATCH] D89025: [RISCV] Add -mtune support

2020-10-13 Thread Luís Marques via Phabricator via cfe-commits

luismarques added a comment.

In D89025#2324334 , @khchen wrote:

> RISCV supports `-mcpu` with default empty arch to align gcc's `-mtune` 
> behavior since clang didn't support `-mtune` before. But now clang has 
> `-mtune`, is it a good idea to remove those options? (ex. `rocket-rv32/rv64`, 
> `sifive-7-rv32/64`)

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or 
unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang 
with GCC. But I wonder if this might be too problematic, in terms of 
compatibility.

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[PATCH] D89025: [RISCV] Add -mtune support

2020-10-13 Thread Kito Cheng via Phabricator via cfe-commits

kito-cheng added a comment.

> If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or 
> unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang 
> with GCC. But I wonder if this might be too problematic, in terms of 
> compatibility.

I am also working on `-mcpu` support for RISC-V GCC, and I expect it would 
included in next GCC release, so `-mcpu` and `-mtune` would align between both 
compilers.
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/556058.html


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[PATCH] D89025: [RISCV] Add -mtune support

2020-10-14 Thread Kito Cheng via Phabricator via cfe-commits

kito-cheng updated this revision to Diff 298060.
kito-cheng added a comment.

ChangeLog

- Fix wording in comment
- Add more comment in testcase
- Fix format issue.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -75,13 +75,16 @@
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU =
   CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+  std::string TuneCPU =
+  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
   FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
-  std::string Key = CPU + FS;
+  std::string Key = CPU + TuneCPU + FS;
   auto &I = SubtargetMap[Key];
   if (!I) {
 // This needs to be done before we create a new subtarget since any
@@ -98,7 +101,7 @@
   }
   ABIName = ModuleTargetABI->getString();
 }
-I = std::make_unique(TargetTriple, CPU, FS, ABIName, *this);
+I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
   }
   return I.get();
 }
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -71,13 +71,15 @@
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
-  StringRef CPU, StringRef FS,
+  StringRef CPU,
+  StringRef TuneCPU,
+  StringRef FS,
   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
-  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
- StringRef ABIName, const TargetMachine &TM);
+  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
+ StringRef FS, StringRef ABIName, const TargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -30,13 +30,16 @@
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
-const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
+const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
   std::string CPUName = std::string(CPU);
+  std::string TuneCPUName = std::string(TuneCPU);
   if (CPUName.empty())
 CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  if (TuneCPUName.empty())
+TuneCPUName = CPUName;
+  ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
   if (Is64Bit) {
 XLenVT = MVT::i64;
 XLen = 64;
@@ -47,11 +50,12 @@
   return *this;
 }
 
-RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
+RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
+   StringRef TuneCPU, StringRef FS,
StringRef ABIName, const TargetMachine &TM)
-: RISCVGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
   UserReservedRegister(RISCV::NUM_TARGET_REGS),
-  FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
+  FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *

[PATCH] D89025: [RISCV] Add -mtune support

2020-10-14 Thread Kito Cheng via Phabricator via cfe-commits

kito-cheng marked 3 inline comments as done.
kito-cheng added a comment.

In D89025#2327749 , @luismarques wrote:

> In D89025#2324334 , @khchen wrote:
>
>> RISCV supports `-mcpu` with default empty arch to align gcc's `-mtune` 
>> behavior since clang didn't support `-mtune` before. But now clang has 
>> `-mtune`, is it a good idea to remove those options? (ex. 
>> `rocket-rv32/rv64`, `sifive-7-rv32/64`)
>
> If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or 
> unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang 
> with GCC. But I wonder if this might be too problematic, in terms of 
> compatibility.

Personally I would like to remove `rocket-rv32/rv64`, `sifive-7-rv32/64`, but I 
didn't remove `rocket-rv32/rv64`, `sifive-7-rv32/64` in version 2 patch,  since 
I concern about compatibility too, Clang/LLVM 11 already included that, I would 
prefer create another patch to remove that and discuss that issue.

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[PATCH] D89025: [RISCV] Add -mtune support

2020-10-14 Thread Fangrui Song via Phabricator via cfe-commits

MaskRay added inline comments.



Comment at: clang/test/Driver/riscv-cpus.c:91
+// MTUNE-E31-MCPU-E76: "-target-feature" "+a"
+// MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f"
+// MTUNE-E31-MCPU-E76: "-target-feature" "+c"

A NOT pattern depends on the feature order and thus a bit unreliable. 
Please use -SAME whenever appropriate


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[PATCH] D89025: [RISCV] Add -mtune support

2020-10-14 Thread Kito Cheng via Phabricator via cfe-commits

kito-cheng updated this revision to Diff 298293.
kito-cheng added a comment.

ChangeLog:

- Update testcase according to MaskRay's suggestion.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -75,13 +75,16 @@
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU =
   CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+  std::string TuneCPU =
+  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
   FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
-  std::string Key = CPU + FS;
+  std::string Key = CPU + TuneCPU + FS;
   auto &I = SubtargetMap[Key];
   if (!I) {
 // This needs to be done before we create a new subtarget since any
@@ -98,7 +101,7 @@
   }
   ABIName = ModuleTargetABI->getString();
 }
-I = std::make_unique(TargetTriple, CPU, FS, ABIName, *this);
+I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
   }
   return I.get();
 }
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -71,13 +71,15 @@
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
-  StringRef CPU, StringRef FS,
+  StringRef CPU,
+  StringRef TuneCPU,
+  StringRef FS,
   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
-  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
- StringRef ABIName, const TargetMachine &TM);
+  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
+ StringRef FS, StringRef ABIName, const TargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -30,13 +30,16 @@
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
-const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
+const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
   std::string CPUName = std::string(CPU);
+  std::string TuneCPUName = std::string(TuneCPU);
   if (CPUName.empty())
 CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  if (TuneCPUName.empty())
+TuneCPUName = CPUName;
+  ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
   if (Is64Bit) {
 XLenVT = MVT::i64;
 XLen = 64;
@@ -47,11 +50,12 @@
   return *this;
 }
 
-RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
+RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
+   StringRef TuneCPU, StringRef FS,
StringRef ABIName, const TargetMachine &TM)
-: RISCVGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
   UserReservedRegister(RISCV::NUM_TARGET_REGS),
-  FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
+  FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
   CallLowerin

[PATCH] D89025: [RISCV] Add -mtune support

2020-10-14 Thread Kito Cheng via Phabricator via cfe-commits

kito-cheng marked an inline comment as done.
kito-cheng added a comment.

@MaskRay Thanks, that's first time I know the suffix `-SAME`  :P


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[PATCH] D89025: [RISCV] Add -mtune support

2020-10-15 Thread Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcfa7094e49cf: [RISCV] Add -mtune support (authored by Kito 
Cheng ).
Herald added a subscriber: NickHung.

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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -75,13 +75,16 @@
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   std::string CPU =
   CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+  std::string TuneCPU =
+  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
   std::string FS =
   FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
-  std::string Key = CPU + FS;
+  std::string Key = CPU + TuneCPU + FS;
   auto &I = SubtargetMap[Key];
   if (!I) {
 // This needs to be done before we create a new subtarget since any
@@ -98,7 +101,7 @@
   }
   ABIName = ModuleTargetABI->getString();
 }
-I = std::make_unique(TargetTriple, CPU, FS, ABIName, *this);
+I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
   }
   return I.get();
 }
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -71,13 +71,15 @@
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
-  StringRef CPU, StringRef FS,
+  StringRef CPU,
+  StringRef TuneCPU,
+  StringRef FS,
   StringRef ABIName);
 
 public:
   // Initializes the data members to match that of the specified triple.
-  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
- StringRef ABIName, const TargetMachine &TM);
+  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
+ StringRef FS, StringRef ABIName, const TargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -30,13 +30,16 @@
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
-const Triple &TT, StringRef CPU, StringRef FS, StringRef ABIName) {
+const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) {
   // Determine default and user-specified characteristics
   bool Is64Bit = TT.isArch64Bit();
   std::string CPUName = std::string(CPU);
+  std::string TuneCPUName = std::string(TuneCPU);
   if (CPUName.empty())
 CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  if (TuneCPUName.empty())
+TuneCPUName = CPUName;
+  ParseSubtargetFeatures(CPUName, TuneCPUName, FS);
   if (Is64Bit) {
 XLenVT = MVT::i64;
 XLen = 64;
@@ -47,11 +50,12 @@
   return *this;
 }
 
-RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
+RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
+   StringRef TuneCPU, StringRef FS,
StringRef ABIName, const TargetMachine &TM)
-: RISCVGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+: RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
   UserReservedRegister(RISCV::NUM_TARGET_REGS),
-  FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
+  FrameLowering(initializeSubtargetDependenci

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

[PATCH] D89025: [RISCV] Add -mtune support

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