[PATCH] D95012: [WebAssembly] Prototype new f64x2 conversions

2021-01-20 Thread Thomas Lively via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG11802eced5d6: [WebAssembly] Prototype new f64x2 conversions 
(authored by tlively).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95012/new/

https://reviews.llvm.org/D95012

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -742,4 +742,22 @@
 # CHECK: prefetch.nt 16 # encoding: [0xfd,0xc6,0x01,0x00,0x10]
 prefetch.nt 16
 
+# CHECK: f64x2.convert_low_i32x4_s # encoding: [0xfd,0x53]
+f64x2.convert_low_i32x4_s
+
+# CHECK: f64x2.convert_low_i32x4_u # encoding: [0xfd,0x54]
+f64x2.convert_low_i32x4_u
+
+# CHECK: i32x4.trunc_sat_zero_f64x2_s # encoding: [0xfd,0x55]
+i32x4.trunc_sat_zero_f64x2_s
+
+# CHECK: i32x4.trunc_sat_zero_f64x2_u # encoding: [0xfd,0x56]
+i32x4.trunc_sat_zero_f64x2_u
+
+# CHECK: f32x4.demote_zero_f64x2 # encoding: [0xfd,0x57]
+f32x4.demote_zero_f64x2
+
+# CHECK: f64x2.promote_low_f32x4 # encoding: [0xfd,0x69]
+f64x2.promote_low_f32x4
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -566,6 +566,26 @@
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: trunc_sat_zero_signed_v4i32:
+; SIMD128-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double>)
+define <4 x i32> @trunc_sat_zero_signed_v4i32(<2 x double> %a) {
+  %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double> %a)
+  ret <4 x i32> %v
+}
+
+; CHECK-LABEL: trunc_sat_zero_unsigned_v4i32:
+; SIMD128-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double>)
+define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
+  %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double> %a)
+  ret <4 x i32> %v
+}
+
 ; ==
 ; 2 x i64
 ; ==
@@ -820,6 +840,16 @@
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: demote_zero_v4f32:
+; SIMD128-NEXT: .functype demote_zero_v4f32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f32x4.demote_zero_f64x2 $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.demote.zero(<2 x double>)
+define <4 x float> @demote_zero_v4f32(<2 x double> %a) {
+  %v = call <4 x float> @llvm.wasm.demote.zero(<2 x double> %a)
+  ret <4 x float> %v
+}
+
 ; ==
 ; 2 x f64
 ; ==
@@ -918,3 +948,33 @@
   )
   ret <2 x double> %v
 }
+
+; CHECK-LABEL: convert_low_signed_v2f64:
+; SIMD128-NEXT: .functype convert_low_signed_v2f64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.convert.low.signed(<4 x i32>)
+define <2 x double> @convert_low_signed_v2f64(<4 x i32> %a) {
+  %v = call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %a)
+  ret <2 x double> %v
+}
+
+; CHECK-LABEL: convert_low_unsigned_v2f64:
+; SIMD128-NEXT: .functype convert_low_unsigned_v2f64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32>)
+define <2 x double> @convert_low_unsigned_v2f64(<4 x i32> %a) {
+  %v = call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %a)
+  ret <2 x double> %v
+}
+
+; CHECK-LABEL: promote_low_v2f64:
+; SIMD128-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.promote.low(<4 x float>)
+define <2 x double> @promote_low_v2f64(<4 x float> %a) {
+  %v = call <2 x double>

[PATCH] D95012: [WebAssembly] Prototype new f64x2 conversions

2021-01-19 Thread Thomas Lively via Phabricator via cfe-commits 
tlively created this revision.
tlively added a reviewer: aheejin.
Herald added subscribers: wingo, ecnelises, sunfish, hiraditya, 
jgravelle-google, sbc100, dschuff.
tlively requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

As proposed in https://github.com/WebAssembly/simd/pull/383.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95012

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -742,4 +742,22 @@
 # CHECK: prefetch.nt 16 # encoding: [0xfd,0xc6,0x01,0x00,0x10]
 prefetch.nt 16
 
+# CHECK: f64x2.convert_low_i32x4_s # encoding: [0xfd,0x53]
+f64x2.convert_low_i32x4_s
+
+# CHECK: f64x2.convert_low_i32x4_u # encoding: [0xfd,0x54]
+f64x2.convert_low_i32x4_u
+
+# CHECK: i32x4.trunc_sat_zero_f64x2_s # encoding: [0xfd,0x55]
+i32x4.trunc_sat_zero_f64x2_s
+
+# CHECK: i32x4.trunc_sat_zero_f64x2_u # encoding: [0xfd,0x56]
+i32x4.trunc_sat_zero_f64x2_u
+
+# CHECK: f32x4.demote_zero_f64x2 # encoding: [0xfd,0x57]
+f32x4.demote_zero_f64x2
+
+# CHECK: f64x2.promote_low_f32x4 # encoding: [0xfd,0x69]
+f64x2.promote_low_f32x4
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -566,6 +566,26 @@
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: trunc_sat_zero_signed_v4i32:
+; SIMD128-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double>)
+define <4 x i32> @trunc_sat_zero_signed_v4i32(<2 x double> %a) {
+  %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double> %a)
+  ret <4 x i32> %v
+}
+
+; CHECK-LABEL: trunc_sat_zero_unsigned_v4i32:
+; SIMD128-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double>)
+define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
+  %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double> %a)
+  ret <4 x i32> %v
+}
+
 ; ==
 ; 2 x i64
 ; ==
@@ -820,6 +840,16 @@
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: demote_zero_v4f32:
+; SIMD128-NEXT: .functype demote_zero_v4f32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f32x4.demote_zero_f64x2 $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.demote.zero(<2 x double>)
+define <4 x float> @demote_zero_v4f32(<2 x double> %a) {
+  %v = call <4 x float> @llvm.wasm.demote.zero(<2 x double> %a)
+  ret <4 x float> %v
+}
+
 ; ==
 ; 2 x f64
 ; ==
@@ -918,3 +948,33 @@
   )
   ret <2 x double> %v
 }
+
+; CHECK-LABEL: convert_low_signed_v2f64:
+; SIMD128-NEXT: .functype convert_low_signed_v2f64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f64x2.convert_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.convert.low.signed(<4 x i32>)
+define <2 x double> @convert_low_signed_v2f64(<4 x i32> %a) {
+  %v = call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %a)
+  ret <2 x double> %v
+}
+
+; CHECK-LABEL: convert_low_unsigned_v2f64:
+; SIMD128-NEXT: .functype convert_low_unsigned_v2f64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f64x2.convert_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32>)
+define <2 x double> @convert_low_unsigned_v2f64(<4 x i32> %a) {
+  %v = call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %a)
+  ret <2 x double> %v
+}
+
+; CHECK-LABEL: promote_low_v2f64:
+; SIMD128-NEXT: .functype promote_low_v2f64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: f64x2.promote_low_f32x4 $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.promote.low(<4 x float>)
+define <2 x double>