[clang] [AArch64] Add soft-float ABI (PR #74460)
https://github.com/ostannard created
https://github.com/llvm/llvm-project/pull/74460
This adds support for the AArch64 soft-float ABI. The specification for this
ABI is currently in review at https://github.com/ARM-software/abi-aa/pull/232,
and I won't commit this until that PR is merged.
Because all existing AArch64 hardware has floating-point hardware, we expect
this to be a niche option, only used for embedded systems on R-profile systems.
We are going to document that SysV-like systems should only ever use the base
(hard-float) PCS variant: https://github.com/ARM-software/abi-aa/pull/233. For
that reason, I've not added an option to select the ABI independently of the
FPU hardware, instead the new ABI is enabled iff the target architecture does
not have an FPU.
For testing, I have run this through an ABI fuzzer, but since this is the first
implementation it can only test for internal consistency (callers and callees
agree on the PCS), not for conformance to the ABI spec.
>From 316854b6558811aaa03b9f96be1849e0426f8aac Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Fri, 1 Dec 2023 10:06:57 +
Subject: [PATCH 1/4] [AArch64] Split feature tests for FP and SIMD
AArch64TargetInfo defaults to having the FP feature enabled, but this
function was ignoring that and checking for SIMD instructions instead.
This won't affect most users, because the driver explicitly enables or
disables fp-armv8, which gets handled by
AArch64TargetInfo::handleTargetFeatures to turn FP and SIMD on or off.
However, it will make testing future patches easier, and allow testing
for the presense of FP registers/instructions in CC1 tests.
Change-Id: I2d2b3569dca5fa1dc40c5c6d1dabf7741b8c480e
---
clang/lib/Basic/Targets/AArch64.cpp | 3 +-
.../test/CodeGen/attr-target-clones-aarch64.c | 126 +++---
2 files changed, 107 insertions(+), 22 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c31f2e0bee543..23090dad83ad7 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -649,7 +649,8 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const
{
return llvm::StringSwitch(Feature)
.Cases("aarch64", "arm64", "arm", true)
.Case("fmv", HasFMV)
- .Cases("neon", "fp", "simd", FPU & NeonMode)
+ .Case("fp", FPU & FPUMode)
+ .Cases("neon", "simd", FPU & NeonMode)
.Case("jscvt", HasJSCVT)
.Case("fcma", HasFCMA)
.Case("rng", HasRandGen)
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c
b/clang/test/CodeGen/attr-target-clones-aarch64.c
index 3f2f2fdd24e8a..4404dd0da8e5e 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-attributes --check-globals --include-generated-funcs
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -S -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S
-emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8 -S
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8
-target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s
-check-prefix=CHECK-NOFMV
int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
int __attribute__((target_clones("sha2", "sha2+memtag2", " default ")))
ftc_def(void) { return 1; }
@@ -22,6 +22,8 @@ int __attribute__((target_clones("default"))) main() {
inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma",
"default"))) ftc_inline2(void) { return 2; };
+
+//.
// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
// CHECK: @ftc.ifunc = weak_odr ifunc i32 (), ptr @ftc.resolver
// CHECK: @ftc_def.ifunc = weak_odr ifunc i32 (), ptr @ftc_def.resolver
@@ -30,19 +32,25 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK: @ftc_inline1.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver
// CHECK: @ftc_inline2.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver
// CHECK: @ftc_inline3.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
-
+//.
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc._MlseMaes(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 0
+//
+//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc._Msve2(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 0
+//
+//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 0
+//
+//
// CHECK-LABEL: @ftc.resolver(
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT:call void @__init_cpu_features_resolver()
@@ -63,18 +71,26 @@ inline int
[clang] [AArch64] Add soft-float ABI (PR #74460)
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: None (ostannard)
Changes
This adds support for the AArch64 soft-float ABI. The specification for this
ABI is currently in review at https://github.com/ARM-software/abi-aa/pull/232,
and I won't commit this until that PR is merged.
Because all existing AArch64 hardware has floating-point hardware, we expect
this to be a niche option, only used for embedded systems on R-profile systems.
We are going to document that SysV-like systems should only ever use the base
(hard-float) PCS variant: https://github.com/ARM-software/abi-aa/pull/233. For
that reason, I've not added an option to select the ABI independently of the
FPU hardware, instead the new ABI is enabled iff the target architecture does
not have an FPU.
For testing, I have run this through an ABI fuzzer, but since this is the first
implementation it can only test for internal consistency (callers and callees
agree on the PCS), not for conformance to the ABI spec.
---
Patch is 22.14 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/74460.diff
6 Files Affected:
- (modified) clang/lib/Basic/Targets/AArch64.cpp (+2-1)
- (modified) clang/lib/CodeGen/CodeGenModule.cpp (+2)
- (modified) clang/lib/CodeGen/TargetInfo.h (+1)
- (modified) clang/lib/CodeGen/Targets/AArch64.cpp (+12-5)
- (added) clang/test/CodeGen/aarch64-soft-float-abi.c (+53)
- (modified) clang/test/CodeGen/attr-target-clones-aarch64.c (+105-21)
``diff
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c31f2e0bee543..23090dad83ad7 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -649,7 +649,8 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const
{
return llvm::StringSwitch(Feature)
.Cases("aarch64", "arm64", "arm", true)
.Case("fmv", HasFMV)
- .Cases("neon", "fp", "simd", FPU & NeonMode)
+ .Case("fp", FPU & FPUMode)
+ .Cases("neon", "simd", FPU & NeonMode)
.Case("jscvt", HasJSCVT)
.Case("fcma", HasFCMA)
.Case("rng", HasRandGen)
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index dea58a7ff4146..2e730fdb0b83f 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -143,6 +143,8 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
Kind = AArch64ABIKind::DarwinPCS;
else if (Triple.isOSWindows())
return createWindowsAArch64TargetCodeGenInfo(CGM, AArch64ABIKind::Win64);
+else if (!Target.hasFeature("fp"))
+ Kind = AArch64ABIKind::AAPCSSoft;
return createAArch64TargetCodeGenInfo(CGM, Kind);
}
diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h
index 0c0781a2d5ab9..0b69d92b70cee 100644
--- a/clang/lib/CodeGen/TargetInfo.h
+++ b/clang/lib/CodeGen/TargetInfo.h
@@ -416,6 +416,7 @@ enum class AArch64ABIKind {
AAPCS = 0,
DarwinPCS,
Win64,
+ AAPCSSoft,
};
std::unique_ptr
diff --git a/clang/lib/CodeGen/Targets/AArch64.cpp
b/clang/lib/CodeGen/Targets/AArch64.cpp
index be5145daa00b7..a4089bb6c70f1 100644
--- a/clang/lib/CodeGen/Targets/AArch64.cpp
+++ b/clang/lib/CodeGen/Targets/AArch64.cpp
@@ -53,8 +53,8 @@ class AArch64ABIInfo : public ABIInfo {
Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
CodeGenFunction &CGF) const;
- Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
- CodeGenFunction &CGF) const;
+ Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty, CodeGenFunction &CGF,
+ AArch64ABIKind Kind) const;
Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
QualType Ty) const override {
@@ -65,7 +65,7 @@ class AArch64ABIInfo : public ABIInfo {
return Kind == AArch64ABIKind::Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
: isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
- : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
+ : EmitAAPCSVAArg(VAListAddr, Ty, CGF,
Kind);
}
Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
@@ -478,6 +478,11 @@ bool AArch64SwiftABIInfo::isLegalVectorType(CharUnits
VectorSize,
}
bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
+ // For the soft-float ABI variant, no types are considered to be homogeneous
+ // aggregates.
+ if (Kind == AArch64ABIKind::AAPCSSoft)
+return false;
+
// Homogeneous aggregates for AAPCS64 must have base types of a floating
// point type or a short-vector type. This is the same as the 32-bit ABI,
// but with the difference that any floating-point type is allowed,
@@ -509,7 +514,8 @@ bool
AArch64ABIInfo::isZeroLengthBitfieldPermittedInHomogeneousAggregate()
}
Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualT
[clang] [AArch64] Add soft-float ABI (PR #74460)
github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff ecf881838045985f381003cc27569c73a207d0cc b68ed60a3fe78bc0e9f57b45bed9dd78ed851904 -- clang/test/CodeGen/aarch64-soft-float-abi.c clang/lib/Basic/Targets/AArch64.cpp clang/lib/CodeGen/CodeGenModule.cpp clang/lib/CodeGen/TargetInfo.h clang/lib/CodeGen/Targets/AArch64.cpp clang/test/CodeGen/attr-target-clones-aarch64.c `` View the diff from clang-format here. ``diff diff --git a/clang/lib/CodeGen/Targets/AArch64.cpp b/clang/lib/CodeGen/Targets/AArch64.cpp index a4089bb6c7..d2ce4c0fce 100644 --- a/clang/lib/CodeGen/Targets/AArch64.cpp +++ b/clang/lib/CodeGen/Targets/AArch64.cpp @@ -65,7 +65,7 @@ private: return Kind == AArch64ABIKind::Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty) : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF) - : EmitAAPCSVAArg(VAListAddr, Ty, CGF, Kind); + : EmitAAPCSVAArg(VAListAddr, Ty, CGF, Kind); } Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, `` https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Add soft-float ABI (PR #74460)
DavidSpickett wrote: (maybe this is for a later patch but...) Does this patch include the clang side options for the ABI or does `-march=...+no-fp-armv8` already work for that? https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Add soft-float ABI (PR #74460)
ostannard wrote: This doesn't add any new options, and I'd like to avoid that if possible, instead it is turned on by `-march=...+nofp`. https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Add soft-float ABI (PR #74460)
DavidSpickett wrote: That makes sense. Didn't realise we had an `fp` flag, I don't see it in `llvm/include/llvm/TargetParser/AArch64TargetParser.h`. https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Add soft-float ABI (PR #74460)
efriedma-quic wrote: I'm a little surprised we don't need any LLVM backend changes, but I guess in soft-float mode we basically treat floats as ints anyway, so maybe things just work. I'd like to see appropriate regression tests, though (if they don't already exist). https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Add soft-float ABI (PR #74460)
@@ -534,7 +540,8 @@ Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualType Ty, BaseTy = ArrTy->getElementType(); NumRegs = ArrTy->getNumElements(); } - bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy(); + bool IsFPR = Kind == AArch64ABIKind::AAPCS && davemgreen wrote: Could this be Kind != AArch64ABIKind::AAPCS` in case other ABIKinds make their way here. https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Add soft-float ABI (PR #74460)
https://github.com/ostannard updated
https://github.com/llvm/llvm-project/pull/74460
>From 316854b6558811aaa03b9f96be1849e0426f8aac Mon Sep 17 00:00:00 2001
From: Oliver Stannard
Date: Fri, 1 Dec 2023 10:06:57 +
Subject: [PATCH 1/6] [AArch64] Split feature tests for FP and SIMD
AArch64TargetInfo defaults to having the FP feature enabled, but this
function was ignoring that and checking for SIMD instructions instead.
This won't affect most users, because the driver explicitly enables or
disables fp-armv8, which gets handled by
AArch64TargetInfo::handleTargetFeatures to turn FP and SIMD on or off.
However, it will make testing future patches easier, and allow testing
for the presense of FP registers/instructions in CC1 tests.
Change-Id: I2d2b3569dca5fa1dc40c5c6d1dabf7741b8c480e
---
clang/lib/Basic/Targets/AArch64.cpp | 3 +-
.../test/CodeGen/attr-target-clones-aarch64.c | 126 +++---
2 files changed, 107 insertions(+), 22 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c31f2e0bee543..23090dad83ad7 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -649,7 +649,8 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const
{
return llvm::StringSwitch(Feature)
.Cases("aarch64", "arm64", "arm", true)
.Case("fmv", HasFMV)
- .Cases("neon", "fp", "simd", FPU & NeonMode)
+ .Case("fp", FPU & FPUMode)
+ .Cases("neon", "simd", FPU & NeonMode)
.Case("jscvt", HasJSCVT)
.Case("fcma", HasFCMA)
.Case("rng", HasRandGen)
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c
b/clang/test/CodeGen/attr-target-clones-aarch64.c
index 3f2f2fdd24e8a..4404dd0da8e5e 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -1,6 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --check-attributes --check-globals --include-generated-funcs
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -S -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S
-emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8 -S
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fp-armv8
-target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s
-check-prefix=CHECK-NOFMV
int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
int __attribute__((target_clones("sha2", "sha2+memtag2", " default ")))
ftc_def(void) { return 1; }
@@ -22,6 +22,8 @@ int __attribute__((target_clones("default"))) main() {
inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma",
"default"))) ftc_inline2(void) { return 2; };
+
+//.
// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
// CHECK: @ftc.ifunc = weak_odr ifunc i32 (), ptr @ftc.resolver
// CHECK: @ftc_def.ifunc = weak_odr ifunc i32 (), ptr @ftc_def.resolver
@@ -30,19 +32,25 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK: @ftc_inline1.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline1.resolver
// CHECK: @ftc_inline2.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline2.resolver
// CHECK: @ftc_inline3.ifunc = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
-
+//.
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc._MlseMaes(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 0
+//
+//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc._Msve2(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 0
+//
+//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 0
+//
+//
// CHECK-LABEL: @ftc.resolver(
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT:call void @__init_cpu_features_resolver()
@@ -63,18 +71,26 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:ret ptr @ftc._Msve2
// CHECK: resolver_else2:
// CHECK-NEXT:ret ptr @ftc
+//
+//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc_def._Msha2(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 1
+//
+//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc_def._Msha2Mmemtag2(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 1
+//
+//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: @ftc_def(
// CHECK-NEXT: entry:
// CHECK-NEXT:ret i32 1
+//
+//
// CHECK-LABEL: @ftc_def.resolver(
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT:call void @__init_cpu_features_resolver()
@@ -95,14 +111,20 @@ inline int __attribute__((target_clones("fp16",
"sve2-bitperm+fcma", "default"))
// CHECK-NEXT:ret ptr @ftc_def._Msha2
// CHECK:
[llvm] [clang] [AArch64] Add soft-float ABI (PR #74460)
@@ -534,7 +540,8 @@ Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualType Ty, BaseTy = ArrTy->getElementType(); NumRegs = ArrTy->getNumElements(); } - bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy(); + bool IsFPR = Kind == AArch64ABIKind::AAPCS && ostannard wrote: Done https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Add soft-float ABI (PR #74460)
ostannard wrote: > I'm a little surprised we don't need any LLVM backend changes, but I guess in > soft-float mode we basically treat floats as ints anyway, so maybe things > just work. I'd like to see appropriate regression tests, though (if they > don't already exist). Yes, the backend already treated floats as if they were an integer of the same width, so no changes are needed there. I've added a test for the backend. https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Add soft-float ABI (PR #74460)
ktkachov-arm wrote: Changing the ABI through the architecture flags i.e. +nofp has potential to greatly confuse users, who may come from other architectures that have soft-float ABIs already (including 32-bit arm) - Does this also happen when using +nosimd? - What about users like the Linux kernel that build with -mgeneral-regs-only? - There is already an -mabi= option. How come it doesn't affect what is a pretty major ABI decision? https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [AArch64] Add soft-float ABI (PR #74460)
ostannard wrote: I originally implemented it this way to avoid making two ABIs valid for one target, but I agree that it would be confusing to have the ABI change automatically. How about we use the `-mabi=` option as you suggest, with values `aapcs` (already accepted by clang) and `aapcs-soft` (new)? * `-mabi=aapcs` is always the default * If `-mabi=aapcs` (or the default) is used without an FPU, then floating-point argument and return values are rejected with an error. This matches GCC's current behaviour, and would be a change for clang, though clang previously used a non-compliant ABI. Code which is accepted with this combination is compatible with both ABIs. * If `-mabi=aapcs-soft` is used with an FPU, then we reject the command-line options with an error. This avoids having two incompatible ABIs for one target. We will always have the option to relax this in future without breaking existing code, but I'd like to avoid that unless there's a very good reason. > Does this also happen when using +nosimd? No, in clang `+nosimd` leaves the FPU turned on. That's probably a bad thing, since that isn't a valid combination for AArch64, but that's a different issue. > What about users like the Linux kernel that build with -mgeneral-regs-only? In clang, that has the same behaviour as `+nofp`. I vaguely remember something about GCC still allowing FP instructions in inline assembly with this option, but we don't do that in clang because the assembler is integrated into the compiler, and gets the same target options. For the purposes of the ABI, I think we should treat it the same way as `+nofp`. https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
