[llvm] [clang-tools-extra] [clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)

2023-12-21 Thread David Sherwood via cfe-commits 

https://github.com/david-arm approved this pull request.

LGTM! A lovely patch. :)

https://github.com/llvm/llvm-project/pull/75821
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[clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)

2023-12-20 Thread via cfe-commits 


@@ -1990,79 +1990,61 @@ def SVWHILELO_COUNT  : SInst<"svwhilelo_{d}",  "}nni", 
"QcQsQiQl", MergeNone, "a
 def SVWHILELS_COUNT  : SInst<"svwhilels_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEHI_COUNT  : SInst<"svwhilehi_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEHS_COUNT  : SInst<"svwhilehs_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+}
+
+multiclass MultiVecLoad {
+  // FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when 
available (SME2 requires __arm_streaming)

CarolineConcatto wrote:

I believe sme2 requires __arm_streaming_compatible instead of arm_streaming

https://github.com/llvm/llvm-project/pull/75821
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[clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)

2023-12-18 Thread Dinar Temirbulatov via cfe-commits 

https://github.com/dtemirbulatov approved this pull request.


https://github.com/llvm/llvm-project/pull/75821
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[clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)

2023-12-18 Thread Dinar Temirbulatov via cfe-commits 

dtemirbulatov wrote:

> Should these builtins be `IsStreamingCompatible` until we add 
> `IsStreamingOrSVE2p1`?

yes, it looks like this is the case. LGTM.

https://github.com/llvm/llvm-project/pull/75821
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[clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)

2023-12-18 Thread Sam Tebbs via cfe-commits 

SamTebbs33 wrote:

Should these builtins be `IsStreamingCompatible` until we add 
`IsStreamingOrSVE2p1`?

https://github.com/llvm/llvm-project/pull/75821
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[clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)

2023-12-18 Thread via cfe-commits 

llvmbot wrote:



@llvm/pr-subscribers-clang-codegen

@llvm/pr-subscribers-clang

Author: Kerry McLaughlin (kmclaughlin-arm)


Changes

This patch enables the following builtins for SME2:
 - svld1, svld1_vnum
 - svldnt1, svldnt1_vnum
 - svst1, svst1_vnum
 - svstnt1, svstnt1_vnum

---
Full diff: https://github.com/llvm/llvm-project/pull/75821.diff


5 Files Affected:

- (modified) clang/include/clang/Basic/arm_sve.td (+53-71) 
- (modified) clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ld1.c 
(+4-1) 
- (modified) clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ldnt1.c 
(+4-1) 
- (modified) clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_st1.c 
(+3-1) 
- (modified) clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_stnt1.c 
(+4-1) 


``diff
diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index a429a3c5fe378a..e9a45c3e655f23 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1990,79 +1990,61 @@ def SVWHILELO_COUNT  : SInst<"svwhilelo_{d}",  "}nni", 
"QcQsQiQl", MergeNone, "a
 def SVWHILELS_COUNT  : SInst<"svwhilels_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEHI_COUNT  : SInst<"svwhilehi_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEHS_COUNT  : SInst<"svwhilehs_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+}
+
+multiclass MultiVecLoad {
+  // FIXME: Add IsStreamingOrHasSVE2p1 when available (SME2 requires 
__arm_streaming)
+  def SV # NAME # B_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "cUc",   
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # H_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "sUshb", 
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # W_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "iUif",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # D_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "lUld",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # B_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "cUc",   
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # H_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "sUshb", 
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # W_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "iUif",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # D_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "lUld",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+
+  def SV # NAME # B_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"cUc",   [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # H_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"sUshb", [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # W_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"iUif",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # D_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"lUld",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # B_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"cUc",   [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # H_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"sUshb", [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # W_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"iUif",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # D_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"lUld",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+}
+
+let TargetGuard = "sve2p1|sme2" in {
+  defm LD1   : MultiVecLoad<"ld1">;
+  defm LDNT1 : MultiVecLoad<"ldnt1">;
+}
+
+multiclass MultiVecStore {
+  // FIXME: Add IsStreamingOrHasSVE2p1 when available (SME2 requires 
__arm_streaming)
+  def SV # NAME # B_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "cUc",   
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # H_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "sUshb", 
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # W_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "iUif",  
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # D_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "lUld",  
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # B_X4 : MInst<"sv" # i # "[_{2}_x4]", "v}p4", "cUc",   
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def

[clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)

2023-12-18 Thread Kerry McLaughlin via cfe-commits 

https://github.com/kmclaughlin-arm created 
https://github.com/llvm/llvm-project/pull/75821

This patch enables the following builtins for SME2:
 - svld1, svld1_vnum
 - svldnt1, svldnt1_vnum
 - svst1, svst1_vnum
 - svstnt1, svstnt1_vnum

>From 1b2022f34ad3b038f714d8d0559f4e129d5e731a Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin 
Date: Mon, 18 Dec 2023 14:58:57 +
Subject: [PATCH] [Clang][SME2] Enable multi-vector loads & stores for SME2

This patch enables the following builtins for SME2:
 - svld1, svld1_vnum
 - svldnt1, svldnt1_vnum
 - svst1, svst1_vnum
 - svstnt1, svstnt1_vnum
---
 clang/include/clang/Basic/arm_sve.td  | 124 --
 .../acle_sve2p1_ld1.c |   5 +-
 .../acle_sve2p1_ldnt1.c   |   5 +-
 .../acle_sve2p1_st1.c |   4 +-
 .../acle_sve2p1_stnt1.c   |   5 +-
 5 files changed, 68 insertions(+), 75 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index a429a3c5fe378a..e9a45c3e655f23 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1990,79 +1990,61 @@ def SVWHILELO_COUNT  : SInst<"svwhilelo_{d}",  "}nni", 
"QcQsQiQl", MergeNone, "a
 def SVWHILELS_COUNT  : SInst<"svwhilels_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEHI_COUNT  : SInst<"svwhilehi_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEHS_COUNT  : SInst<"svwhilehs_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+}
+
+multiclass MultiVecLoad {
+  // FIXME: Add IsStreamingOrHasSVE2p1 when available (SME2 requires 
__arm_streaming)
+  def SV # NAME # B_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "cUc",   
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # H_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "sUshb", 
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # W_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "iUif",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # D_X2 : MInst<"sv" # i # "[_{2}]_x2", "2}c", "lUld",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # B_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "cUc",   
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # H_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "sUshb", 
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # W_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "iUif",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # D_X4 : MInst<"sv" # i # "[_{2}]_x4", "4}c", "lUld",  
[IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+
+  def SV # NAME # B_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"cUc",   [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # H_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"sUshb", [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # W_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"iUif",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # D_VNUM_X2 : MInst<"sv" # i # "_vnum" # "[_{2}]_x2", "2}cl", 
"lUld",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # B_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"cUc",   [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # H_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"sUshb", [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # W_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"iUif",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+  def SV # NAME # D_VNUM_X4 : MInst<"sv" # i # "_vnum" # "[_{2}]_x4", "4}cl", 
"lUld",  [IsStructLoad], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x4">;
+}
+
+let TargetGuard = "sve2p1|sme2" in {
+  defm LD1   : MultiVecLoad<"ld1">;
+  defm LDNT1 : MultiVecLoad<"ldnt1">;
+}
+
+multiclass MultiVecStore {
+  // FIXME: Add IsStreamingOrHasSVE2p1 when available (SME2 requires 
__arm_streaming)
+  def SV # NAME # B_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "cUc",   
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # H_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "sUshb", 
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # W_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "iUif",  
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_pn_x2">;
+  def SV # NAME # D_X2 : MInst<"sv" # i # "[_{2}_x2]", "v}p2", "lUld",  
[IsStructStore], MemEltTyDefault, "aarch64_sve_" # i # "_p