llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Brandon Wu (4vtomat)
Changes
---
Patch is 204.88 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/79615.diff
5 Files Affected:
- (modified) clang/include/clang/Basic/riscv_vector.td (+14)
- (added)
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
(+479)
- (added)
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmaccbf16.c
(+469)
- (added)
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmaccbf16.c
(+808)
- (added)
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmaccbf16.c
(+952)
``diff
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index a00ca353588ed5..40a77fa709b7ae 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1730,12 +1730,26 @@ let ManualCodegen = [{
defm vfwnmacc : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
+
+// Vector BF16 widening multiply-accumulate
+let Log2LMUL = [-2, -1, 0, 1, 2],
+HasMaskedOffOperand = false in
+defm vfwmaccbf16 : RVVOutOp1Op2BuiltinSet<"vfwmaccbf16", "y",
+ [["vv", "Fw", "FwFwvvu"],
+ ["vf", "Fw", "FwFwevu"]]>;
}
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm vfwmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwnmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwmsac : RVVFloatingWidenTerBuiltinSet;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSet;
+
+ // Vector BF16 widening multiply-accumulate
+ let Log2LMUL = [-2, -1, 0, 1, 2],
+ HasMaskedOffOperand = false in
+ defm vfwmaccbf16 : RVVOutOp1Op2BuiltinSet<"vfwmaccbf16", "y",
+[["vv", "Fw", "FwFwvv"],
+ ["vf", "Fw", "FwFwev"]]>;
}
}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
new file mode 100644
index 00..75888573d6f344
--- /dev/null
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
@@ -0,0 +1,479 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +zvfh -target-feature +experimental-zvfbfwma
-disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include
+
+// CHECK-RV64-LABEL: define dso_local
@test_vfwmaccbf16_vv_f32mf2(
+// CHECK-RV64-SAME: [[VD:%.*]],
[[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]])
#[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(
[[VD]], [[VS1]], [[VS2]], i64 7,
i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vfloat32mf2_t test_vfwmaccbf16_vv_f32mf2(vfloat32mf2_t vd, vbfloat16mf4_t vs1,
+ vbfloat16mf4_t vs2, size_t vl) {
+ return __riscv_vfwmaccbf16_vv_f32mf2(vd, vs1, vs2, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vfwmaccbf16_vf_f32mf2(
+// CHECK-RV64-SAME: [[VD:%.*]], bfloat noundef
[[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( [[VD]],
bfloat [[VS1]], [[VS2]], i64 7, i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vfloat32mf2_t test_vfwmaccbf16_vf_f32mf2(vfloat32mf2_t vd, __bf16 vs1,
+ vbfloat16mf4_t vs2, size_t vl) {
+ return __riscv_vfwmaccbf16_vf_f32mf2(vd, vs1, vs2, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vfwmaccbf16_vv_f32m1(
+// CHECK-RV64-SAME: [[VD:%.*]],
[[VS1:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]])
#[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(
[[VD]], [[VS1]], [[VS2]], i64 7,
i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret [[TMP0]]
+//
+vfloat32m1_t test_vfwmaccbf16_vv_f32m1(vfloat32m1_t vd, vbfloat16mf2_t vs1,
+ vbfloat16mf2_t vs2, size_t vl) {
+ return __riscv_vfwmaccbf16_vv_f32m1(vd, vs1, vs2, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local
@test_vfwmaccbf16_vf_f32m1(
+// CHECK-RV64-SAME: [[VD:%.*]],
