[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-28 Thread Yingwei Zheng via cfe-commits 

dtcxzyw wrote:

Rebased on top of #70241.

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-28 Thread Yingwei Zheng via cfe-commits 

https://github.com/dtcxzyw updated 
https://github.com/llvm/llvm-project/pull/70232

>From b34055dca42c23682bb9f0e9e022f17e9dbf2aca Mon Sep 17 00:00:00 2001
From: Yingwei Zheng 
Date: Sat, 28 Oct 2023 20:46:37 +0800
Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu

Co-authored-by: SForeKeeper 
---
 clang/test/Driver/riscv-cpus.c|  14 +
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCV.td|   1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  21 +
 .../Target/RISCV/RISCVSchedXiangShanNanHu.td  | 307 ++
 .../llvm-mca/RISCV/XiangShan/cascade-fma.s|  53 ++
 .../llvm-mca/RISCV/XiangShan/gpr-bypass.s | 527 ++
 .../llvm-mca/RISCV/XiangShan/load-to-alu.s|  73 +++
 8 files changed, 998 insertions(+), 2 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | 
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature" 
"+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc" 
"-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd" 
"-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed" 
"-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid 
CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck 
-check-prefix=MTUNE-VEYRON-V1 %s
 // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | 
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
 // Check mtune alias CPU has resolved to the right CPU according XLEN.
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck 
-check-prefix=MTUNE-GENERIC-32 %s
 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, 
sifive-x280, veyron-v1{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, 
sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, 
sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket

[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-26 Thread Yingwei Zheng via cfe-commits 


@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | 
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"

dtcxzyw wrote:

Fixed. Please move to #70294 to review the processor definition part.

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Fangrui Song via cfe-commits 


@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | 
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"

MaskRay wrote:

Prefer `-SAME` for strings on the same line

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Yingwei Zheng via cfe-commits 

dtcxzyw wrote:

> Can you separate out the basic processor definition (using NoSchedModel), and 
> a patch which adds the scheduling model? We can at least get the processor 
> definition landed while we iterate on the scheduling related pieces.
> 
> edit: For clarity, I'm requesting that the basic processor definition and 
> test updates be made into its own pull request, and that this pull request be 
> reserved for adding the schedule model on top.

Posted as #70294.

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Philip Reames via cfe-commits 

preames wrote:

Can you separate out the basic processor definition (using NoSchedModel), and a 
patch which adds the scheduling model?  We can at least get the processor 
definition landed while we iterate on the scheduling related pieces.  

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Yingwei Zheng via cfe-commits 


@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 } // Predicates = [HasStdExtF]
 
 foreach Ext = FExts in {
-  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {

dtcxzyw wrote:

Posted as #70241.

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Craig Topper via cfe-commits 


@@ -936,7 +936,9 @@ def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
 def : ReadAdvance;
+def : ReadAdvance;

topperc wrote:

Please make FMA16 consistent

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Michael Maitland via cfe-commits 


@@ -78,7 +78,7 @@ def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
 } // Predicates = [HasStdExtD]
 
 foreach Ext = DExts in {
-  let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
+  let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in {

michaelmaitland wrote:

Should this change be in a separate commit?

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Michael Maitland via cfe-commits 


@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 } // Predicates = [HasStdExtF]
 
 foreach Ext = FExts in {
-  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+  let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {

michaelmaitland wrote:

Should this change be in a separate commit?

https://github.com/llvm/llvm-project/pull/70232
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[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang-driver

Author: Yingwei Zheng (dtcxzyw)


Changes

[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source 
high-performance RISC-V processor.

This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the 
XiangShan processor series.
Overview: 
https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/

It is based on the patch [D122556](https://reviews.llvm.org/D122556) by @SForeKeeper. The original patch hasn't been updated for a long time and it 
is out of sync with the current RTL design.

Now ICT-CAS is about to complete the tape-out of NanHu core according to @poemonsense. So I posted this PR to add support for it.

[Move 
elimination](https://github.com/dtcxzyw/llvm-project/commit/59f6e22bf12f67d799af641853fec76c0aa8#diff-32270ea35a510b9a116a50cf5b922c46c194da7b0e0afe76576b8b2bef06556d)
 and macro fusions will be supported in subsequent PRs.


---

Patch is 70.52 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/70232.diff


14 Files Affected:

- (modified) clang/test/Driver/riscv-cpus.c (+14) 
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2) 
- (modified) llvm/lib/Target/RISCV/RISCV.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoD.td (+1-1) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoF.td (+1-1) 
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+21) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+2) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+2) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td (+2) 
- (added) llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td (+307) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+2) 
- (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s (+53) 
- (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s (+527) 
- (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s (+73) 


``diff
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | 
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature" 
"+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc" 
"-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd" 
"-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed" 
"-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid 
CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck 
-check-prefix=MTUNE-VEYRON-V1 %s
 // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | 
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
 // Check mtune alias CPU has resolved to the right CPU according XLEN.
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck 
-check-prefix=MTUNE-GENERIC-32 %s
 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, 
sifive-x280, veyron-v1{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifi

[clang] [RISCV] Add sched model for XiangShan-NanHu (PR #70232)

2023-10-25 Thread Yingwei Zheng via cfe-commits 

https://github.com/dtcxzyw created 
https://github.com/llvm/llvm-project/pull/70232

[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source 
high-performance RISC-V processor.

This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the 
XiangShan processor series.
Overview: 
https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/

It is based on the patch [D122556](https://reviews.llvm.org/D122556) by 
@SForeKeeper. The original patch hasn't been updated for a long time and it is 
out of sync with the current RTL design.

Now ICT-CAS is about to complete the tape-out of NanHu core according to 
@poemonsense. So I posted this PR to add support for it.

[Move 
elimination](https://github.com/dtcxzyw/llvm-project/commit/59f6e22bf12f67d799af641853fec76c0aa8#diff-32270ea35a510b9a116a50cf5b922c46c194da7b0e0afe76576b8b2bef06556d)
 and macro fusions will be supported in subsequent PRs.


>From 46644679be9cf1d2fdb75c70a27aefc1fd1488da Mon Sep 17 00:00:00 2001
From: Yingwei Zheng 
Date: Thu, 26 Oct 2023 00:23:32 +0800
Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu

Co-authored-by: SForeKeeper 
---
 clang/test/Driver/riscv-cpus.c|  14 +
 clang/test/Misc/target-invalid-cpu-note.c |   4 +-
 llvm/lib/Target/RISCV/RISCV.td|   1 +
 llvm/lib/Target/RISCV/RISCVInstrInfoD.td  |   2 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoF.td  |   2 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  21 +
 llvm/lib/Target/RISCV/RISCVSchedRocket.td |   2 +
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td|   2 +
 .../Target/RISCV/RISCVSchedSyntacoreSCR1.td   |   2 +
 .../Target/RISCV/RISCVSchedXiangShanNanHu.td  | 307 ++
 llvm/lib/Target/RISCV/RISCVSchedule.td|   2 +
 .../llvm-mca/RISCV/XiangShan/cascade-fma.s|  53 ++
 .../llvm-mca/RISCV/XiangShan/gpr-bypass.s | 527 ++
 .../llvm-mca/RISCV/XiangShan/load-to-alu.s|  73 +++
 14 files changed, 1008 insertions(+), 4 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 3eaceedce685fc6..70f0a63336bd478 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -20,6 +20,17 @@
 // MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu | 
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
+// MCPU-XIANGSHAN-NANHU: "-nostdsysteminc" "-target-cpu" "xiangshan-nanhu"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+c"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zicbom" "-target-feature" 
"+zicboz" "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zba" "-target-feature" "+zbb" 
"-target-feature" "+zbc"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zbkb" "-target-feature" "+zbkc" 
"-target-feature" "+zbkx" "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zkn" "-target-feature" "+zknd" 
"-target-feature" "+zkne" "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-NANHU: "-target-feature" "+zks" "-target-feature" "+zksed" 
"-target-feature" "+zksh" "-target-feature" "+svinval"
+// MCPU-XIANGSHAN-NANHU: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid 
CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -62,6 +73,9 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck 
-check-prefix=MTUNE-VEYRON-V1 %s
 // MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | 
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
+// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
+
 // Check mtune alias CPU has resolved to the right CPU according XLEN.
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck 
-check-prefix=MTUNE-GENERIC-32 %s
 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b2a04ebdbce628f..8e91eb4c62dd259 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-//