[clang] [RISCV] Support floating point VCIX (PR #67094)

2023-09-24 Thread Brandon Wu via cfe-commits

4vtomat wrote:

> The target is support LLVM IR part only, we would like to prevent expose that 
> on the C intrinsic level if possible, because that's intentionally to expose 
> vector with unsigned integer only.

Sure~

https://github.com/llvm/llvm-project/pull/67094
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[clang] [RISCV] Support floating point VCIX (PR #67094)

2023-09-24 Thread Brandon Wu via cfe-commits


@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd, 
 ; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0
 ; CHECK-NEXT:ret
 entry:
-  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1, 
 %vd,  %vs2, half %fs1, iXLen %vl)
+  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.i16.iXLen(iXLen 1, 
 %vd,  %vs2, half %fs1, iXLen %vl)

4vtomat wrote:

Oh, I accidentally changed the type, it should be f16 lol~

https://github.com/llvm/llvm-project/pull/67094
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[clang] [RISCV] Support floating point VCIX (PR #67094)

2023-09-22 Thread Kito Cheng via cfe-commits

https://github.com/kito-cheng edited 
https://github.com/llvm/llvm-project/pull/67094
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[clang] [RISCV] Support floating point VCIX (PR #67094)

2023-09-22 Thread Kito Cheng via cfe-commits

https://github.com/kito-cheng commented:

The target is support LLVM IR part only, we would like to prevent expose that 
on the C intrinsic level if possible, because that's intentionally to expose 
vector with unsigned integer only.

https://github.com/llvm/llvm-project/pull/67094
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[clang] [RISCV] Support floating point VCIX (PR #67094)

2023-09-22 Thread Kito Cheng via cfe-commits


@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd, 
 ; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0
 ; CHECK-NEXT:ret
 entry:
-  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1, 
 %vd,  %vs2, half %fs1, iXLen %vl)
+  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.i16.iXLen(iXLen 1, 
 %vd,  %vs2, half %fs1, iXLen %vl)

kito-cheng wrote:

Why changed to `i16`? arguments is half, which `f16` should be the right type?

https://github.com/llvm/llvm-project/pull/67094
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