[clang] [RISCV] Unify all the code that adds unaligned-scalar/vector-mem to Features vector. (PR #94660)

2024-06-06 Thread Craig Topper via cfe-commits

https://github.com/topperc closed 
https://github.com/llvm/llvm-project/pull/94660
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits


[clang] [RISCV] Unify all the code that adds unaligned-scalar/vector-mem to Features vector. (PR #94660)

2024-06-06 Thread Fangrui Song via cfe-commits

https://github.com/MaskRay approved this pull request.


https://github.com/llvm/llvm-project/pull/94660
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits


[clang] [RISCV] Unify all the code that adds unaligned-scalar/vector-mem to Features vector. (PR #94660)

2024-06-06 Thread via cfe-commits

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Craig Topper (topperc)


Changes

Instead of having multiple places insert into the Features vector 
independently, check all the conditions in one place.

This avoids a subtle ordering requirement that -mstrict-align processing had to 
be done after the others.

---
Full diff: https://github.com/llvm/llvm-project/pull/94660.diff


1 Files Affected:

- (modified) clang/lib/Driver/ToolChains/Arch/RISCV.cpp (+18-13) 


``diff
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 2e2bce8494672..26789b0ba6e09 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -67,11 +67,6 @@ static void getRISCFeaturesFromMcpu(const Driver , const 
Arg *A,
   D.Diag(clang::diag::err_drv_unsupported_option_argument)
   << A->getSpelling() << Mcpu;
   }
-
-  if (llvm::RISCV::hasFastUnalignedAccess(Mcpu)) {
-Features.push_back("+unaligned-scalar-mem");
-Features.push_back("+unaligned-vector-mem");
-  }
 }
 
 void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple ,
@@ -82,6 +77,8 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
   if (!getArchFeatures(D, MArch, Features, Args))
 return;
 
+  bool CPUFastUnaligned = false;
+
   // If users give march and mcpu, get std extension feature from MArch
   // and other features (ex. mirco architecture feature) from mcpu
   if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
@@ -90,6 +87,9 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
   CPU = llvm::sys::getHostCPUName();
 
 getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features);
+
+if (llvm::RISCV::hasFastUnalignedAccess(CPU))
+  CPUFastUnaligned = true;
   }
 
   // Handle features corresponding to "-ffixed-X" options
@@ -169,18 +169,23 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
 Features.push_back("-relax");
   }
 
-  // Android requires fast unaligned access on RISCV64.
-  if (Triple.isAndroid()) {
+  // If -mstrict-align or -mno-strict-align is passed, use it. Otherwise, the
+  // unaligned-*-mem is enabled if the CPU supports it or the target is
+  // Android.
+  if (const Arg *A = Args.getLastArg(options::OPT_mno_strict_align,
+ options::OPT_mstrict_align)) {
+if (A->getOption().matches(options::OPT_mno_strict_align)) {
+  Features.push_back("+unaligned-scalar-mem");
+  Features.push_back("+unaligned-vector-mem");
+} else {
+  Features.push_back("-unaligned-scalar-mem");
+  Features.push_back("-unaligned-vector-mem");
+}
+  } else if (CPUFastUnaligned || Triple.isAndroid()) {
 Features.push_back("+unaligned-scalar-mem");
 Features.push_back("+unaligned-vector-mem");
   }
 
-  // -mstrict-align is default, unless -mno-strict-align is specified.
-  AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
-   options::OPT_mstrict_align, "unaligned-scalar-mem");
-  AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
-   options::OPT_mstrict_align, "unaligned-vector-mem");
-
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,

``




https://github.com/llvm/llvm-project/pull/94660
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits


[clang] [RISCV] Unify all the code that adds unaligned-scalar/vector-mem to Features vector. (PR #94660)

2024-06-06 Thread via cfe-commits

llvmbot wrote:




@llvm/pr-subscribers-clang-driver

Author: Craig Topper (topperc)


Changes

Instead of having multiple places insert into the Features vector 
independently, check all the conditions in one place.

This avoids a subtle ordering requirement that -mstrict-align processing had to 
be done after the others.

---
Full diff: https://github.com/llvm/llvm-project/pull/94660.diff


1 Files Affected:

- (modified) clang/lib/Driver/ToolChains/Arch/RISCV.cpp (+18-13) 


``diff
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 2e2bce8494672..26789b0ba6e09 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -67,11 +67,6 @@ static void getRISCFeaturesFromMcpu(const Driver , const 
Arg *A,
   D.Diag(clang::diag::err_drv_unsupported_option_argument)
   << A->getSpelling() << Mcpu;
   }
-
-  if (llvm::RISCV::hasFastUnalignedAccess(Mcpu)) {
-Features.push_back("+unaligned-scalar-mem");
-Features.push_back("+unaligned-vector-mem");
-  }
 }
 
 void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple ,
@@ -82,6 +77,8 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
   if (!getArchFeatures(D, MArch, Features, Args))
 return;
 
+  bool CPUFastUnaligned = false;
+
   // If users give march and mcpu, get std extension feature from MArch
   // and other features (ex. mirco architecture feature) from mcpu
   if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
@@ -90,6 +87,9 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
   CPU = llvm::sys::getHostCPUName();
 
 getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features);
+
+if (llvm::RISCV::hasFastUnalignedAccess(CPU))
+  CPUFastUnaligned = true;
   }
 
   // Handle features corresponding to "-ffixed-X" options
@@ -169,18 +169,23 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
 Features.push_back("-relax");
   }
 
-  // Android requires fast unaligned access on RISCV64.
-  if (Triple.isAndroid()) {
+  // If -mstrict-align or -mno-strict-align is passed, use it. Otherwise, the
+  // unaligned-*-mem is enabled if the CPU supports it or the target is
+  // Android.
+  if (const Arg *A = Args.getLastArg(options::OPT_mno_strict_align,
+ options::OPT_mstrict_align)) {
+if (A->getOption().matches(options::OPT_mno_strict_align)) {
+  Features.push_back("+unaligned-scalar-mem");
+  Features.push_back("+unaligned-vector-mem");
+} else {
+  Features.push_back("-unaligned-scalar-mem");
+  Features.push_back("-unaligned-vector-mem");
+}
+  } else if (CPUFastUnaligned || Triple.isAndroid()) {
 Features.push_back("+unaligned-scalar-mem");
 Features.push_back("+unaligned-vector-mem");
   }
 
-  // -mstrict-align is default, unless -mno-strict-align is specified.
-  AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
-   options::OPT_mstrict_align, "unaligned-scalar-mem");
-  AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
-   options::OPT_mstrict_align, "unaligned-vector-mem");
-
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,

``




https://github.com/llvm/llvm-project/pull/94660
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits


[clang] [RISCV] Unify all the code that adds unaligned-scalar/vector-mem to Features vector. (PR #94660)

2024-06-06 Thread Craig Topper via cfe-commits

https://github.com/topperc created 
https://github.com/llvm/llvm-project/pull/94660

Instead of having multiple places insert into the Features vector 
independently, check all the conditions in one place.

This avoids a subtle ordering requirement that -mstrict-align processing had to 
be done after the others.

>From d8ddf3218a197ad6fe1227eddd7d3dba6b79b14c Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Thu, 6 Jun 2024 11:51:52 -0700
Subject: [PATCH] [RISCV] Unify all the code that adds
 unaligned-scalar/vector-mem to Features vector.

Instead of having multiple places insert into the Features vector
independently, check all the conditions in one place.

This avoids a subtle ordering requirement that -mstrict-align processing
had to be done after the others.
---
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 31 +-
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp 
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 2e2bce8494672..26789b0ba6e09 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -67,11 +67,6 @@ static void getRISCFeaturesFromMcpu(const Driver , const 
Arg *A,
   D.Diag(clang::diag::err_drv_unsupported_option_argument)
   << A->getSpelling() << Mcpu;
   }
-
-  if (llvm::RISCV::hasFastUnalignedAccess(Mcpu)) {
-Features.push_back("+unaligned-scalar-mem");
-Features.push_back("+unaligned-vector-mem");
-  }
 }
 
 void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple ,
@@ -82,6 +77,8 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
   if (!getArchFeatures(D, MArch, Features, Args))
 return;
 
+  bool CPUFastUnaligned = false;
+
   // If users give march and mcpu, get std extension feature from MArch
   // and other features (ex. mirco architecture feature) from mcpu
   if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
@@ -90,6 +87,9 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
   CPU = llvm::sys::getHostCPUName();
 
 getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features);
+
+if (llvm::RISCV::hasFastUnalignedAccess(CPU))
+  CPUFastUnaligned = true;
   }
 
   // Handle features corresponding to "-ffixed-X" options
@@ -169,18 +169,23 @@ void riscv::getRISCVTargetFeatures(const Driver , const 
llvm::Triple ,
 Features.push_back("-relax");
   }
 
-  // Android requires fast unaligned access on RISCV64.
-  if (Triple.isAndroid()) {
+  // If -mstrict-align or -mno-strict-align is passed, use it. Otherwise, the
+  // unaligned-*-mem is enabled if the CPU supports it or the target is
+  // Android.
+  if (const Arg *A = Args.getLastArg(options::OPT_mno_strict_align,
+ options::OPT_mstrict_align)) {
+if (A->getOption().matches(options::OPT_mno_strict_align)) {
+  Features.push_back("+unaligned-scalar-mem");
+  Features.push_back("+unaligned-vector-mem");
+} else {
+  Features.push_back("-unaligned-scalar-mem");
+  Features.push_back("-unaligned-vector-mem");
+}
+  } else if (CPUFastUnaligned || Triple.isAndroid()) {
 Features.push_back("+unaligned-scalar-mem");
 Features.push_back("+unaligned-vector-mem");
   }
 
-  // -mstrict-align is default, unless -mno-strict-align is specified.
-  AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
-   options::OPT_mstrict_align, "unaligned-scalar-mem");
-  AddTargetFeature(Args, Features, options::OPT_mno_strict_align,
-   options::OPT_mstrict_align, "unaligned-vector-mem");
-
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits