[clang] [llvm] [AArch64] Add intrinsics for bflaot16 min/max/minnm/maxnm (PR #90105)

2024-05-09 Thread Momchil Velikov via cfe-commits 

momchil-velikov wrote:

Typo in commit message: `bflaot16`

> Variations other than bfloat16 had been already supported.

-> Variations other than bfloat16 are already supported.

https://github.com/llvm/llvm-project/pull/90105
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[clang] [llvm] [AArch64] Add intrinsics for bflaot16 min/max/minnm/maxnm (PR #90105)

2024-04-29 Thread Momchil Velikov via cfe-commits 


@@ -3373,7 +3373,7 @@ let TargetPrefix = "aarch64" in {
   // Multi-vector min/max
   //
 
-  foreach ty = ["f", "s", "u"] in {
+  foreach ty = ["bf", "f", "s", "u"] in {

momchil-velikov wrote:

You could just omit that part. Then the `bfloat` intrinsics would use 
`fmin`/`fmax`/etc in the names without ambiguity, since they are polymorphic.

https://github.com/llvm/llvm-project/pull/90105
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[clang] [llvm] [AArch64] Add intrinsics for bflaot16 min/max/minnm/maxnm (PR #90105)

2024-04-29 Thread Momchil Velikov via cfe-commits 


@@ -3387,7 +3387,7 @@ let TargetPrefix = "aarch64" in {
   // Multi-vector floating point min/max number
   //
 
-  foreach instr = ["fmaxnm", "fminnm"] in {
+  foreach instr = ["fmaxnm", "bfmaxnm", "fminnm", "bfminnm"] in {

momchil-velikov wrote:

Likewise here.

https://github.com/llvm/llvm-project/pull/90105
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[clang] [llvm] [AArch64] Add intrinsics for bflaot16 min/max/minnm/maxnm (PR #90105)

2024-04-29 Thread via cfe-commits 


@@ -109,6 +109,19 @@ define { ,  } 
@multi_vec_max_single_x2_u64(<
   ret { ,  } %res
 }
 
+; BFMAX (Single, x2)
+
+define { ,  } 
@multi_vec_max_single_x2_bf16( %zdn1,  %zdn2,  %zm) {
+; CHECK-LABEL: multi_vec_max_single_x2_bf16:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:// kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:// kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
+; CHECK-NEXT:bfmax { z0.h, z1.h }, { z0.h, z1.h }, z2.h
+; CHECK-NEXT:ret
+  %res = call { ,  } 
@llvm.aarch64.sve.bfmax.single.x2.nxv8bf16( %zdn1,  %zdn2,  %zm)

CarolineConcatto wrote:

I am not sure we should keep this. I understand that in InstriniscAArch64.td 
you are declaring together with previous implementation, but maybe we should 
split it and have one just for BF types

https://github.com/llvm/llvm-project/pull/90105
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[clang] [llvm] [AArch64] Add intrinsics for bflaot16 min/max/minnm/maxnm (PR #90105)

2024-04-29 Thread via cfe-commits 

https://github.com/CarolineConcatto edited 
https://github.com/llvm/llvm-project/pull/90105
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[clang] [llvm] [AArch64] Add intrinsics for bflaot16 min/max/minnm/maxnm (PR #90105)

2024-04-29 Thread via cfe-commits 

https://github.com/CarolineConcatto commented:

It looks good Hassnaa, I am just concern about how we build the llvm-ir 
intrinsic. All the other BF intrinsics don't have the name b + the type size

https://github.com/llvm/llvm-project/pull/90105
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[clang] [llvm] [AArch64] Add intrinsics for bflaot16 min/max/minnm/maxnm (PR #90105)

2024-04-25 Thread via cfe-commits 

llvmbot wrote:



@llvm/pr-subscribers-llvm-ir

@llvm/pr-subscribers-clang

Author: Hassnaa Hamdi (hassnaaHamdi)


Changes

According to specifications in 
[ARM-software/acle/pull/309](https://github.com/ARM-software/acle/pull/309)
Add following intrinsics:

```
// svmax single,multi
svbfloat16x2_t svmax_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm)
svbfloat16x4_t svmax_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm)
svbfloat16x2_t svmax_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm)
svbfloat16x4_t svmax_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm)
```

```
// svmin single,multi
svbfloat16x2_t svmin_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm)
svbfloat16x4_t svmin_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm)
svbfloat16x2_t svmin_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm)
svbfloat16x4_t svmin_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm)
```

```
// svmaxnm single,multi
svbfloat16x2_t svmaxnm_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm)
svbfloat16x4_t svmaxnm_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm)
svbfloat16x2_t svmaxnm_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm)
svbfloat16x4_t svmaxnm_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm)
```

```
// svminnm single,multi
svbfloat16x2_t svminnm_single_bf16_x2(svbfloat16x2_t zdn, svbfloat16_t zm)
svbfloat16x4_t svminnm_single_bf16_x4(svbfloat16x4_t zdn, svbfloat16_t zm)
svbfloat16x2_t svminnm_bf16_x2(svbfloat16x2_t zdn, svbfloat16x2_t zm)
svbfloat16x4_t svminnm_bf16_x4(svbfloat16x4_t zdn, svbfloat16x4_t zm)
```
- Variations other than bfloat16 had been already supported.

---

Patch is 124.44 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/90105.diff


9 Files Affected:

- (modified) clang/include/clang/Basic/arm_sve.td (+28) 
- (modified) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c 
(+145-5) 
- (modified) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c 
(+145-5) 
- (modified) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c 
(+145-5) 
- (modified) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c 
(+145-5) 
- (modified) llvm/include/llvm/IR/IntrinsicsAArch64.td (+2-2) 
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+113-1) 
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll (+125-1) 
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll (+126-1) 


``diff
diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 6cc249837d3f3d..884ca6a3363421 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2111,6 +2111,20 @@ let TargetGuard = "sme2" in {
   defm MIN_MULTI_X4  : MinMaxIntr<"min", "","x4", "444">;
 }
 
+multiclass BFMinMaxIntr {
+  def SVBF # NAME # _SINGLE_X2 : SInst<"sv" # name # "[_single_{d}_x2]", 
"22d", "b", MergeNone, "aarch64_sve_bf" # name # "_single_x2", [IsStreaming], 
[]>;
+  def SVBF # NAME # _SINGLE_X4 : SInst<"sv" # name # "[_single_{d}_x4]", 
"44d", "b", MergeNone, "aarch64_sve_bf" # name # "_single_x4", [IsStreaming], 
[]>;
+
+  def SVBF # NAME # _MULTI_X2 : SInst<"sv" # name # "[_{d}_x2]", "222", "b", 
MergeNone, "aarch64_sve_bf" # name # "_x2", [IsStreaming], []>;
+  def SVBF # NAME # _MULTI_X4 : SInst<"sv" # name # "[_{d}_x4]", "444", "b", 
MergeNone, "aarch64_sve_bf" # name # "_x4", [IsStreaming], []>;
+}
+
+let TargetGuard = "sme2,b16b16" in {
+// == BFMIN / BFMAX ==
+  defm SVMIN : BFMinMaxIntr<"min">;
+  defm SVMAX : BFMinMaxIntr<"max">;
+}
+
 multiclass SInstMinMaxByVector {
   def NAME # _SINGLE_X2 : SInst<"sv" # name # "nm[_single_{d}_x2]", "22d", 
"hfd", MergeNone, "aarch64_sve_f" # name # "nm_single_x2", [IsStreaming], []>;
   def NAME # _SINGLE_X4 : SInst<"sv" # name # "nm[_single_{d}_x4]", "44d", 
"hfd", MergeNone, "aarch64_sve_f" # name # "nm_single_x4", [IsStreaming], []>;
@@ -2125,6 +2139,20 @@ let TargetGuard = "sme2" in {
   defm SVMAXNM : SInstMinMaxByVector<"max">;
 }
 
+multiclass SInstBFMinMaxByVector {
+  def SVBF # NAME # _SINGLE_X2 : SInst<"sv" # name # "[_single_{d}_x2]", 
"22d", "b", MergeNone, "aarch64_sve_bf" # name # "_single_x2", [IsStreaming], 
[]>;
+  def SVBF # NAME # _SINGLE_X4 : SInst<"sv" # name # "[_single_{d}_x4]", 
"44d", "b", MergeNone, "aarch64_sve_bf" # name # "_single_x4", [IsStreaming], 
[]>;
+
+  def SVBF # NAME # _MULTI_X2 : SInst<"sv" # name # "[_{d}_x2]", "222", "b", 
MergeNone, "aarch64_sve_bf" # name # "_x2", [IsStreaming], []>;
+  def SVBF # NAME # _MULTI_X4 : SInst<"sv" # name # "[_{d}_x4]", "444", "b", 
MergeNone, "aarch64_sve_bf" # name # "_x4", [IsStreaming], []>;
+}
+
+let TargetGuard = "sme2,b16b16" in {
+// == BFMINNM / BFMAXNM ==
+  defm SVMINNM : SInstBFMinMaxByVector<"minnm">;
+  defm SVMAXNM : SInstBFMinMaxByVector<"maxnm">;
+}
+
 let TargetGuard = "sme2" in {
   // FRINTA / FRINTM / FRINTN / FRINTP
   def SVRINTA_X2 : SInst<"svrinta[_{d}_x2]", "22", "f", MergeNone, 
"aarch64_sve_frinta_x2", [IsStreaming],