[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/joelkevinjones closed https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/joelkevinjones approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
wxz2020 wrote: Any more comments? Otherwise, we will move forward. Thanks, https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -0,0 +1,1659 @@
+//=- AArch64SchedOryon.td - Qualcomm Oryon CPU 001 ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the scheduling model for Qualcomm Oryon
+// family of processors.
+//
+//===--===//
+
+//===--===//
+// Pipeline Description.
+
+def OryonModel : SchedMachineModel {
+ let IssueWidth= 14;
+ let MicroOpBufferSize = 376;
+ let LoadLatency = 4;
+ let MispredictPenalty = 13; // 13 cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 0; // Do not have a LoopMicroOpBuffer
+ let PostRAScheduler = 1; // Using PostRA sched.
+ let CompleteModel = 1;
+
+ list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+SMEUnsupported.F,
+MTEUnsupported.F,
+PAUnsupported.F,
+[HasPAuth, HasCSSC]);
+}
+
+let SchedModel = OryonModel in {
+
+// Issue ports.
+// IXU has 6 ports p0 ~ p5
+// LSU has 4 ports p6 ~ p9(ls0 ~ ls3), p10/p11(std0, std1) has to work with
ls0~ls3
+// VXU has 4 ports p12 ~ p15
+
+// cross IXU/LSU/VXU resource group for FMOV P41 of VXU
+// I2V
+def ORYONI4FP0 : ProcResource<1>;
+def ORYONI5FP1 : ProcResource<1>;
+// V2I
+def ORYONFP0I4 : ProcResource<1>;
+def ORYONFP1I5 : ProcResource<1>;
+
+// store 1 for normal store instructions
+def ORYONST0 : ProcResource<1>;
+// store 2 for normal store instructions
+def ORYONST1 : ProcResource<1>;
+
+// Port 0: ALU/Indirect/Direct Branch.
+def ORYONP0 : ProcResource<1>;
+
+// Port 1: ALU/Direct Branch.
+def ORYONP1 : ProcResource<1>;
+
+// Port 2: ALU.
+def ORYONP2 : ProcResource<1>;
+
+// Port 3: ALU.
+def ORYONP3 : ProcResource<1>;
+
+// Port 4: ALU.
+def ORYONP4 : ProcResource<1> {
+let Super = ORYONI4FP0;
+let Super = ORYONFP0I4; }
+
+// Port 5: ALU.
+def ORYONP5 : ProcResource<1> {
+let Super = ORYONI5FP1;
+let Super = ORYONFP1I5; }
+
+// Port 6: Load/Store. LS0
+def ORYONP6 : ProcResource<1> {
+let Super = ORYONST0; }
+
+// Port 7: Load/store. LS1
+def ORYONP7 : ProcResource<1> {
+let Super = ORYONST0; }
+
+// Port 8: Load/Store. LS2
+def ORYONP8 : ProcResource<1> {
+let Super = ORYONST1; }
+
+// Port 9: Load/store. LS3
+def ORYONP9 : ProcResource<1> {
+let Super = ORYONST1; }
+
+// Port 10: Load/Store. STD0
+def ORYONP10SD0 : ProcResource<1> {
+let Super = ORYONST0; }
+
+// Port 11: Load/store. STD1
+def ORYONP11SD1 : ProcResource<1> {
+let Super = ORYONST1; }
+
+// Port 12: FP/Neon/SIMD/Crypto.
+def ORYONP12FP0 : ProcResource<1> {
+let Super = ORYONI4FP0;
+let Super = ORYONFP0I4; }
+
+// Port 13: FP/Neon/SIMD/Crypto.
+def ORYONP13FP1 : ProcResource<1> {
+let Super = ORYONI5FP1;
+let Super = ORYONFP1I5; }
+
+// Port 14: FP/Neon/SIMD/Crypto.
+def ORYONP14FP2 : ProcResource<1>;
+
+// Port 15: FP/Neon/SIMD/Crypto.
+def ORYONP15FP3 : ProcResource<1>;
+
+// Define groups for the functional units on each issue port. Each group
+// created will be used by a WriteRes.
+
+// Integer add/shift/logical/misc. instructions on port I0/I1/I2/I3/I4/I5.
+def ORYONI012345 : ProcResGroup<[ORYONP0, ORYONP1, ORYONP2,
+ ORYONP3, ORYONP4, ORYONP5]> {
+ let BufferSize = 120;
+}
+
+// Direct Conditional Branch instructions on ports I0/I1.
+def ORYONI01 : ProcResGroup<[ORYONP0, ORYONP1]> {
+ let BufferSize = 40;
+}
+
+// Indirect/crypto Conditional Branch instructions on ports I0.
+def ORYONI0 : ProcResGroup<[ORYONP0]> {
+ let BufferSize = 20;
+}
+
+// Crypto/CRC/PAU instructions on ports I2.
+def ORYONI2 : ProcResGroup<[ORYONP2]> {
+ let BufferSize = 20;
+}
+
+// Multiply/Multiply-ADD instructions on ports I4/I5.
+def ORYONI45 : ProcResGroup<[ORYONP4, ORYONP5]> {
+ let BufferSize = 40;
+}
+
+// Divide instructions on ports I5.
+def ORYONI5 : ProcResGroup<[ORYONP5]> {
+ let BufferSize = 20;
+}
+
+// Comparison instructions on ports I0/I1/I2/I3.
+def ORYONI0123 : ProcResGroup<[ORYONP0, ORYONP1,
+ORYONP2, ORYONP3]> {
+ let BufferSize = 80;
+}
+
+// Load instructions on ports P6/P7/P8/P9.
+def ORYONLD : ProcResGroup<[ORYONP6, ORYONP7, ORYONP8, ORYONP9]> {
+ let BufferSize = 64;
+}
+
+// Store instructions on combo of STA/STD pipes
+def ORYONST : ProcResGroup<[ORYONST0, ORYONST1]> {
+let BufferSize = 64;
+}
+
+// Arithmetic and CRYP-AED ASIMD/FP instructions on ports FP0/FP1/FP2/FP3.
+def ORYONFP0123 : ProcResGroup<[ORYONP12FP0,
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -0,0 +1,1659 @@
+//=- AArch64SchedOryon.td - Qualcomm Oryon CPU 001 ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the scheduling model for Qualcomm Oryon
+// family of processors.
+//
+//===--===//
+
+//===--===//
+// Pipeline Description.
+
+def OryonModel : SchedMachineModel {
+ let IssueWidth= 14;
+ let MicroOpBufferSize = 376;
+ let LoadLatency = 4;
+ let MispredictPenalty = 13; // 13 cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 0; // Do not have a LoopMicroOpBuffer
+ let PostRAScheduler = 1; // Using PostRA sched.
+ let CompleteModel = 1;
+
+ list UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+SMEUnsupported.F,
+MTEUnsupported.F,
+PAUnsupported.F,
+[HasPAuth, HasCSSC]);
+}
+
+let SchedModel = OryonModel in {
+
+// Issue ports.
+// IXU has 6 ports p0 ~ p5
+// LSU has 4 ports p6 ~ p9(ls0 ~ ls3), p10/p11(std0, std1) has to work with
ls0~ls3
+// VXU has 4 ports p12 ~ p15
+
+// cross IXU/LSU/VXU resource group for FMOV P41 of VXU
+// I2V
+def ORYONI4FP0 : ProcResource<1>;
+def ORYONI5FP1 : ProcResource<1>;
+// V2I
+def ORYONFP0I4 : ProcResource<1>;
+def ORYONFP1I5 : ProcResource<1>;
+
+// store 1 for normal store instructions
+def ORYONST0 : ProcResource<1>;
+// store 2 for normal store instructions
+def ORYONST1 : ProcResource<1>;
+
+// Port 0: ALU/Indirect/Direct Branch.
+def ORYONP0 : ProcResource<1>;
+
+// Port 1: ALU/Direct Branch.
+def ORYONP1 : ProcResource<1>;
+
+// Port 2: ALU.
+def ORYONP2 : ProcResource<1>;
+
+// Port 3: ALU.
+def ORYONP3 : ProcResource<1>;
+
+// Port 4: ALU.
+def ORYONP4 : ProcResource<1> {
+let Super = ORYONI4FP0;
+let Super = ORYONFP0I4; }
+
+// Port 5: ALU.
+def ORYONP5 : ProcResource<1> {
+let Super = ORYONI5FP1;
+let Super = ORYONFP1I5; }
+
+// Port 6: Load/Store. LS0
+def ORYONP6 : ProcResource<1> {
+let Super = ORYONST0; }
+
+// Port 7: Load/store. LS1
+def ORYONP7 : ProcResource<1> {
+let Super = ORYONST0; }
+
+// Port 8: Load/Store. LS2
+def ORYONP8 : ProcResource<1> {
+let Super = ORYONST1; }
+
+// Port 9: Load/store. LS3
+def ORYONP9 : ProcResource<1> {
+let Super = ORYONST1; }
+
+// Port 10: Load/Store. STD0
+def ORYONP10SD0 : ProcResource<1> {
+let Super = ORYONST0; }
+
+// Port 11: Load/store. STD1
+def ORYONP11SD1 : ProcResource<1> {
+let Super = ORYONST1; }
+
+// Port 12: FP/Neon/SIMD/Crypto.
+def ORYONP12FP0 : ProcResource<1> {
+let Super = ORYONI4FP0;
+let Super = ORYONFP0I4; }
+
+// Port 13: FP/Neon/SIMD/Crypto.
+def ORYONP13FP1 : ProcResource<1> {
+let Super = ORYONI5FP1;
+let Super = ORYONFP1I5; }
+
+// Port 14: FP/Neon/SIMD/Crypto.
+def ORYONP14FP2 : ProcResource<1>;
+
+// Port 15: FP/Neon/SIMD/Crypto.
+def ORYONP15FP3 : ProcResource<1>;
+
+// Define groups for the functional units on each issue port. Each group
+// created will be used by a WriteRes.
+
+// Integer add/shift/logical/misc. instructions on port I0/I1/I2/I3/I4/I5.
+def ORYONI012345 : ProcResGroup<[ORYONP0, ORYONP1, ORYONP2,
+ ORYONP3, ORYONP4, ORYONP5]> {
+ let BufferSize = 120;
+}
+
+// Direct Conditional Branch instructions on ports I0/I1.
+def ORYONI01 : ProcResGroup<[ORYONP0, ORYONP1]> {
+ let BufferSize = 40;
+}
+
+// Indirect/crypto Conditional Branch instructions on ports I0.
+def ORYONI0 : ProcResGroup<[ORYONP0]> {
+ let BufferSize = 20;
+}
+
+// Crypto/CRC/PAU instructions on ports I2.
+def ORYONI2 : ProcResGroup<[ORYONP2]> {
+ let BufferSize = 20;
+}
+
+// Multiply/Multiply-ADD instructions on ports I4/I5.
+def ORYONI45 : ProcResGroup<[ORYONP4, ORYONP5]> {
+ let BufferSize = 40;
+}
+
+// Divide instructions on ports I5.
+def ORYONI5 : ProcResGroup<[ORYONP5]> {
+ let BufferSize = 20;
+}
+
+// Comparison instructions on ports I0/I1/I2/I3.
+def ORYONI0123 : ProcResGroup<[ORYONP0, ORYONP1,
+ORYONP2, ORYONP3]> {
+ let BufferSize = 80;
+}
+
+// Load instructions on ports P6/P7/P8/P9.
+def ORYONLD : ProcResGroup<[ORYONP6, ORYONP7, ORYONP8, ORYONP9]> {
+ let BufferSize = 64;
+}
+
+// Store instructions on combo of STA/STD pipes
+def ORYONST : ProcResGroup<[ORYONST0, ORYONST1]> {
+let BufferSize = 64;
+}
+
+// Arithmetic and CRYP-AED ASIMD/FP instructions on ports FP0/FP1/FP2/FP3.
+def ORYONFP0123 : ProcResGroup<[ORYONP12FP0,
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/kuhar updated https://github.com/llvm/llvm-project/pull/91022
>From 8aebe46d7fdd15f02a9716718f53b03056ef0d19 Mon Sep 17 00:00:00 2001
From: Wei Zhao
Date: Fri, 3 May 2024 22:01:58 +
Subject: [PATCH 1/3] [AArch64] Add support for Qualcomm Oryon processor
---
clang/test/Driver/aarch64-oryon-1.c | 19 +
clang/test/Misc/target-invalid-cpu-note.c |4 +-
.../llvm/TargetParser/AArch64TargetParser.h |5 +
llvm/lib/Target/AArch64/AArch64.td|5 +
llvm/lib/Target/AArch64/AArch64Processors.td | 30 +
llvm/lib/Target/AArch64/AArch64SchedOryon.td | 1727 +
llvm/lib/Target/AArch64/AArch64Subtarget.cpp |7 +
llvm/lib/TargetParser/Host.cpp|1 +
llvm/unittests/TargetParser/Host.cpp |3 +
.../TargetParser/TargetParserTest.cpp | 16 +-
10 files changed, 1813 insertions(+), 4 deletions(-)
create mode 100644 clang/test/Driver/aarch64-oryon-1.c
create mode 100644 llvm/lib/Target/AArch64/AArch64SchedOryon.td
diff --git a/clang/test/Driver/aarch64-oryon-1.c
b/clang/test/Driver/aarch64-oryon-1.c
new file mode 100644
index 0..952ba5df74baf
--- /dev/null
+++ b/clang/test/Driver/aarch64-oryon-1.c
@@ -0,0 +1,19 @@
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1
| FileCheck -check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix-TUNE %s
+// Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"oryon-1" "-target-feature" "+v8.6a"
+// Phoenix-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic"
+
+// RUN: %clang -target arm64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix-TUNE %s
+// ARM64-Phoenix: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "oryon-1"
"-target-feature" "+v8.6a"
+// ARM64-Phoenix-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"
+
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -mtune=cortex-a53 -### -c %s 2>&1
| FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// RUN: %clang -target aarch64 -mtune=cortex-a53 -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// MCPU-MTUNE-Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"oryon-1"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3a..a71ebd6a023e7 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2,
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10,
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17,
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4,
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx,
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1,
ampere1a, ampere1b, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/wxz2020 updated
https://github.com/llvm/llvm-project/pull/91022
>From 8aebe46d7fdd15f02a9716718f53b03056ef0d19 Mon Sep 17 00:00:00 2001
From: Wei Zhao
Date: Fri, 3 May 2024 22:01:58 +
Subject: [PATCH 1/3] [AArch64] Add support for Qualcomm Oryon processor
---
clang/test/Driver/aarch64-oryon-1.c | 19 +
clang/test/Misc/target-invalid-cpu-note.c |4 +-
.../llvm/TargetParser/AArch64TargetParser.h |5 +
llvm/lib/Target/AArch64/AArch64.td|5 +
llvm/lib/Target/AArch64/AArch64Processors.td | 30 +
llvm/lib/Target/AArch64/AArch64SchedOryon.td | 1727 +
llvm/lib/Target/AArch64/AArch64Subtarget.cpp |7 +
llvm/lib/TargetParser/Host.cpp|1 +
llvm/unittests/TargetParser/Host.cpp |3 +
.../TargetParser/TargetParserTest.cpp | 16 +-
10 files changed, 1813 insertions(+), 4 deletions(-)
create mode 100644 clang/test/Driver/aarch64-oryon-1.c
create mode 100644 llvm/lib/Target/AArch64/AArch64SchedOryon.td
diff --git a/clang/test/Driver/aarch64-oryon-1.c
b/clang/test/Driver/aarch64-oryon-1.c
new file mode 100644
index 0..952ba5df74baf
--- /dev/null
+++ b/clang/test/Driver/aarch64-oryon-1.c
@@ -0,0 +1,19 @@
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1
| FileCheck -check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix-TUNE %s
+// Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"oryon-1" "-target-feature" "+v8.6a"
+// Phoenix-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic"
+
+// RUN: %clang -target arm64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix-TUNE %s
+// ARM64-Phoenix: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "oryon-1"
"-target-feature" "+v8.6a"
+// ARM64-Phoenix-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"
+
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -mtune=cortex-a53 -### -c %s 2>&1
| FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// RUN: %clang -target aarch64 -mtune=cortex-a53 -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// MCPU-MTUNE-Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"oryon-1"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3a..a71ebd6a023e7 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2,
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10,
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17,
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4,
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx,
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1,
ampere1a, ampere1b, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -0,0 +1,1664 @@
+//=- AArch64SchedOryon.td - Nuvia Inc Oryon CPU 001 ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the scheduling model for Nuvia Inc Oryon
+// family of processors.
+//
+//===--===//
+
+//===--===//
+// Pipeline Description.
+
+def OryonModel : SchedMachineModel {
+ let IssueWidth= 14; // 14 micro-ops dispatched at a time.
IXU=6, LSU=4, VXU=4
+ let MicroOpBufferSize = 376; // 192 (48x4) entries in micro-op re-order
buffer in VXU.
+ // 120 ((20+20)x3) entries in micro-op
re-order buffer in IXU
+ // 64 (16+16)x2 re-order buffer in LSU
+ // total 373
+ let LoadLatency = 4; // 4 cycle Load-to-use from L1D$
+ // LSU=5 NEON load
+ let MispredictPenalty = 13; // 13 cycles for mispredicted branch.
+ // Determined via a mix of micro-arch details and experimentation.
+ let LoopMicroOpBufferSize = 0; // Do not have a LoopMicroOpBuffer
asb wrote:
Thanks Joel. FWIW there's been some development in this setting since I posted
this. 54e52aa5ebe68de122a3fe6064e0abef97f6b8e0 reduced the
LoopMicroOpBufferSize for Zen to 96 (Zen3) and 108 (Zen4) so they're no longer
outliers with much larger values than anyone else.
I totally agree that in-order cores will be more sensitive to scheduling
changes in general. I'll note that as runtime and partial loop unrolling are
disabled unless this is set, I'd see the impact as slightly more than just
scheduling. In some cases further optimisations trigger on the (partially)
unrolled IR which can lead to better code. e.g. setting this reduced dynamic
instruction count on some SPEC benchmarks for a RISC-V OoO scheduling model. If
you do experiment with the value I'd be interested in your findings.
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -0,0 +1,1664 @@
+//=- AArch64SchedOryon.td - Nuvia Inc Oryon CPU 001 ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the scheduling model for Nuvia Inc Oryon
+// family of processors.
+//
+//===--===//
+
+//===--===//
+// Pipeline Description.
+
+def OryonModel : SchedMachineModel {
+ let IssueWidth= 14; // 14 micro-ops dispatched at a time.
IXU=6, LSU=4, VXU=4
+ let MicroOpBufferSize = 376; // 192 (48x4) entries in micro-op re-order
buffer in VXU.
+ // 120 ((20+20)x3) entries in micro-op
re-order buffer in IXU
+ // 64 (16+16)x2 re-order buffer in LSU
+ // total 373
+ let LoadLatency = 4; // 4 cycle Load-to-use from L1D$
+ // LSU=5 NEON load
+ let MispredictPenalty = 13; // 13 cycles for mispredicted branch.
+ // Determined via a mix of micro-arch details and experimentation.
+ let LoopMicroOpBufferSize = 0; // Do not have a LoopMicroOpBuffer
joelkevinjones wrote:
Thanks for this attention to detail and bringing up this issue. We had a
discussion internally about this setting. At one extreme would be to try to
specify all details relevant to instruction scheduling. For micro-op buffers,
to be completely architecturally accurate, a scalar value would be
insufficient. We certainly wouldn't sign up to extend LLVM in this fashion. We
decided to take the other extreme here. While not explicitly varying
LoopMcroOpBufferSize, our benchmarking of the effects of varying scheduling
settings showed little effect. Our team hasn't done any experiments on
non-AArch64 targets varying this specific setting recently. I will the
submitter decide what to do. We may decide to do some experiments varying this
value. If the processor is in order, it would matter more.
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/asb edited https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/asb edited https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -0,0 +1,1664 @@
+//=- AArch64SchedOryon.td - Nuvia Inc Oryon CPU 001 ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the scheduling model for Nuvia Inc Oryon
+// family of processors.
+//
+//===--===//
+
+//===--===//
+// Pipeline Description.
+
+def OryonModel : SchedMachineModel {
+ let IssueWidth= 14; // 14 micro-ops dispatched at a time.
IXU=6, LSU=4, VXU=4
+ let MicroOpBufferSize = 376; // 192 (48x4) entries in micro-op re-order
buffer in VXU.
+ // 120 ((20+20)x3) entries in micro-op
re-order buffer in IXU
+ // 64 (16+16)x2 re-order buffer in LSU
+ // total 373
+ let LoadLatency = 4; // 4 cycle Load-to-use from L1D$
+ // LSU=5 NEON load
+ let MispredictPenalty = 13; // 13 cycles for mispredicted branch.
+ // Determined via a mix of micro-arch details and experimentation.
+ let LoopMicroOpBufferSize = 0; // Do not have a LoopMicroOpBuffer
asb wrote:
Although it may not be microarchitecturally accurate, I wonder if you've
benchmarked setting LoopMicroOpBufferSize to a non-zero value. Unless targets
override it, partial and runtime loop unrolling aren't enabled unless
LoopMicroOpBufferSize is non-zero (and this is the only way it's currently
queried and used). In AArch64's case, they only override that decision f or
in-order scheduling models. If you look at other models that set this value
in-tree you'll see it's become somewhat divorced from microarchitectual reality
- e.g. a number of the AArch64 models setting it based on instruction queue
size or noting they just copied the value from the A57 model. On the X86 side,
it's set to 50-72 for the modern Intel X86 and even up to 512 for Zen (noting
it should be higher, but compile time impact is too high).
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
jthackray wrote:
Thanks for removing those. Can't see anything else obviously wrong. LGTM,
Approved.
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
wxz2020 wrote:
Thanks for the FIXME prompt, I got it fixed and did some cleaning, Just
uploaded the code.
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Wei Zhao (wxz2020)
Changes
Oryon is an ARM V8 AArch64 CPU from Qualcomm.
---
Patch is 73.24 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/91022.diff
10 Files Affected:
- (added) clang/test/Driver/aarch64-oryon-1.c (+19)
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2)
- (modified) llvm/include/llvm/TargetParser/AArch64TargetParser.h (+5)
- (modified) llvm/lib/Target/AArch64/AArch64.td (+5)
- (modified) llvm/lib/Target/AArch64/AArch64Processors.td (+30)
- (added) llvm/lib/Target/AArch64/AArch64SchedOryon.td (+1664)
- (modified) llvm/lib/Target/AArch64/AArch64Subtarget.cpp (+7)
- (modified) llvm/lib/TargetParser/Host.cpp (+1)
- (modified) llvm/unittests/TargetParser/Host.cpp (+3)
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+14-2)
``diff
diff --git a/clang/test/Driver/aarch64-oryon-1.c
b/clang/test/Driver/aarch64-oryon-1.c
new file mode 100644
index ..952ba5df74ba
--- /dev/null
+++ b/clang/test/Driver/aarch64-oryon-1.c
@@ -0,0 +1,19 @@
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1
| FileCheck -check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix-TUNE %s
+// Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"oryon-1" "-target-feature" "+v8.6a"
+// Phoenix-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic"
+
+// RUN: %clang -target arm64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix-TUNE %s
+// ARM64-Phoenix: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "oryon-1"
"-target-feature" "+v8.6a"
+// ARM64-Phoenix-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"
+
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -mtune=cortex-a53 -### -c %s 2>&1
| FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// RUN: %clang -target aarch64 -mtune=cortex-a53 -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// MCPU-MTUNE-Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"oryon-1"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3..a71ebd6a023e 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2,
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10,
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17,
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4,
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx,
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1,
ampere1a, ampere1b, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2,
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9,
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/wxz2020 updated
https://github.com/llvm/llvm-project/pull/91022
>From 8aebe46d7fdd15f02a9716718f53b03056ef0d19 Mon Sep 17 00:00:00 2001
From: Wei Zhao
Date: Fri, 3 May 2024 22:01:58 +
Subject: [PATCH 1/2] [AArch64] Add support for Qualcomm Oryon processor
---
clang/test/Driver/aarch64-oryon-1.c | 19 +
clang/test/Misc/target-invalid-cpu-note.c |4 +-
.../llvm/TargetParser/AArch64TargetParser.h |5 +
llvm/lib/Target/AArch64/AArch64.td|5 +
llvm/lib/Target/AArch64/AArch64Processors.td | 30 +
llvm/lib/Target/AArch64/AArch64SchedOryon.td | 1727 +
llvm/lib/Target/AArch64/AArch64Subtarget.cpp |7 +
llvm/lib/TargetParser/Host.cpp|1 +
llvm/unittests/TargetParser/Host.cpp |3 +
.../TargetParser/TargetParserTest.cpp | 16 +-
10 files changed, 1813 insertions(+), 4 deletions(-)
create mode 100644 clang/test/Driver/aarch64-oryon-1.c
create mode 100644 llvm/lib/Target/AArch64/AArch64SchedOryon.td
diff --git a/clang/test/Driver/aarch64-oryon-1.c
b/clang/test/Driver/aarch64-oryon-1.c
new file mode 100644
index ..952ba5df74ba
--- /dev/null
+++ b/clang/test/Driver/aarch64-oryon-1.c
@@ -0,0 +1,19 @@
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1
| FileCheck -check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix-TUNE %s
+// Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"oryon-1" "-target-feature" "+v8.6a"
+// Phoenix-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic"
+
+// RUN: %clang -target arm64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix-TUNE %s
+// ARM64-Phoenix: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "oryon-1"
"-target-feature" "+v8.6a"
+// ARM64-Phoenix-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"
+
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -mtune=cortex-a53 -### -c %s 2>&1
| FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// RUN: %clang -target aarch64 -mtune=cortex-a53 -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// MCPU-MTUNE-Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"oryon-1"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3..a71ebd6a023e 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2,
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10,
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17,
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4,
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx,
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1,
ampere1a, ampere1b, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
jthackray wrote:
Oh yes. Thanks.
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/jthackray approved this pull request. LGTM. (You've still got a few FIXMEs in AArch64SchedOryon.td, I assume you know about these) https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
wxz2020 wrote:
It is referenced in AArch64SchedOryon.td on line 33. The Oryon CPU does not
support MTE.
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/jthackray edited https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
@@ -85,6 +85,10 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
jthackray wrote:
I can't see that MTEUnsupported is referenced from elsewhere in this commit -
superfluous? If so, remove. Thanks.
https://github.com/llvm/llvm-project/pull/91022
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[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
pinskia wrote: Note the corresponding GCC patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650664.html https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)
https://github.com/wxz2020 created
https://github.com/llvm/llvm-project/pull/91022
Oryon is an ARM V8 AArch64 CPU from Qualcomm.
>From 8aebe46d7fdd15f02a9716718f53b03056ef0d19 Mon Sep 17 00:00:00 2001
From: Wei Zhao
Date: Fri, 3 May 2024 22:01:58 +
Subject: [PATCH] [AArch64] Add support for Qualcomm Oryon processor
---
clang/test/Driver/aarch64-oryon-1.c | 19 +
clang/test/Misc/target-invalid-cpu-note.c |4 +-
.../llvm/TargetParser/AArch64TargetParser.h |5 +
llvm/lib/Target/AArch64/AArch64.td|5 +
llvm/lib/Target/AArch64/AArch64Processors.td | 30 +
llvm/lib/Target/AArch64/AArch64SchedOryon.td | 1727 +
llvm/lib/Target/AArch64/AArch64Subtarget.cpp |7 +
llvm/lib/TargetParser/Host.cpp|1 +
llvm/unittests/TargetParser/Host.cpp |3 +
.../TargetParser/TargetParserTest.cpp | 16 +-
10 files changed, 1813 insertions(+), 4 deletions(-)
create mode 100644 clang/test/Driver/aarch64-oryon-1.c
create mode 100644 llvm/lib/Target/AArch64/AArch64SchedOryon.td
diff --git a/clang/test/Driver/aarch64-oryon-1.c
b/clang/test/Driver/aarch64-oryon-1.c
new file mode 100644
index 00..952ba5df74bafe
--- /dev/null
+++ b/clang/test/Driver/aarch64-oryon-1.c
@@ -0,0 +1,19 @@
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix %s
+// RUN: %clang -target aarch64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1
| FileCheck -check-prefix=Phoenix-TUNE %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=Phoenix-TUNE %s
+// Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"oryon-1" "-target-feature" "+v8.6a"
+// Phoenix-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu"
"generic"
+
+// RUN: %clang -target arm64 -mcpu=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix %s
+// RUN: %clang -target arm64 -mtune=oryon-1 -### -c %s 2>&1 | FileCheck
-check-prefix=ARM64-Phoenix-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=oryon-1 -### -c %s 2>&1 |
FileCheck -check-prefix=ARM64-Phoenix-TUNE %s
+// ARM64-Phoenix: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "oryon-1"
"-target-feature" "+v8.6a"
+// ARM64-Phoenix-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu"
"generic"
+
+// RUN: %clang -target aarch64 -mcpu=oryon-1 -mtune=cortex-a53 -### -c %s 2>&1
| FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// RUN: %clang -target aarch64 -mtune=cortex-a53 -mcpu=oryon-1 -### -c %s
2>&1 | FileCheck -check-prefix=MCPU-MTUNE-Phoenix %s
+// MCPU-MTUNE-Phoenix: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"oryon-1"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3a3..a71ebd6a023e79 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1,
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2,
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10,
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17,
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4,
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx,
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1,
ampere1a, ampere1b, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35,
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57,
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710,
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1,
cortex-x1c, cortex-x2,
