[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-20 Thread Momchil Velikov via cfe-commits 

https://github.com/momchil-velikov closed 
https://github.com/llvm/llvm-project/pull/75596
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[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-19 Thread Momchil Velikov via cfe-commits 


@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
   def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1, 
ImmCheck2_4_Mul2>]>;
 }
 
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {

momchil-velikov wrote:

Done.

https://github.com/llvm/llvm-project/pull/75596
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[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-19 Thread via cfe-commits 


@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
   def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1, 
ImmCheck2_4_Mul2>]>;
 }
 
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {

CarolineConcatto wrote:

I do believe we should add:
__arm_streaming_compatible; 
in the tests.

svbfloat16_t test_svadd_bf16_m(svbool_t pg, svbfloat16_t op1, svbfloat16_t op2) 
  __arm_streaming_compatible
{
  return SVE_ACLE_FUNC(svadd, _bf16, _m)(pg, op1, op2);
}

https://github.com/llvm/llvm-project/pull/75596
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[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-19 Thread Momchil Velikov via cfe-commits 

momchil-velikov wrote:

Rebased the clear the test run.

https://github.com/llvm/llvm-project/pull/75596
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[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-19 Thread Momchil Velikov via cfe-commits 

https://github.com/momchil-velikov updated 
https://github.com/llvm/llvm-project/pull/75596

>From 04a03eae3fcbdd57257ce3867615ec6be9d84e53 Mon Sep 17 00:00:00 2001
From: Momchil Velikov 
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of SVE
 bfloat instructions

According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en
all of the affected instruction encodings now require

(FEAT_SVE2 or FEAT_SME2) and FEAT_SVE_B16B16
---
 clang/include/clang/Basic/arm_sve.td  |  2 +-
 .../acle_sve2p1_bfadd.c   | 11 ++--
 .../acle_sve2p1_bfmax.c   | 11 ++--
 .../acle_sve2p1_bfmaxnm.c | 11 ++--
 .../acle_sve2p1_bfmin.c   | 11 ++--
 .../acle_sve2p1_bfminnm.c | 11 ++--
 .../acle_sve2p1_bfmla.c   | 11 ++--
 .../acle_sve2p1_bfmls.c   | 11 ++--
 .../acle_sve2p1_bfmul.c   | 11 ++--
 .../acle_sve2p1_bfsub.c   | 11 ++--
 llvm/lib/Target/AArch64/AArch64.td|  4 +-
 .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 ++--
 llvm/test/MC/AArch64/SVE2p1/bfadd.s   | 43 ++--
 llvm/test/MC/AArch64/SVE2p1/bfclamp.s | 32 
 llvm/test/MC/AArch64/SVE2p1/bfmax.s   | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmin.s   | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfminnm.s | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmla.s   | 44 +---
 llvm/test/MC/AArch64/SVE2p1/bfmls.s   | 45 +---
 llvm/test/MC/AArch64/SVE2p1/bfmul.s   | 51 +++
 llvm/test/MC/AArch64/SVE2p1/bfsub.s   | 43 ++--
 22 files changed, 311 insertions(+), 198 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 98d7028eb28309..e84d6e5e4cc602 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
   def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1, 
ImmCheck2_4_Mul2>]>;
 }
 
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
 defm SVMUL_BF  : SInstZPZZ<"svmul",  "b", "aarch64_sve_fmul",   
"aarch64_sve_fmul_u">;
 defm SVADD_BF  : SInstZPZZ<"svadd",  "b", "aarch64_sve_fadd",   
"aarch64_sve_fadd_u">;
 defm SVSUB_BF  : SInstZPZZ<"svsub",  "b", "aarch64_sve_fsub",   
"aarch64_sve_fsub_u">;
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
index 327c4f078872b3..a3026fee3f6d29 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
@@ -1,10 +1,11 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | 
FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | 
FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - %s

[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-18 Thread Momchil Velikov via cfe-commits 

https://github.com/momchil-velikov updated 
https://github.com/llvm/llvm-project/pull/75596

>From fc5c82e61efef3f1cd2f6606b12c358637a687f5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov 
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of SVE
 bfloat instructions

According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en
all of the affected instruction encodings now require

(FEAT_SVE2 or FEAT_SME2) and FEAT_SVE_B16B16
---
 clang/include/clang/Basic/arm_sve.td  |  2 +-
 .../acle_sve2p1_bfadd.c   | 11 ++--
 .../acle_sve2p1_bfmax.c   | 11 ++--
 .../acle_sve2p1_bfmaxnm.c | 11 ++--
 .../acle_sve2p1_bfmin.c   | 11 ++--
 .../acle_sve2p1_bfminnm.c | 11 ++--
 .../acle_sve2p1_bfmla.c   | 11 ++--
 .../acle_sve2p1_bfmls.c   | 11 ++--
 .../acle_sve2p1_bfmul.c   | 11 ++--
 .../acle_sve2p1_bfsub.c   | 11 ++--
 llvm/lib/Target/AArch64/AArch64.td|  4 +-
 .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 ++--
 llvm/test/MC/AArch64/SVE2p1/bfadd.s   | 43 ++--
 llvm/test/MC/AArch64/SVE2p1/bfclamp.s | 32 
 llvm/test/MC/AArch64/SVE2p1/bfmax.s   | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmin.s   | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfminnm.s | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmla.s   | 44 +---
 llvm/test/MC/AArch64/SVE2p1/bfmls.s   | 45 +---
 llvm/test/MC/AArch64/SVE2p1/bfmul.s   | 51 +++
 llvm/test/MC/AArch64/SVE2p1/bfsub.s   | 43 ++--
 22 files changed, 311 insertions(+), 198 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 98d7028eb28309..e84d6e5e4cc602 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
   def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1, 
ImmCheck2_4_Mul2>]>;
 }
 
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
 defm SVMUL_BF  : SInstZPZZ<"svmul",  "b", "aarch64_sve_fmul",   
"aarch64_sve_fmul_u">;
 defm SVADD_BF  : SInstZPZZ<"svadd",  "b", "aarch64_sve_fadd",   
"aarch64_sve_fadd_u">;
 defm SVSUB_BF  : SInstZPZZ<"svsub",  "b", "aarch64_sve_fsub",   
"aarch64_sve_fsub_u">;
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
index 327c4f078872b3..a3026fee3f6d29 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
@@ -1,10 +1,11 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | 
FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | 
FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - %s

[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-15 Thread Sander de Smalen via cfe-commits 


@@ -2066,7 +2066,7 @@ let TargetGuard = "sve2p1|sme2" in {
   def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "", 
[IsOverloadNone, IsStreamingCompatible]>;
 }
 
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {

sdesmalen-arm wrote:

nit: Github doesn't allow me to select the right line, but the comment on line 
2083 is no longer correct.

https://github.com/llvm/llvm-project/pull/75596
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[clang] [llvm] [AArch64] Update target feature requirements of SVE bfloat instructions (PR #75596)

2023-12-15 Thread Momchil Velikov via cfe-commits 

https://github.com/momchil-velikov created 
https://github.com/llvm/llvm-project/pull/75596

According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en all of the 
affected instruction encodings now require

(FEAT_SVE2 or FEAT_SME2) and FEAT_SVE_B16B16

>From fa5fbcb55eceb02ea9d516922cfa3a7e23ec8faf Mon Sep 17 00:00:00 2001
From: Momchil Velikov 
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH] [AArch64] Update target feature requirements of SVE bfloat
 instructions

According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en
all of the affected instruction encodings now require

(FEAT_SVE2 or FEAT_SME2) and FEAT_SVE_B16B16
---
 clang/include/clang/Basic/arm_sve.td  |  2 +-
 .../acle_sve2p1_bfadd.c   | 11 ++--
 .../acle_sve2p1_bfmax.c   | 11 ++--
 .../acle_sve2p1_bfmaxnm.c | 11 ++--
 .../acle_sve2p1_bfmin.c   | 11 ++--
 .../acle_sve2p1_bfminnm.c | 11 ++--
 .../acle_sve2p1_bfmla.c   | 11 ++--
 .../acle_sve2p1_bfmls.c   | 11 ++--
 .../acle_sve2p1_bfmul.c   | 11 ++--
 .../acle_sve2p1_bfsub.c   | 11 ++--
 llvm/lib/Target/AArch64/AArch64.td|  4 +-
 .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 10 ++--
 llvm/test/MC/AArch64/SVE2p1/bfadd.s   | 43 ++--
 llvm/test/MC/AArch64/SVE2p1/bfclamp.s | 32 
 llvm/test/MC/AArch64/SVE2p1/bfmax.s   | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmin.s   | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfminnm.s | 34 -
 llvm/test/MC/AArch64/SVE2p1/bfmla.s   | 44 +---
 llvm/test/MC/AArch64/SVE2p1/bfmls.s   | 45 +---
 llvm/test/MC/AArch64/SVE2p1/bfmul.s   | 51 +++
 llvm/test/MC/AArch64/SVE2p1/bfsub.s   | 43 ++--
 22 files changed, 311 insertions(+), 198 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index aa9b105364a51a..b53409a3e1656a 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2066,7 +2066,7 @@ let TargetGuard = "sve2p1|sme2" in {
   def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "", 
[IsOverloadNone, IsStreamingCompatible]>;
 }
 
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
 defm SVMUL_BF  : SInstZPZZ<"svmul",  "b", "aarch64_sve_fmul",   
"aarch64_sve_fmul_u">;
 defm SVADD_BF  : SInstZPZZ<"svadd",  "b", "aarch64_sve_fadd",   
"aarch64_sve_fadd_u">;
 defm SVSUB_BF  : SInstZPZZ<"svsub",  "b", "aarch64_sve_fsub",   
"aarch64_sve_fsub_u">;
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
index 327c4f078872b3..a3026fee3f6d29 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfadd.c
@@ -1,10 +1,11 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | 
FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -target-feature +b16b16 -S -disable-O0-optnone -Werror 
-Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | 
FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 
-target-feature +b16b16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DS