[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-06-28 Thread Piyou Chen via cfe-commits 

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786

>From 937fecdd1a95baf99ca42ea832efac885aef720e Mon Sep 17 00:00:00 2001
From: Piyou Chen 
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/2] [RISCV] Add groupid/bitmask for RISC-V extension

---
 .../llvm/TargetParser/RISCVTargetParser.h |   8 +
 llvm/lib/Target/RISCV/RISCVFeatures.td| 155 --
 llvm/lib/TargetParser/RISCVTargetParser.cpp   |  32 
 llvm/test/TableGen/riscv-target-def.td|  26 ++-
 llvm/utils/TableGen/RISCVTargetDefEmitter.cpp |  37 +
 5 files changed, 205 insertions(+), 53 deletions(-)

diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h 
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..e998bc4ca59ee 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
 
 namespace RISCV {
 
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+  const char *Name;
+  unsigned GroupID;
+  unsigned BitPosition;
+};
+} // namespace RISCVExtensionBitmaskTable
+
 // We use 64 bits as the known part in the scalable vector types.
 static constexpr unsigned RVVBitsPerBlock = 64;
 
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 011edca019fd6..67615b9f76763 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+int GroupID = groupID;
+int BitPos = bitmaskShift;
+}
+
 // Version of RISCVExtension to be used for Experimental extensions. This
 // sets the Experimental flag and prepends experimental- to the -mattr name.
 class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+  RISCVExtensionBitmask<0, 8>;
 
 def FeatureStdExtE
 : RISCVExtension<"e", 2, 0,
@@ -78,7 +88,8 @@ def HasStdExtZicbop : 
Predicate<"Subtarget->hasStdExtZicbop()">,
 
 def FeatureStdExtZicboz
 : RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+  RISCVExtensionBitmask<0, 26>;
 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
   AssemblerPredicate<(all_of FeatureStdExtZicboz),
   "'Zicboz' (Cache-Block Zero Instructions)">;
@@ -101,7 +112,8 @@ def FeatureStdExtZiccrse
 
 def FeatureStdExtZicsr
 : RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)">;
+ "'zicsr' (CSRs)">,
+  RISCVExtensionBitmask<0, 27>;
 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
  AssemblerPredicate<(all_of FeatureStdExtZicsr),
 "'Zicsr' (CSRs)">;
@@ -113,7 +125,8 @@ def FeatureStdExtZicntr
 
 def FeatureStdExtZicond
 : RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">;
+ "'Zicond' (Integer Conditional Operations)">,
+  RISCVExtensionBitmask<0, 28>;
 def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
   AssemblerPredicate<(all_of FeatureStdExtZicond),
   "'Zicond' (Integer Conditional Operations)">;
@@ -134,7 +147,8 @@ def HasStdExtZihintpause : 
Predicate<"Subtarget->hasStdExtZihintpause()">,
 
 def FeatureStdExtZihintntl
 : RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">;
+ "'Zihintntl' (Non-Temporal Locality Hints)">,
+  RISCVExtensionBitmask<0, 29>;
 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
  AssemblerPredicate<(all_of FeatureStdExtZihintntl),
  "'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -173,7 +187,8 @@ def NoHasStdExtZicfiss : 
Predicate<"!Subtarget->hasStdExtZicfiss()">;
 
 def FeatureStdExtM
 : RISCVExtension<"m", 2, 0,
- "'M' (Integer Multiplication and Division)">;
+ "'M' (Integer Multiplication and Division)">,
+  RISCVExtensionBitmask<0, 12>;
 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
  AssemblerPredicate<(all_of FeatureStdExtM),
  "'M' (Integer Multiplication and Division)">;
@@ -192,14 +207,16 @@ def HasStdExtMOrZmmul
 
 def FeatureStdExtA
 : RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)">;
+ "'A' (Atomic Instructions)">,
+  RISCVExtensionBitmask<0, 0>;
 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
  AssemblerPredicate<(all_of FeatureStdExtA),
 "'A' (Atomic Instructions)">;
 
 def FeatureStdExtZtso
 : RISCVExperimentalExtension<"ztso", 0, 1,
-

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-06-11 Thread Piyou Chen via cfe-commits 

BeMg wrote:

Stack on https://github.com/llvm/llvm-project/pull/94440

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-06-11 Thread Piyou Chen via cfe-commits 

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786

>From 48eea6eda33c4e73316fe938a15d8e361039072e Mon Sep 17 00:00:00 2001
From: Piyou Chen 
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/2] [RISCV] Add groupid/bitmask for RISC-V extension

Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.

This patch defines the groupid/bitmask in RISCVFeatures.td and generates the 
corresponding table in RISCVTargetParserDef.inc.

The groupid/bitmask of extensions provides an abstraction layer between the 
compiler and runtime functions.
---
 .../llvm/TargetParser/RISCVTargetParser.h |   8 +
 llvm/lib/Target/RISCV/RISCVFeatures.td| 301 --
 llvm/lib/TargetParser/RISCVTargetParser.cpp   |  32 ++
 llvm/test/TableGen/riscv-target-def.td|  26 +-
 llvm/utils/TableGen/RISCVTargetDefEmitter.cpp |  52 +++
 5 files changed, 318 insertions(+), 101 deletions(-)

diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h 
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..8444935bd666d 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
 
 namespace RISCV {
 
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+  const char *Name;
+  unsigned GroupID;
+  uint64_t Bitmask;
+};
+} // namespace RISCVExtensionBitmaskTable
+
 // We use 64 bits as the known part in the scalable vector types.
 static constexpr unsigned RVVBitsPerBlock = 64;
 
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 011edca019fd6..624bd3f408858 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+bits<3> GroupID = groupID;
+bits<64> Bitmask = !shl(1, bitmaskShift);
+}
+
 // Version of RISCVExtension to be used for Experimental extensions. This
 // sets the Experimental flag and prepends experimental- to the -mattr name.
 class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+  RISCVExtensionBitmask<0, 0>;
 
 def FeatureStdExtE
 : RISCVExtension<"e", 2, 0,
- "Implements RV{32,64}E (provides 16 rather than 32 
GPRs)">;
+ "Implements RV{32,64}E (provides 16 rather than 32 
GPRs)">,
+  RISCVExtensionBitmask<0, 1>;
 
 def FeatureStdExtZic64b
 : RISCVExtension<"zic64b", 1, 0,
- "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">,
+  RISCVExtensionBitmask<0, 2>;
 
 def FeatureStdExtZicbom
 : RISCVExtension<"zicbom", 1, 0,
- "'Zicbom' (Cache-Block Management Instructions)">;
+ "'Zicbom' (Cache-Block Management Instructions)">,
+  RISCVExtensionBitmask<0, 3>;
 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
   AssemblerPredicate<(all_of FeatureStdExtZicbom),
   "'Zicbom' (Cache-Block Management Instructions)">;
 
 def FeatureStdExtZicbop
 : RISCVExtension<"zicbop", 1, 0,
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
+ "'Zicbop' (Cache-Block Prefetch Instructions)">,
+  RISCVExtensionBitmask<0, 4>;
 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
   AssemblerPredicate<(all_of FeatureStdExtZicbop),
   "'Zicbop' (Cache-Block Prefetch Instructions)">;
 
 def FeatureStdExtZicboz
 : RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+  RISCVExtensionBitmask<0, 5>;
 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
   AssemblerPredicate<(all_of FeatureStdExtZicboz),
   "'Zicboz' (Cache-Block Zero Instructions)">;
 
 def FeatureStdExtZiccamoa
 : RISCVExtension<"ziccamoa", 1, 0,
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">,
+  RISCVExtensionBitmask<0, 6>;
 
 def FeatureStdExtZiccif
 : RISCVExtension<"ziccif", 1, 0,
- "'Ziccif' (Main Memory Supports Instruction Fetch with 
Atomicity Requirement)">;
+ "'Ziccif' (Main Memory Supports Instruction Fetch with 
Atomicity Requirement)">,
+  RISCVExtensionBitmask<0, 7>;
 
 def FeatureStdExtZicclsm
 : RISCVExtension<"zicclsm", 1, 0,
- "'Zicclsm' (Main Memory Supports Misaligned 
Loads/Stores)">;
+ "'Zicclsm' (Main Memory Supports Misaligned 
Loads/Stores)">,
+  RISCVExtensionBitmask<0, 8>;
 
 def FeatureStdExtZiccrse
 : RISCVExtension<"ziccrse", 1, 0,
-

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-06-05 Thread Shao-Ce SUN via cfe-commits 


@@ -0,0 +1,142 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S -emit-llvm 
-o - %s | FileCheck %s
+
+__attribute__((target_clones("default", "arch=rv64im"))) int foo1(void) {
+  return 1;
+}
+__attribute__((target_clones("default", "arch=+zbb"))) int foo2(void) { return 
2; }
+__attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { 
return 3; }
+__attribute__((target_clones("default", "arch=rv64ima", "arch=+zbb,+v"))) int
+foo4(void) {
+  return 4;
+}
+__attribute__((target_clones("default"))) int foo5(void) { return 5; }
+
+int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
+
+//.
+// CHECK: @__riscv_hwprobe_args = internal global [2 x %riscv_hwprobe_pair] 
[%riscv_hwprobe_pair { i64 3, i64 1 }, %riscv_hwprobe_pair { i64 4, i64 0 }]
+// CHECK: @__riscv_hwprobe_args.1 = internal global [2 x 
%riscv_hwprobe_pair.0] [%riscv_hwprobe_pair.0 { i64 3, i64 1 }, 
%riscv_hwprobe_pair.0 { i64 4, i64 16 }]
+// CHECK: @__riscv_hwprobe_args.2 = internal global [2 x 
%riscv_hwprobe_pair.1] [%riscv_hwprobe_pair.1 { i64 3, i64 1 }, 
%riscv_hwprobe_pair.1 { i64 4, i64 18 }]
+// CHECK: @__riscv_hwprobe_args.3 = internal global [2 x 
%riscv_hwprobe_pair.2] [%riscv_hwprobe_pair.2 { i64 3, i64 1 }, 
%riscv_hwprobe_pair.2 { i64 4, i64 0 }]
+// CHECK: @__riscv_hwprobe_args.4 = internal global [2 x 
%riscv_hwprobe_pair.3] [%riscv_hwprobe_pair.3 { i64 3, i64 1 }, 
%riscv_hwprobe_pair.3 { i64 4, i64 20 }]
+// CHECK: @foo1.ifunc = weak_odr alias i32 (), ptr @foo1
+// CHECK: @foo2.ifunc = weak_odr alias i32 (), ptr @foo2
+// CHECK: @foo3.ifunc = weak_odr alias i32 (), ptr @foo3
+// CHECK: @foo4.ifunc = weak_odr alias i32 (), ptr @foo4
+// CHECK: @foo5.ifunc = weak_odr alias i32 (), ptr @foo5
+// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
+// CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver
+// CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver
+// CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver
+// CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver
+//.
+// CHECK-LABEL: define dso_local signext i32 @foo1.default(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret i32 1
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
+// CHECK-NEXT:  resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr 
@__riscv_hwprobe_args, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label 
[[RESOLVER_ELSE:%.*]]
+// CHECK:   resolver_return:
+// CHECK-NEXT:ret ptr @"foo1.arch=rv64im"
+// CHECK:   resolver_else:
+// CHECK-NEXT:ret ptr @foo1.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo2.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret i32 2
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
+// CHECK-NEXT:  resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr 
@__riscv_hwprobe_args.1, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label 
[[RESOLVER_ELSE:%.*]]
+// CHECK:   resolver_return:
+// CHECK-NEXT:ret ptr @"foo2.arch=+zbb"
+// CHECK:   resolver_else:
+// CHECK-NEXT:ret ptr @foo2.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo3.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret i32 3
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
+// CHECK-NEXT:  resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr 
@__riscv_hwprobe_args.2, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label 
[[RESOLVER_ELSE:%.*]]
+// CHECK:   resolver_return:
+// CHECK-NEXT:ret ptr @"foo3.arch=+zbb,+c"
+// CHECK:   resolver_else:
+// CHECK-NEXT:ret ptr @foo3.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo4.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret i32 4
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
+// CHECK-NEXT:  resolver_entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i1 @__riscv_ifunc_select(ptr 
@__riscv_hwprobe_args.3, i32 2)
+// CHECK-NEXT:br i1 [[TMP0]], label [[RESOLVER_RETURN:%.*]], label 
[[RESOLVER_ELSE:%.*]]
+// CHECK:   resolver_return:
+// CHECK-NEXT:ret ptr @"foo4.arch=rv64ima"
+// CHECK:   resolver_else:
+// CHECK-NEXT:[[TMP1:%.*]] = call i1 @__riscv_ifunc_select(ptr 
@__riscv_hwprobe_args.4, i32 2)
+// CHECK-NEXT:br i1 [[TMP1]], label [[RESOLVER_RETURN1:%.*]], label 
[[RESOLVER_ELSE2:%.*]]
+// CHECK:   resolver_return1:
+// CHECK-NEXT:ret ptr @"foo4.arch=+zbb,+v"
+// CHECK:   resolver_else2:
+// CHECK-NEXT:ret ptr @foo4.default
+//
+//
+// CHECK-LABEL: define

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-05-22 Thread Piyou Chen via cfe-commits 

https://github.com/BeMg converted_to_draft 
https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-11 Thread Piyou Chen via cfe-commits 

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786

>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen 
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 01/11] [RISCV][FMV] Support target_clones

---
 clang/include/clang/Basic/TargetInfo.h|   3 +-
 clang/lib/AST/ASTContext.cpp  |   9 ++
 clang/lib/Basic/Targets/RISCV.cpp |  10 +-
 clang/lib/Basic/Targets/RISCV.h   |   2 +
 clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
 clang/lib/CodeGen/CodeGenFunction.h   |   3 +
 clang/lib/CodeGen/CodeGenModule.cpp   |   2 +
 clang/lib/CodeGen/Targets/RISCV.cpp   |  23 +++
 clang/lib/Sema/SemaDeclAttr.cpp   |  22 +++
 clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
 .../CodeGenCXX/attr-target-clones-riscv.cpp   | 136 ++
 .../test/SemaCXX/attr-target-clones-riscv.cpp |  19 +++
 12 files changed, 462 insertions(+), 4 deletions(-)
 create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
 create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
 create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp

diff --git a/clang/include/clang/Basic/TargetInfo.h 
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
   /// Identify whether this target supports multiversioning of functions,
   /// which requires support for cpu_supports and cpu_is functionality.
   bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+   getTriple().isRISCV();
   }
 
   /// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void 
ASTContext::getFunctionFeatureMap(llvm::StringMap ,
   Features.insert(Features.begin(),
   Target->getTargetOpts().FeaturesAsWritten.begin(),
   Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+  if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+  }
+  Features.insert(Features.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.end());
 } else {
   if (VersionStr.starts_with("arch="))
 TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
 
   // If a target attribute specified a full arch string, override all the ISA
   // extension target features.
-  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
   if (I != FeaturesVec.end()) {
 std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
 
@@ -366,6 +366,12 @@ bool 
RISCVTargetInfo::handleTargetFeatures(std::vector ,
   return true;
 }
 
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+  if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+  return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
 bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
   bool Is64Bit = getTriple().isArch64Bit();
   return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
 
 static void handleFullArchString(StringRef FullArchStr,
  std::vector ) {
-  Features.push_back("__RISCV_TargetAttrNeedOverride");
+  Features.push_back("+__RISCV_TargetAttrNeedOverride");
   auto RII = llvm::RISCVISAInfo::parseArchString(
   FullArchStr, /* EnableExperimentalExtension */ true);
   if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
   bool handleTargetFeatures(std::vector ,
 DiagnosticsEngine ) override;
 
+  bool isValidFeatureName(StringRef Feature) const

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-10 Thread Jessica Clarke via cfe-commits 


@@ -0,0 +1,14 @@
+// RUN: not %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S 
-emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-EXT
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -S -emit-llvm -o - 
%s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
+
+// CHECK-UNSUPPORT-EXT: error: Unsupport 'zicsr' for _riscv_hwprobe
+__attribute__((target_clones("default", "arch=+zicsr"))) int foo1(void) {
+  return 1;
+}
+
+// CHECK-UNSUPPORT-OS: error: Only Linux support _riscv_hwprobe

jrtc27 wrote:

Yes, that seems fine

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-10 Thread Craig Topper via cfe-commits 


@@ -0,0 +1,14 @@
+// RUN: not %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S 
-emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-EXT
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -S -emit-llvm -o - 
%s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
+
+// CHECK-UNSUPPORT-EXT: error: Unsupport 'zicsr' for _riscv_hwprobe
+__attribute__((target_clones("default", "arch=+zicsr"))) int foo1(void) {
+  return 1;
+}
+
+// CHECK-UNSUPPORT-OS: error: Only Linux support _riscv_hwprobe

topperc wrote:

@jrtc27 so something like "target_clones is currently only supported on Linux"?

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-09 Thread Piyou Chen via cfe-commits 

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786

>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen 
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 01/10] [RISCV][FMV] Support target_clones

---
 clang/include/clang/Basic/TargetInfo.h|   3 +-
 clang/lib/AST/ASTContext.cpp  |   9 ++
 clang/lib/Basic/Targets/RISCV.cpp |  10 +-
 clang/lib/Basic/Targets/RISCV.h   |   2 +
 clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
 clang/lib/CodeGen/CodeGenFunction.h   |   3 +
 clang/lib/CodeGen/CodeGenModule.cpp   |   2 +
 clang/lib/CodeGen/Targets/RISCV.cpp   |  23 +++
 clang/lib/Sema/SemaDeclAttr.cpp   |  22 +++
 clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
 .../CodeGenCXX/attr-target-clones-riscv.cpp   | 136 ++
 .../test/SemaCXX/attr-target-clones-riscv.cpp |  19 +++
 12 files changed, 462 insertions(+), 4 deletions(-)
 create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
 create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
 create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp

diff --git a/clang/include/clang/Basic/TargetInfo.h 
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
   /// Identify whether this target supports multiversioning of functions,
   /// which requires support for cpu_supports and cpu_is functionality.
   bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+   getTriple().isRISCV();
   }
 
   /// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void 
ASTContext::getFunctionFeatureMap(llvm::StringMap ,
   Features.insert(Features.begin(),
   Target->getTargetOpts().FeaturesAsWritten.begin(),
   Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+  if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+  }
+  Features.insert(Features.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.end());
 } else {
   if (VersionStr.starts_with("arch="))
 TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
 
   // If a target attribute specified a full arch string, override all the ISA
   // extension target features.
-  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
   if (I != FeaturesVec.end()) {
 std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
 
@@ -366,6 +366,12 @@ bool 
RISCVTargetInfo::handleTargetFeatures(std::vector ,
   return true;
 }
 
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+  if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+  return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
 bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
   bool Is64Bit = getTriple().isArch64Bit();
   return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
 
 static void handleFullArchString(StringRef FullArchStr,
  std::vector ) {
-  Features.push_back("__RISCV_TargetAttrNeedOverride");
+  Features.push_back("+__RISCV_TargetAttrNeedOverride");
   auto RII = llvm::RISCVISAInfo::parseArchString(
   FullArchStr, /* EnableExperimentalExtension */ true);
   if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
   bool handleTargetFeatures(std::vector ,
 DiagnosticsEngine ) override;
 
+  bool isValidFeatureName(StringRef Feature) const

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Jessica Clarke via cfe-commits 

https://github.com/jrtc27 edited https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Jessica Clarke via cfe-commits 


@@ -0,0 +1,14 @@
+// RUN: not %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S 
-emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-EXT
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -S -emit-llvm -o - 
%s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
+
+// CHECK-UNSUPPORT-EXT: error: Unsupport 'zicsr' for _riscv_hwprobe
+__attribute__((target_clones("default", "arch=+zicsr"))) int foo1(void) {
+  return 1;
+}
+
+// CHECK-UNSUPPORT-OS: error: Only Linux support _riscv_hwprobe

jrtc27 wrote:

That's not the right error message still. " is only 
supported on Linux" isn't the point, the point is that the current 
implementation only supports Linux because it is written to use that specific 
system call. Other OSes can and likely will provide alternative interfaces that 
could equally be used.

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Craig Topper via cfe-commits 


@@ -14156,6 +14157,84 @@ 
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
   return Result;
 }
 
+llvm::SmallVector
+CodeGenFunction::EmitRISCVExtSupports(ArrayRef FeaturesStrs) {
+  auto BaseExtReqs = llvm::RISCV::getBaseExtensionKey(FeaturesStrs);
+  auto IMACompatibleExtReqs =
+  llvm::RISCV::getIMACompatibleExtensionKey(FeaturesStrs);
+
+  // check whether all FeatureStrs are available for hwprobe.
+  llvm::SmallVector UnsupportByHwprobe;
+  llvm::StringSet<> ImpliedExtBySupportExt;
+  for (unsigned Idx = 0; Idx < FeaturesStrs.size(); Idx++) {
+if (BaseExtReqs[Idx] == 0 && IMACompatibleExtReqs[Idx] == 0)
+  UnsupportByHwprobe.push_back(FeaturesStrs[Idx]);
+else
+  ImpliedExtBySupportExt.insert(FeaturesStrs[Idx].str());
+  }
+
+  // Repeatly find ImpliedExts until no longer found new.
+  bool Changed = true;
+  while (Changed) {
+unsigned Size = ImpliedExtBySupportExt.size();
+for (auto Ext : ImpliedExtBySupportExt.keys()) {
+  auto ImpliedExts = llvm::RISCV::getImpliedExts(Ext);
+  for (auto ImpliedExt : ImpliedExts)
+ImpliedExtBySupportExt.insert(ImpliedExt);
+}
+if (Size == ImpliedExtBySupportExt.size())
+  Changed = false;
+  }
+
+  // FIXME: Could hwprobe guarantee that the hardware will support the Implied
+  // extension?
+  for (unsigned Idx = 0; Idx < UnsupportByHwprobe.size(); Idx++) {
+if (!llvm::is_contained(ImpliedExtBySupportExt, UnsupportByHwprobe[Idx]))
+  CGM.getDiags().Report(diag::err_extension_unsupport_riscv_hwprobe)
+  << UnsupportByHwprobe[Idx];
+  }
+
+  StructType *structType =

topperc wrote:

Variable name should be capitalized

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Craig Topper via cfe-commits 


@@ -14156,6 +14157,84 @@ 
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
   return Result;
 }
 
+llvm::SmallVector
+CodeGenFunction::EmitRISCVExtSupports(ArrayRef FeaturesStrs) {
+  auto BaseExtReqs = llvm::RISCV::getBaseExtensionKey(FeaturesStrs);
+  auto IMACompatibleExtReqs =
+  llvm::RISCV::getIMACompatibleExtensionKey(FeaturesStrs);
+
+  // check whether all FeatureStrs are available for hwprobe.
+  llvm::SmallVector UnsupportByHwprobe;
+  llvm::StringSet<> ImpliedExtBySupportExt;
+  for (unsigned Idx = 0; Idx < FeaturesStrs.size(); Idx++) {
+if (BaseExtReqs[Idx] == 0 && IMACompatibleExtReqs[Idx] == 0)
+  UnsupportByHwprobe.push_back(FeaturesStrs[Idx]);
+else
+  ImpliedExtBySupportExt.insert(FeaturesStrs[Idx].str());
+  }
+
+  // Repeatly find ImpliedExts until no longer found new.

topperc wrote:

found -> find

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Craig Topper via cfe-commits 


@@ -14156,6 +14157,84 @@ 
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
   return Result;
 }
 
+llvm::SmallVector
+CodeGenFunction::EmitRISCVExtSupports(ArrayRef FeaturesStrs) {
+  auto BaseExtReqs = llvm::RISCV::getBaseExtensionKey(FeaturesStrs);
+  auto IMACompatibleExtReqs =
+  llvm::RISCV::getIMACompatibleExtensionKey(FeaturesStrs);
+
+  // check whether all FeatureStrs are available for hwprobe.
+  llvm::SmallVector UnsupportByHwprobe;
+  llvm::StringSet<> ImpliedExtBySupportExt;
+  for (unsigned Idx = 0; Idx < FeaturesStrs.size(); Idx++) {
+if (BaseExtReqs[Idx] == 0 && IMACompatibleExtReqs[Idx] == 0)
+  UnsupportByHwprobe.push_back(FeaturesStrs[Idx]);
+else
+  ImpliedExtBySupportExt.insert(FeaturesStrs[Idx].str());
+  }
+
+  // Repeatly find ImpliedExts until no longer found new.
+  bool Changed = true;
+  while (Changed) {
+unsigned Size = ImpliedExtBySupportExt.size();
+for (auto Ext : ImpliedExtBySupportExt.keys()) {
+  auto ImpliedExts = llvm::RISCV::getImpliedExts(Ext);
+  for (auto ImpliedExt : ImpliedExts)
+ImpliedExtBySupportExt.insert(ImpliedExt);
+}
+if (Size == ImpliedExtBySupportExt.size())

topperc wrote:

Can you use the return value from `insert` to tell if the insert happened?

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Craig Topper via cfe-commits 


@@ -14156,6 +14157,84 @@ 
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
   return Result;
 }
 
+llvm::SmallVector
+CodeGenFunction::EmitRISCVExtSupports(ArrayRef FeaturesStrs) {
+  auto BaseExtReqs = llvm::RISCV::getBaseExtensionKey(FeaturesStrs);
+  auto IMACompatibleExtReqs =
+  llvm::RISCV::getIMACompatibleExtensionKey(FeaturesStrs);
+
+  // check whether all FeatureStrs are available for hwprobe.

topperc wrote:

check->Check

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Craig Topper via cfe-commits 


@@ -0,0 +1,14 @@
+// RUN: not %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S 
-emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-EXT
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -S -emit-llvm -o - 
%s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
+
+// CHECK-UNSUPPORT-EXT: error: Unsupport 'zicsr' for _riscv_hwprobe
+__attribute__((target_clones("default", "arch=+zicsr"))) int foo1(void) {
+  return 1;
+}
+
+// CHECK-UNSUPPORT-OS: error: Only Linux support _riscv_hwprobe

topperc wrote:

`_riscv_hwprobe is only supported on Linux`

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-08 Thread Craig Topper via cfe-commits 


@@ -0,0 +1,14 @@
+// RUN: not %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -S 
-emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-EXT
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -S -emit-llvm -o - 
%s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
+
+// CHECK-UNSUPPORT-EXT: error: Unsupport 'zicsr' for _riscv_hwprobe

topperc wrote:

`Unsupported extension 'zicsr' for _riscv_hwprobe`?

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-04-07 Thread Piyou Chen via cfe-commits 

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786

>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen 
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/6] [RISCV][FMV] Support target_clones

---
 clang/include/clang/Basic/TargetInfo.h|   3 +-
 clang/lib/AST/ASTContext.cpp  |   9 ++
 clang/lib/Basic/Targets/RISCV.cpp |  10 +-
 clang/lib/Basic/Targets/RISCV.h   |   2 +
 clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
 clang/lib/CodeGen/CodeGenFunction.h   |   3 +
 clang/lib/CodeGen/CodeGenModule.cpp   |   2 +
 clang/lib/CodeGen/Targets/RISCV.cpp   |  23 +++
 clang/lib/Sema/SemaDeclAttr.cpp   |  22 +++
 clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
 .../CodeGenCXX/attr-target-clones-riscv.cpp   | 136 ++
 .../test/SemaCXX/attr-target-clones-riscv.cpp |  19 +++
 12 files changed, 462 insertions(+), 4 deletions(-)
 create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
 create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
 create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp

diff --git a/clang/include/clang/Basic/TargetInfo.h 
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
   /// Identify whether this target supports multiversioning of functions,
   /// which requires support for cpu_supports and cpu_is functionality.
   bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+   getTriple().isRISCV();
   }
 
   /// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void 
ASTContext::getFunctionFeatureMap(llvm::StringMap ,
   Features.insert(Features.begin(),
   Target->getTargetOpts().FeaturesAsWritten.begin(),
   Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+  if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+  }
+  Features.insert(Features.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.end());
 } else {
   if (VersionStr.starts_with("arch="))
 TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
 
   // If a target attribute specified a full arch string, override all the ISA
   // extension target features.
-  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
   if (I != FeaturesVec.end()) {
 std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
 
@@ -366,6 +366,12 @@ bool 
RISCVTargetInfo::handleTargetFeatures(std::vector ,
   return true;
 }
 
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+  if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+  return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
 bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
   bool Is64Bit = getTriple().isArch64Bit();
   return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
 
 static void handleFullArchString(StringRef FullArchStr,
  std::vector ) {
-  Features.push_back("__RISCV_TargetAttrNeedOverride");
+  Features.push_back("+__RISCV_TargetAttrNeedOverride");
   auto RII = llvm::RISCVISAInfo::parseArchString(
   FullArchStr, /* EnableExperimentalExtension */ true);
   if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
   bool handleTargetFeatures(std::vector ,
 DiagnosticsEngine ) override;
 
+  bool isValidFeatureName(StringRef Feature) const

[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-03-30 Thread Piyou Chen via cfe-commits 

BeMg wrote:

1. Suppress the warning `warn_target_clone_mixed_values` for RISC-V
2. Update `__riscv_ifunc_select`. From `__riscv_ifunc_select(char *)` into 
`__riscv_ifunc_select(unsigned long long, unsigned long long )`. 
3. Add one more error messenge when there are +extension that hwprobe can't 
detect.

https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)

2024-03-30 Thread Piyou Chen via cfe-commits 

https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786

>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen 
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/4] [RISCV][FMV] Support target_clones

---
 clang/include/clang/Basic/TargetInfo.h|   3 +-
 clang/lib/AST/ASTContext.cpp  |   9 ++
 clang/lib/Basic/Targets/RISCV.cpp |  10 +-
 clang/lib/Basic/Targets/RISCV.h   |   2 +
 clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
 clang/lib/CodeGen/CodeGenFunction.h   |   3 +
 clang/lib/CodeGen/CodeGenModule.cpp   |   2 +
 clang/lib/CodeGen/Targets/RISCV.cpp   |  23 +++
 clang/lib/Sema/SemaDeclAttr.cpp   |  22 +++
 clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
 .../CodeGenCXX/attr-target-clones-riscv.cpp   | 136 ++
 .../test/SemaCXX/attr-target-clones-riscv.cpp |  19 +++
 12 files changed, 462 insertions(+), 4 deletions(-)
 create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
 create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
 create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp

diff --git a/clang/include/clang/Basic/TargetInfo.h 
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
   /// Identify whether this target supports multiversioning of functions,
   /// which requires support for cpu_supports and cpu_is functionality.
   bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+   getTriple().isRISCV();
   }
 
   /// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void 
ASTContext::getFunctionFeatureMap(llvm::StringMap ,
   Features.insert(Features.begin(),
   Target->getTargetOpts().FeaturesAsWritten.begin(),
   Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+  if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+  }
+  Features.insert(Features.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.begin(),
+  Target->getTargetOpts().FeaturesAsWritten.end());
 } else {
   if (VersionStr.starts_with("arch="))
 TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp 
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
 
   // If a target attribute specified a full arch string, override all the ISA
   // extension target features.
-  const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+  const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
   if (I != FeaturesVec.end()) {
 std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
 
@@ -366,6 +366,12 @@ bool 
RISCVTargetInfo::handleTargetFeatures(std::vector ,
   return true;
 }
 
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+  if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+  return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
 bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
   bool Is64Bit = getTriple().isArch64Bit();
   return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
 
 static void handleFullArchString(StringRef FullArchStr,
  std::vector ) {
-  Features.push_back("__RISCV_TargetAttrNeedOverride");
+  Features.push_back("+__RISCV_TargetAttrNeedOverride");
   auto RII = llvm::RISCVISAInfo::parseArchString(
   FullArchStr, /* EnableExperimentalExtension */ true);
   if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
   bool handleTargetFeatures(std::vector ,
 DiagnosticsEngine ) override;
 
+  bool isValidFeatureName(StringRef Feature) const