[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-13 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/9] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 326 +-
 7 files changed, 235 insertions(+), 163 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 1a15be1c6e4dc1..b8ea4fd738fdf7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -61,6 +61,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -557,6 +559,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a1de8596480da9..69e823eac25fc6 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -362,6 +362,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6eec03fd6f7082..17f39223b99bac 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -95,6 +95,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -258,7 +260,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Garvit Gupta via cfe-commits

quic-garvgupt wrote:

Thanks for the prompt reply and latest patchset.

1. Do we need to add documentation in RISCVUsage.rst file for xsfcease?
2. Also, as we are adding cease instruction in this PR, can we rename the PR to 
include the cease instruction as well?

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/8] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 326 +-
 7 files changed, 235 insertions(+), 163 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 1a15be1c6e4dc1..b8ea4fd738fdf7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -61,6 +61,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -557,6 +559,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a1de8596480da9..69e823eac25fc6 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -362,6 +362,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6eec03fd6f7082..17f39223b99bac 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -95,6 +95,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -258,7 +260,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Craig Topper via cfe-commits

topperc wrote:

> Thanks for clearing the confusion around whether rs1 would be optional or 
> not. Can we also add lit tests for the aliases?

I already addded tests 
https://github.com/llvm/llvm-project/pull/83896/commits/f6f43e9f8ffa8b58d63178d28c826d0009de2f3b

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Garvit Gupta via cfe-commits

quic-garvgupt wrote:

Thanks for clearing the confusion around whether rs1 would be optional or not. 
Can we also add lit tests for the aliases? 

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Peter Rong via cfe-commits

https://github.com/DataCorrupted updated 
https://github.com/llvm/llvm-project/pull/83896

>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/7] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 326 +-
 7 files changed, 235 insertions(+), 163 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 1a15be1c6e4dc1..b8ea4fd738fdf7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -61,6 +61,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -557,6 +559,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a1de8596480da9..69e823eac25fc6 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -362,6 +362,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6eec03fd6f7082..17f39223b99bac 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -95,6 +95,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -258,7 +260,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef 

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread via cfe-commits

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff f1ca2a09671e4d4acc2bea362b39268ed7883b6d 
c31b2fd3cb923bc306cf9d086bb7723e4c7004cd -- 
clang/test/Preprocessor/riscv-target-features.c 
llvm/lib/Support/RISCVISAInfo.cpp 
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
llvm/unittests/Support/RISCVISAInfoTest.cpp
``





View the diff from clang-format here.


``diff
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index cd6fb27b49..6aadabdf1b 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -601,8 +601,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst , 
uint64_t ,
 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
   DecoderTableXSiFivecflushdlone32,
   "SiFive sf.cflush.d.l1 custom opcode table");
-TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease,
-  DecoderTableXSfcease32,
+TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
   "SiFive sf.cease custom opcode table");
 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
   DecoderTableXCVbitmanip32,

``




https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/6] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 326 +-
 7 files changed, 235 insertions(+), 163 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 1a15be1c6e4dc1..b8ea4fd738fdf7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -61,6 +61,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -557,6 +559,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a1de8596480da9..69e823eac25fc6 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -362,6 +362,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6eec03fd6f7082..17f39223b99bac 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -95,6 +95,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -258,7 +260,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From f22a5cd30f77b2043f9c1f7f4482fad87fb79250 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/5] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 326 +-
 7 files changed, 235 insertions(+), 163 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 1a15be1c6e4dc1..b8ea4fd738fdf7 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -61,6 +61,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -557,6 +559,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a1de8596480da9..69e823eac25fc6 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -362,6 +362,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6eec03fd6f7082..17f39223b99bac 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -95,6 +95,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -258,7 +260,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/5] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 324 +-
 7 files changed, 234 insertions(+), 162 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 664279cb123949..f8d4800aabbb44 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,6 +60,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -548,6 +550,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d293b02144307..f1e2e86390c838 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -352,6 +352,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 68f5c36e8fafc6..8dbb40f97bf338 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -94,6 +94,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -257,7 +259,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-12 Thread Craig Topper via cfe-commits

topperc wrote:

> > > Hi @topperc, can you add instruction alias for cflush and cdiscard 
> > > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` 
> > > respectively, as this register is optional according to spec?
> > 
> > 
> > x0 has special meaning, but the spec never says it is "optional".
> 
> Possibly I am mistaken here but this is what I inferred from the below text 
> in the mannual - rs1 is optional, so if a user does not specify it then by 
> default it will be X0. Apologies if I am missing something here but just 
> wanted to be clear.
> 
> From the mannual - `Opcode 0xFC73, with **optional** rs1 field in bits 
> [19:15]`

I think i had a bad copy of the file. There are several iterations. And one of 
the copies I had doesn't have the "optional" text on cflush.d.l1.

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Garvit Gupta via cfe-commits

quic-garvgupt wrote:

> > Also, I think we might need to update the extensions in the 
> > `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
> 
> This is a M-mode only extension, and we haven't historically been adding M or 
> S mode extensions to the -mcpu lists. Except for `xiangshan-nanhu` having 
> `Svinval`. But maybe there's a microcontroller vs application core 
> distinction we should be making?

I see, I was not aware of this. Thanks for your reply

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Garvit Gupta via cfe-commits

quic-garvgupt wrote:

> > Hi @topperc, can you add instruction alias for cflush and cdiscard 
> > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` 
> > respectively, as this register is optional according to spec?
> 
> x0 has special meaning, but the spec never says it is "optional".

Possibly I am mistaken here but this is what I inferred from the below text in 
the mannual - rs1 is optional, so if a user does not specify it then by default 
it will be X0. Apologies if I am missing something here but just wanted to be 
clear.

>From the mannual - 
`Opcode 0xFC73, with **optional** rs1 field in bits [19:15]`

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Craig Topper via cfe-commits

topperc wrote:

> Also, I think we might need to update the extensions in the 
> `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?

This is a M-mode only extension, and we haven't historically been adding M or S 
mode extensions to the -mcpu lists. Except for `xiangshan-nanhu` having 
`Svinval`. But maybe there's a microcontroller vs application core distinction 
we should be making?

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Craig Topper via cfe-commits

topperc wrote:

> Hi @topperc, can you add instruction alias for cflush and cdiscard 
> instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` 
> respectively, as this register is optional according to spec?

x0 has special meaning, but the spec never says it is "optional".

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Garvit Gupta via cfe-commits

quic-garvgupt wrote:

Also, I think we might need to update the extensions in the 
`RISCVProcessors.td` file under SIFIVE_S76 microcontroller?

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Garvit Gupta via cfe-commits

quic-garvgupt wrote:

Hi @topperc, can you add instruction alias for cflush and cdiscard instructions 
when the rs1 is X0 to `sf.cflush.d.l1`  and `sf.cflush.d.l1` respectively, as 
this register is optional according to spec? 

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Ana Pazos via cfe-commits

apazos wrote:

Also, @topperc, we should add the new extensions  to the list of vendor 
extensions in the specs:
ttps://github.com/riscv-non-isa/riscv-toolchain-conventions/tree/master?tab=readme-ov-file#list-of-vendor-extensions

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-11 Thread Ana Pazos via cfe-commits

apazos wrote:

@topperc , how about the CEASE instruction? Can you add it in this patch?

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-08 Thread Jessica Clarke via cfe-commits

https://github.com/jrtc27 dismissed 
https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-08 Thread Jessica Clarke via cfe-commits

jrtc27 wrote:

> @jrtc27 does this look better now?

Yes; thanks

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-08 Thread Craig Topper via cfe-commits

topperc wrote:

@jrtc27 does this look better now?

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-06 Thread Shao-Ce SUN via cfe-commits

sunshaoce wrote:

> > > By the way, is there any plan to support `CFLUSH.I.L1` in the future?
> > 
> > 
> > Flushing the instruction cache doesn't make sense given it can never be 
> > dirty. Invalidating/discarding does, but that's just what fence.i is doing?
> 
> A cflush.i.l1 did appear in some SiFive manual at some point, but I don't 
> think any hardware implements it.

Understood, thank you for the reply!

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-05 Thread Craig Topper via cfe-commits

topperc wrote:

> > By the way, is there any plan to support `CFLUSH.I.L1` in the future?
> 
> Flushing the instruction cache doesn't make sense given it can never be 
> dirty. Invalidating/discarding does, but that's just what fence.i is doing?

A cflush.i.l1 did appear in some SiFive manual at some point, but I don't think 
any hardware implements it.

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-05 Thread Jessica Clarke via cfe-commits

jrtc27 wrote:

> By the way, is there any plan to support `CFLUSH.I.L1` in the future?

Flushing the instruction cache doesn't make sense given it can never be dirty. 
Invalidating/discarding does, but that's just what fence.i is doing?

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-05 Thread Shao-Ce SUN via cfe-commits

sunshaoce wrote:

By the way, is there any plan to support `CFLUSH.I.L1` in the future?

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-05 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/4] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 324 +-
 7 files changed, 234 insertions(+), 162 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 664279cb123949..f8d4800aabbb44 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,6 +60,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -548,6 +550,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d293b02144307..f1e2e86390c838 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -352,6 +352,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 68f5c36e8fafc6..8dbb40f97bf338 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -94,6 +94,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -257,7 +259,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-04 Thread Jessica Clarke via cfe-commits

https://github.com/jrtc27 requested changes to this pull request.

These need the vendor "sf." prefix

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-04 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/3] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 324 +-
 7 files changed, 234 insertions(+), 162 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 664279cb123949..f8d4800aabbb44 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,6 +60,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -548,6 +550,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d293b02144307..f1e2e86390c838 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -352,6 +352,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 68f5c36e8fafc6..8dbb40f97bf338 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -94,6 +94,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -257,7 +259,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-04 Thread Craig Topper via cfe-commits

https://github.com/topperc updated 
https://github.com/llvm/llvm-project/pull/83896

>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/2] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 324 +-
 7 files changed, 234 insertions(+), 162 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 664279cb123949..f8d4800aabbb44 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,6 +60,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -548,6 +550,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d293b02144307..f1e2e86390c838 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -352,6 +352,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 68f5c36e8fafc6..8dbb40f97bf338 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -94,6 +94,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -257,7 +259,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-04 Thread Yingwei Zheng via cfe-commits


@@ -60,6 +60,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}

dtcxzyw wrote:

```suggestion
// CHECK-NOT: __riscv_xsifivecdiscarddlone {{.*$}}
// CHECK-NOT: __riscv_xsifivecflushdlone {{.*$}}
```

https://github.com/llvm/llvm-project/pull/83896
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[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-04 Thread via cfe-commits

llvmbot wrote:



@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang

Author: Craig Topper (topperc)


Changes

These were in LLVM 17 but removed from LLVM 18 due to an incorrect extension 
name being used.

This restores them with new extension names that match SiFive's downstream 
compiler. The extension name has been used internally for some time. It uses 
XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
 though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate a longer 
extension name.

---
Full diff: https://github.com/llvm/llvm-project/pull/83896.diff


7 Files Affected:

- (modified) clang/test/Preprocessor/riscv-target-features.c (+18) 
- (modified) llvm/docs/RISCVUsage.rst (+6) 
- (modified) llvm/lib/Support/RISCVISAInfo.cpp (+3-1) 
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+6) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+16) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td (+22) 
- (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+163-161) 


``diff
diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 664279cb123949..f8d4800aabbb44 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,6 +60,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -548,6 +550,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d293b02144307..f1e2e86390c838 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -352,6 +352,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 68f5c36e8fafc6..8dbb40f97bf338 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -94,6 +94,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xsfvfwmaccqqq", {1, 0}},
 {"xsfvqmaccdod", {1, 0}},
 {"xsfvqmaccqoq", {1, 0}},
+{"xsifivecdiscarddlone", {1, 0}},
+{"xsifivecflushdlone", {1, 0}},
 {"xtheadba", {1, 0}},
 {"xtheadbb", {1, 0}},
 {"xtheadbs", {1, 0}},
@@ -257,7 +259,7 @@ static void PrintExtension(StringRef Name, StringRef 
Version,
StringRef Description) {
   outs().indent(4);
   unsigned VersionWidth = Description.empty() ? 0 : 10;
-  outs() << 

[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)

2024-03-04 Thread Craig Topper via cfe-commits

https://github.com/topperc created 
https://github.com/llvm/llvm-project/pull/83896

These were in LLVM 17 but removed from LLVM 18 due to an incorrect extension 
name being used.

This restores them with new extension names that match SiFive's downstream 
compiler. The extension name has been used internally for some time. It uses 
XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
 though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate a longer 
extension name.

>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper 
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
 instructions.

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.

The spec for the instructions is here 
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
 .../test/Preprocessor/riscv-target-features.c |  18 +
 llvm/docs/RISCVUsage.rst  |   6 +
 llvm/lib/Support/RISCVISAInfo.cpp |   4 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   6 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  16 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td|  22 ++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   | 324 +-
 7 files changed, 234 insertions(+), 162 deletions(-)

diff --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 664279cb123949..f8d4800aabbb44 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,6 +60,8 @@
 // CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
 // CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
 // CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
 // CHECK-NOT: __riscv_xtheadba {{.*$}}
 // CHECK-NOT: __riscv_xtheadbb {{.*$}}
 // CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -548,6 +550,22 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
 // CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 100{{$}}
 
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 100{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN:   -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN:   -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 100{{$}}
+
 // RUN: %clang --target=riscv32-unknown-linux-gnu \
 // RUN:   -march=rv32ixtheadba -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d293b02144307..f1e2e86390c838 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -352,6 +352,12 @@ The current vendor extensions supported are:
 ``XCVbi``
   LLVM implements `version 1.0.0 of the CORE-V immediate branching custom 
instructions specification 
`__
 by OpenHW Group.  All instructions are prefixed with `cv.` as described in the 
specification. These instructions are only available for riscv32 at this time.
 
+``XSiFivecdiscarddlone``
+  LLVM implements `the SiFive cdiscard.d.l1 instruction specified in 
`_
 by SiFive.
+
+``XSiFivecflushdlone``
+  LLVM implements `the SiFive cflush.d.l1 instruction specified in 
`_
 by SiFive.
+
 Experimental C Intrinsics
 =
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index