[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-18 Thread Luke Lau via cfe-commits 

https://github.com/lukel97 closed 
https://github.com/llvm/llvm-project/pull/77458
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[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-18 Thread Luke Lau via cfe-commits 

https://github.com/lukel97 updated 
https://github.com/llvm/llvm-project/pull/77458

>From d22817bcd7ea7ab5763cb4da58552ce6930d4b73 Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
 defined in profiles spec

This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions

As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
 llvm/lib/Support/RISCVISAInfo.cpp  |  7 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
 llvm/test/CodeGen/RISCV/attributes.ll  | 14 ++
 3 files changed, 47 insertions(+)

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index d991878a5f1ecac..8c9eb1bddb3cb52 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -88,6 +88,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xtheadvdot", {1, 0}},
 {"xventanacondops", {1, 0}},
 
+{"za128rs", {1, 0}},
+{"za64rs", {1, 0}},
 {"zawrs", {1, 0}},
 
 {"zba", {1, 0}},
@@ -116,9 +118,14 @@ static const RISCVSupportedExtension SupportedExtensions[] 
= {
 {"zhinx", {1, 0}},
 {"zhinxmin", {1, 0}},
 
+{"zic64b", {1, 0}},
 {"zicbom", {1, 0}},
 {"zicbop", {1, 0}},
 {"zicboz", {1, 0}},
+{"ziccamoa", {1, 0}},
+{"ziccif", {1, 0}},
+{"zicclsm", {1, 0}},
+{"ziccrse", {1, 0}},
 {"zicntr", {2, 0}},
 {"zicsr", {2, 0}},
 {"zifencei", {2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa334c69ddc982b..1946f2253fa6c07 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -93,6 +93,22 @@ def HasStdExtZifencei : 
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of 
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
 
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+   "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+   "'Ziccif' (Main Memory Supports Instruction Fetch with 
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+   "'Zicclsm' (Main Memory Supports Misaligned 
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+   "'Ziccrse' (Main Memory Supports Forward Progress on 
LR/SC Sequences)">;
+
 def FeatureStdExtZicntr
 : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -517,6 +533,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision 
Floating-Point)">;
 
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+   "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
 def FeatureStdExtZicbom
 : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -561,6 +581,12 @@ def HasStdExtZtso : 
Predicate<"Subtarget->hasStdExtZtso()">,
   "'Ztso' (Memory Model - Total Store Order)">;
 def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", 
"true",
+"'Za64rs' (Reservation Set Size of 
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", 
"true",
+"'Za128rs' (Reservation Set Size 
of at Most 128 Bytes)">;
+
 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
   "'Zawrs' (Wait on Reservation Set)">;
 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 60ef404ac345d15..3e55e0fb4e6861e 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -130,6 +130,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck 
--check-prefixes=CHECK,RV64COMBINEINTOZK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - 
| FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
 ; RUN: llc

[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-18 Thread Luke Lau via cfe-commits 

https://github.com/lukel97 updated 
https://github.com/llvm/llvm-project/pull/77458

>From fb8eebe1c7f5b4dec812c64d9a2572a98d59bdb8 Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
 defined in profiles spec

This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions

As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
 llvm/lib/Support/RISCVISAInfo.cpp  |  7 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
 llvm/test/CodeGen/RISCV/attributes.ll  | 14 ++
 3 files changed, 47 insertions(+)

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index d991878a5f1eca..8c9eb1bddb3cb5 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -88,6 +88,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xtheadvdot", {1, 0}},
 {"xventanacondops", {1, 0}},
 
+{"za128rs", {1, 0}},
+{"za64rs", {1, 0}},
 {"zawrs", {1, 0}},
 
 {"zba", {1, 0}},
@@ -116,9 +118,14 @@ static const RISCVSupportedExtension SupportedExtensions[] 
= {
 {"zhinx", {1, 0}},
 {"zhinxmin", {1, 0}},
 
+{"zic64b", {1, 0}},
 {"zicbom", {1, 0}},
 {"zicbop", {1, 0}},
 {"zicboz", {1, 0}},
+{"ziccamoa", {1, 0}},
+{"ziccif", {1, 0}},
+{"zicclsm", {1, 0}},
+{"ziccrse", {1, 0}},
 {"zicntr", {2, 0}},
 {"zicsr", {2, 0}},
 {"zifencei", {2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa334c69ddc982..1946f2253fa6c0 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -93,6 +93,22 @@ def HasStdExtZifencei : 
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of 
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
 
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+   "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+   "'Ziccif' (Main Memory Supports Instruction Fetch with 
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+   "'Zicclsm' (Main Memory Supports Misaligned 
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+   "'Ziccrse' (Main Memory Supports Forward Progress on 
LR/SC Sequences)">;
+
 def FeatureStdExtZicntr
 : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -517,6 +533,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision 
Floating-Point)">;
 
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+   "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
 def FeatureStdExtZicbom
 : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -561,6 +581,12 @@ def HasStdExtZtso : 
Predicate<"Subtarget->hasStdExtZtso()">,
   "'Ztso' (Memory Model - Total Store Order)">;
 def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", 
"true",
+"'Za64rs' (Reservation Set Size of 
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", 
"true",
+"'Za128rs' (Reservation Set Size 
of at Most 128 Bytes)">;
+
 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
   "'Zawrs' (Wait on Reservation Set)">;
 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 60ef404ac345d1..3e55e0fb4e6861 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -130,6 +130,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck 
--check-prefixes=CHECK,RV64COMBINEINTOZK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - 
| FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
 ; RUN: llc -mtri

[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-11 Thread Luke Lau via cfe-commits 

lukel97 wrote:

Rebased on top of 79889fedc57707e99740abc1f48e6c5601d5a3f3

https://github.com/llvm/llvm-project/pull/77458
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[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-11 Thread Luke Lau via cfe-commits 

https://github.com/lukel97 updated 
https://github.com/llvm/llvm-project/pull/77458

>From 8de2b22ba2723fccf16ca4d2a863f84fd1b66493 Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
 defined in profiles spec

This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions

As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
 llvm/lib/Support/RISCVISAInfo.cpp  |  7 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
 llvm/test/CodeGen/RISCV/attributes.ll  | 14 ++
 3 files changed, 47 insertions(+)

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a795..bac7fa1b8f07da 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -88,6 +88,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xtheadvdot", {1, 0}},
 {"xventanacondops", {1, 0}},
 
+{"za128rs", {1, 0}},
+{"za64rs", {1, 0}},
 {"zawrs", {1, 0}},
 
 {"zba", {1, 0}},
@@ -116,9 +118,14 @@ static const RISCVSupportedExtension SupportedExtensions[] 
= {
 {"zhinx", {1, 0}},
 {"zhinxmin", {1, 0}},
 
+{"zic64b", {1, 0}},
 {"zicbom", {1, 0}},
 {"zicbop", {1, 0}},
 {"zicboz", {1, 0}},
+{"ziccamoa", {1, 0}},
+{"ziccif", {1, 0}},
+{"zicclsm", {1, 0}},
+{"ziccrse", {1, 0}},
 {"zicntr", {2, 0}},
 {"zicsr", {2, 0}},
 {"zifencei", {2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 279509575bb52a..1d34fb2c4b5cf6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei : 
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of 
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
 
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+   "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+   "'Ziccif' (Main Memory Supports Instruction Fetch with 
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+   "'Zicclsm' (Main Memory Supports Misaligned 
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+   "'Ziccrse' (Main Memory Supports Forward Progress on 
LR/SC Sequences)">;
+
 def FeatureStdExtZicntr
 : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision 
Floating-Point)">;
 
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+   "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
 def FeatureStdExtZicbom
 : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso : 
Predicate<"Subtarget->hasStdExtZtso()">,
   "'Ztso' (Memory Model - Total Store Order)">;
 def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", 
"true",
+"'Za64rs' (Reservation Set Size of 
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", 
"true",
+"'Za128rs' (Reservation Set Size 
of at Most 128 Bytes)">;
+
 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
   "'Zawrs' (Wait on Reservation Set)">;
 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..8373ead932a695 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -130,6 +130,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck 
--check-prefixes=CHECK,RV64COMBINEINTOZK %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - 
| FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
 ; RUN: llc -mtri

[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-11 Thread Luke Lau via cfe-commits 

https://github.com/lukel97 updated 
https://github.com/llvm/llvm-project/pull/77458

>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
 defined in profiles spec

This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions

As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
 llvm/lib/Support/RISCVISAInfo.cpp  |  7 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
 llvm/test/CodeGen/RISCV/attributes.ll  | 14 ++
 3 files changed, 47 insertions(+)

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..c5c8f86a72d9d7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xtheadvdot", RISCVExtensionVersion{1, 0}},
 {"xventanacondops", RISCVExtensionVersion{1, 0}},
 
+{"za128rs", RISCVExtensionVersion{1, 0}},
+{"za64rs", RISCVExtensionVersion{1, 0}},
 {"zawrs", RISCVExtensionVersion{1, 0}},
 
 {"zba", RISCVExtensionVersion{1, 0}},
@@ -121,9 +123,14 @@ static const RISCVSupportedExtension SupportedExtensions[] 
= {
 {"zhinx", RISCVExtensionVersion{1, 0}},
 {"zhinxmin", RISCVExtensionVersion{1, 0}},
 
+{"zic64b", RISCVExtensionVersion{1, 0}},
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
+{"ziccamoa", RISCVExtensionVersion{1, 0}},
+{"ziccif", RISCVExtensionVersion{1, 0}},
+{"zicclsm", RISCVExtensionVersion{1, 0}},
+{"ziccrse", RISCVExtensionVersion{1, 0}},
 {"zicntr", RISCVExtensionVersion{2, 0}},
 {"zicsr", RISCVExtensionVersion{2, 0}},
 {"zifencei", RISCVExtensionVersion{2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..17ed2a3aa2c57c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei : 
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of 
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
 
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+   "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+   "'Ziccif' (Main Memory Supports Instruction Fetch with 
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+   "'Zicclsm' (Main Memory Supports Misaligned 
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+   "'Ziccrse' (Main Memory Supports Forward Progress on 
LR/SC Sequences)">;
+
 def FeatureStdExtZicntr
 : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision 
Floating-Point)">;
 
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+   "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
 def FeatureStdExtZicbom
 : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso : 
Predicate<"Subtarget->hasStdExtZtso()">,
   "'Ztso' (Memory Model - Total Store Order)">;
 def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", 
"true",
+"'Za64rs' (Reservation Set Size of 
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", 
"true",
+"'Za128rs' (Reservation Set Size 
of at Most 128 Bytes)">;
+
 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
   "'Zawrs' (Wait on Reservation Set)">;
 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..83

[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-10 Thread Philip Reames via cfe-commits 


@@ -96,6 +96,8 @@ on support follow.
  ``Svnapot``  Assembly Support
  ``Svpbmt``   Supported
  ``V``Supported
+ ``Za128rs``  Supported

preames wrote:

I think these may warrant an explanatory note after the table.  See what we do 
for e.g. zicntr.  Something which says these are defined by the profile 
specification seems like a useful breadcrumb.  

https://github.com/llvm/llvm-project/pull/77458
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[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-10 Thread Alex Bradbury via cfe-commits 

https://github.com/asb approved this pull request.

LGTM, but please add a release note too.

https://github.com/llvm/llvm-project/pull/77458
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[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-09 Thread Luke Lau via cfe-commits 

lukel97 wrote:

@asb I got a response from https://github.com/riscv/riscv-profiles/issues/139, 
looks like Ziccrse, Ziccamoa, Za64rs, and Za128rs don't imply A.

https://github.com/llvm/llvm-project/pull/77458
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[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

2024-01-09 Thread Luke Lau via cfe-commits 

https://github.com/lukel97 updated 
https://github.com/llvm/llvm-project/pull/77458

>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau 
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/4] [RISCV] Add support for new unprivileged extensions
 defined in profiles spec

This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions

As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
 llvm/lib/Support/RISCVISAInfo.cpp  |  7 +++
 llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
 llvm/test/CodeGen/RISCV/attributes.ll  | 14 ++
 3 files changed, 47 insertions(+)

diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..c5c8f86a72d9d7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 {"xtheadvdot", RISCVExtensionVersion{1, 0}},
 {"xventanacondops", RISCVExtensionVersion{1, 0}},
 
+{"za128rs", RISCVExtensionVersion{1, 0}},
+{"za64rs", RISCVExtensionVersion{1, 0}},
 {"zawrs", RISCVExtensionVersion{1, 0}},
 
 {"zba", RISCVExtensionVersion{1, 0}},
@@ -121,9 +123,14 @@ static const RISCVSupportedExtension SupportedExtensions[] 
= {
 {"zhinx", RISCVExtensionVersion{1, 0}},
 {"zhinxmin", RISCVExtensionVersion{1, 0}},
 
+{"zic64b", RISCVExtensionVersion{1, 0}},
 {"zicbom", RISCVExtensionVersion{1, 0}},
 {"zicbop", RISCVExtensionVersion{1, 0}},
 {"zicboz", RISCVExtensionVersion{1, 0}},
+{"ziccamoa", RISCVExtensionVersion{1, 0}},
+{"ziccif", RISCVExtensionVersion{1, 0}},
+{"zicclsm", RISCVExtensionVersion{1, 0}},
+{"ziccrse", RISCVExtensionVersion{1, 0}},
 {"zicntr", RISCVExtensionVersion{2, 0}},
 {"zicsr", RISCVExtensionVersion{2, 0}},
 {"zifencei", RISCVExtensionVersion{2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..17ed2a3aa2c57c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei : 
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of 
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
 
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+   "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+   "'Ziccif' (Main Memory Supports Instruction Fetch with 
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+   "'Zicclsm' (Main Memory Supports Misaligned 
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+   "'Ziccrse' (Main Memory Supports Forward Progress on 
LR/SC Sequences)">;
+
 def FeatureStdExtZicntr
 : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision 
Floating-Point)">;
 
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+   "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
 def FeatureStdExtZicbom
 : SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso : 
Predicate<"Subtarget->hasStdExtZtso()">,
   "'Ztso' (Memory Model - Total Store Order)">;
 def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
 
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", 
"true",
+"'Za64rs' (Reservation Set Size of 
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", 
"true",
+"'Za128rs' (Reservation Set Size 
of at Most 128 Bytes)">;
+
 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
   "'Zawrs' (Wait on Reservation Set)">;
 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll 
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..83