subject:"\[clang\] \[llvm\] \[SME\] Add intrinsics for FCVT\(wid.\) and FCVTL \(PR #93202\)"

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-23 Thread via cfe-commits


https://github.com/Lukacma created 
https://github.com/llvm/llvm-project/pull/93202

According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics

svfloat32x2_t svcvt_f32[_f16_x2](svfloat16_t zn) __arm_streaming;
svfloat32x2_t svcvtl_f32[_f16_x2](svfloat16_t zn) __arm_streaming;

These are available only if __ARM_FEATURE_SME_F16F16 is enabled.

>From a1750b2b5658f8ced700bbf010019703fc52f126 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Mon, 15 Apr 2024 13:31:00 +
Subject: [PATCH 1/6] [LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16

According to the latest ISA Spec release[1] all instructions under:
 HasSME2p1 and HasSMEF16F16
should now only require:
HasSMEF16F16

[1]https://developer.arm.com
---
 llvm/test/MC/AArch64/SME2p1/fadd.s | 8 
 llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fsub.s | 8 
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/llvm/test/MC/AArch64/SME2p1/fadd.s 
b/llvm/test/MC/AArch64/SME2p1/fadd.s
index bdb769093c838..ec4f27e021a00 100644
--- a/llvm/test/MC/AArch64/SME2p1/fadd.s
+++ b/llvm/test/MC/AArch64/SME2p1/fadd.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s 
--check-prefix=CHECK-UNKNOWN
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \
 // RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
+// RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 faddza.h[w8, 0, vgx2], {z0.h, z1.h}  // 1101-10100100-00011100-
diff --git a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
index 2f0dccb57c907..c31b54fc05dea 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
@@ -66,7 +66,7 @@ fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
index 3ff09321e3436..2deb18186eafc 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
@@ -66,7 +66,7 @@ fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fsub.s 
b/llvm/test/MC/AArch64/SME2p1/fsub.s
index 66410008eb11d..e42a819e0d415 100644
--- a/llvm/test/MC/AArch64/SME2p1/fsub.s
+++ b/llvm/test/MC/AArch64/SME2p1/fsub.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-pr

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-23 Thread via cfe-commits


https://github.com/Lukacma edited 
https://github.com/llvm/llvm-project/pull/93202
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-23 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-clang

Author: None (Lukacma)


Changes

According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
```
svfloat32x2_t svcvt_f32[_f16_x2](svfloat16_t zn) __arm_streaming;
svfloat32x2_t svcvtl_f32[_f16_x2](svfloat16_t zn) __arm_streaming;

```
These are available only if __ARM_FEATURE_SME_F16F16 is enabled.

---
Full diff: https://github.com/llvm/llvm-project/pull/93202.diff


7 Files Affected:

- (modified) clang/include/clang/Basic/arm_sve.td (+11) 
- (modified) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c (+22) 
- (added) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c (+40) 
- (modified) llvm/include/llvm/IR/IntrinsicsAArch64.td (+13-1) 
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+6) 
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-cvt.ll (+10-1) 
- (added) llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtl.ll (+11) 


``diff
diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 15340ebb62b36..af0562ad87080 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2265,6 +2265,10 @@ let TargetGuard = "sme2" in {
   def SVCVT_S32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "i",  
MergeNone, "aarch64_sve_fcvtzs_x4", [IsStreaming, 
IsOverloadWhileOrMultiVecCvt], []>;
 }
 
+let TargetGuard = "sme-f16f16" in {
+  def SVCVT_F32_X2 : SInst<"svcvt_{d}[_f16_x2]", "2h", "f", MergeNone, 
"aarch64_sve_fcvt_widen_x2", [ IsStreaming],[]>;
+}
+
 //
 // Multi-vector floating-point convert from single-precision to interleaved 
half-precision/BFloat16
 //
@@ -2273,6 +2277,13 @@ let TargetGuard = "sme2" in {
   def SVCVTN_BF16_X2 : SInst<"svcvtn_bf16[_f32_x2]", "$2", "f", MergeNone, 
"aarch64_sve_bfcvtn_x2", [IsOverloadNone, IsStreaming],[]>;
 }
 
+//
+//Multi-vector floating-point convert from half-precision to deinterleaved 
single-precision.
+//
+let TargetGuard = "sme-f16f16" in {
+  def SVCVTL_F32_X2 : SInst<"svcvtl_f32[_f16_x2]", "2h", "f", MergeNone, 
"aarch64_sve_fcvtl_widen_x2", [ IsStreaming],[]>;
+}
+
 //
 // Multi-vector saturating extract narrow
 //
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c 
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
index 79a11c2ec153e..d117a685bfc29 100644
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
@@ -497,3 +497,25 @@ svuint8_t test_qcvt_u8_s32_x4(svint32x4_t zn) 
__arm_streaming {
 svuint16_t test_qcvt_u16_s64_x4(svint64x4_t zn) __arm_streaming {
   return SVE_ACLE_FUNC(svqcvt_u16,_s64_x4,,)(zn);
 }
+
+// CHECK-LABEL: @test_cvt_f32_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { ,  } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32( 
[[ZN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = extractvalue { ,  } [[TMP0]], 0
+// CHECK-NEXT:[[TMP2:%.*]] = tail call  
@llvm.vector.insert.nxv8f32.nxv4f32( poison,  [[TMP1]], i64 0)
+// CHECK-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP0]], 1
+// CHECK-NEXT:[[TMP4:%.*]] = tail call  
@llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]],  [[TMP3]], i64 4)
+// CHECK-NEXT:ret  [[TMP4]]
+//
+// CPP-CHECK-LABEL: @_Z15test_cvt_f32_x2u13__SVFloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call { ,  } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32( 
[[ZN:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = extractvalue { , 
 } [[TMP0]], 0
+// CPP-CHECK-NEXT:[[TMP2:%.*]] = tail call  
@llvm.vector.insert.nxv8f32.nxv4f32( poison,  [[TMP1]], i64 0)
+// CPP-CHECK-NEXT:[[TMP3:%.*]] = extractvalue { , 
 } [[TMP0]], 1
+// CPP-CHECK-NEXT:[[TMP4:%.*]] = tail call  
@llvm.vector.insert.nxv8f32.nxv4f32( [[TMP2]],  [[TMP3]], i64 4)
+// CPP-CHECK-NEXT:ret  [[TMP4]]
+//
+__attribute__((target("sme-f16f16"))) svfloat32x2_t 
test_cvt_f32_x2(svfloat16_t zn)  __arm_streaming {
+  return SVE_ACLE_FUNC(svcvt_f32,_f16_x2,,)(zn);
+}
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c 
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
new file mode 100644
index 0..1142065614b8f
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c
@@ -0,0 +1,40 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sme-f16f16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o 
- %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sme-f16f16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o 
- -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-t

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-23 Thread via cfe-commits


Lukacma wrote:

This pull request reapplies #90215 with fixed test

https://github.com/llvm/llvm-project/pull/93202
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-23 Thread via cfe-commits


https://github.com/Lukacma updated 
https://github.com/llvm/llvm-project/pull/93202

>From a1750b2b5658f8ced700bbf010019703fc52f126 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Mon, 15 Apr 2024 13:31:00 +
Subject: [PATCH 1/7] [LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16

According to the latest ISA Spec release[1] all instructions under:
 HasSME2p1 and HasSMEF16F16
should now only require:
HasSMEF16F16

[1]https://developer.arm.com
---
 llvm/test/MC/AArch64/SME2p1/fadd.s | 8 
 llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fsub.s | 8 
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/llvm/test/MC/AArch64/SME2p1/fadd.s 
b/llvm/test/MC/AArch64/SME2p1/fadd.s
index bdb769093c838..ec4f27e021a00 100644
--- a/llvm/test/MC/AArch64/SME2p1/fadd.s
+++ b/llvm/test/MC/AArch64/SME2p1/fadd.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s 
--check-prefix=CHECK-UNKNOWN
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \
 // RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
+// RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 faddza.h[w8, 0, vgx2], {z0.h, z1.h}  // 1101-10100100-00011100-
diff --git a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
index 2f0dccb57c907..c31b54fc05dea 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
@@ -66,7 +66,7 @@ fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
index 3ff09321e3436..2deb18186eafc 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
@@ -66,7 +66,7 @@ fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fsub.s 
b/llvm/test/MC/AArch64/SME2p1/fsub.s
index 66410008eb11d..e42a819e0d415 100644
--- a/llvm/test/MC/AArch64/SME2p1/fsub.s
+++ b/llvm/test/MC/AArch64/SME2p1/fsub.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 //

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-23 Thread via cfe-commits


https://github.com/Lukacma updated 
https://github.com/llvm/llvm-project/pull/93202

>From a1750b2b5658f8ced700bbf010019703fc52f126 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Mon, 15 Apr 2024 13:31:00 +
Subject: [PATCH 1/7] [LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16

According to the latest ISA Spec release[1] all instructions under:
 HasSME2p1 and HasSMEF16F16
should now only require:
HasSMEF16F16

[1]https://developer.arm.com
---
 llvm/test/MC/AArch64/SME2p1/fadd.s | 8 
 llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fsub.s | 8 
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/llvm/test/MC/AArch64/SME2p1/fadd.s 
b/llvm/test/MC/AArch64/SME2p1/fadd.s
index bdb769093c838..ec4f27e021a00 100644
--- a/llvm/test/MC/AArch64/SME2p1/fadd.s
+++ b/llvm/test/MC/AArch64/SME2p1/fadd.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s 
--check-prefix=CHECK-UNKNOWN
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \
 // RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
+// RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 faddza.h[w8, 0, vgx2], {z0.h, z1.h}  // 1101-10100100-00011100-
diff --git a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
index 2f0dccb57c907..c31b54fc05dea 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
@@ -66,7 +66,7 @@ fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
index 3ff09321e3436..2deb18186eafc 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
@@ -66,7 +66,7 @@ fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fsub.s 
b/llvm/test/MC/AArch64/SME2p1/fsub.s
index 66410008eb11d..e42a819e0d415 100644
--- a/llvm/test/MC/AArch64/SME2p1/fsub.s
+++ b/llvm/test/MC/AArch64/SME2p1/fsub.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 //

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-28 Thread via cfe-commits


https://github.com/Lukacma updated 
https://github.com/llvm/llvm-project/pull/93202

>From a1750b2b5658f8ced700bbf010019703fc52f126 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Mon, 15 Apr 2024 13:31:00 +
Subject: [PATCH 1/7] [LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16

According to the latest ISA Spec release[1] all instructions under:
 HasSME2p1 and HasSMEF16F16
should now only require:
HasSMEF16F16

[1]https://developer.arm.com
---
 llvm/test/MC/AArch64/SME2p1/fadd.s | 8 
 llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fsub.s | 8 
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/llvm/test/MC/AArch64/SME2p1/fadd.s 
b/llvm/test/MC/AArch64/SME2p1/fadd.s
index bdb769093c838..ec4f27e021a00 100644
--- a/llvm/test/MC/AArch64/SME2p1/fadd.s
+++ b/llvm/test/MC/AArch64/SME2p1/fadd.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s 
--check-prefix=CHECK-UNKNOWN
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \
 // RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
+// RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 faddza.h[w8, 0, vgx2], {z0.h, z1.h}  // 1101-10100100-00011100-
diff --git a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
index 2f0dccb57c907..c31b54fc05dea 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
@@ -66,7 +66,7 @@ fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
index 3ff09321e3436..2deb18186eafc 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
@@ -66,7 +66,7 @@ fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fsub.s 
b/llvm/test/MC/AArch64/SME2p1/fsub.s
index 66410008eb11d..e42a819e0d415 100644
--- a/llvm/test/MC/AArch64/SME2p1/fsub.s
+++ b/llvm/test/MC/AArch64/SME2p1/fsub.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 //

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-28 Thread via cfe-commits


https://github.com/Lukacma updated 
https://github.com/llvm/llvm-project/pull/93202

>From a1750b2b5658f8ced700bbf010019703fc52f126 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Mon, 15 Apr 2024 13:31:00 +
Subject: [PATCH 1/7] [LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16

According to the latest ISA Spec release[1] all instructions under:
 HasSME2p1 and HasSMEF16F16
should now only require:
HasSMEF16F16

[1]https://developer.arm.com
---
 llvm/test/MC/AArch64/SME2p1/fadd.s | 8 
 llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fsub.s | 8 
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/llvm/test/MC/AArch64/SME2p1/fadd.s 
b/llvm/test/MC/AArch64/SME2p1/fadd.s
index bdb769093c838..ec4f27e021a00 100644
--- a/llvm/test/MC/AArch64/SME2p1/fadd.s
+++ b/llvm/test/MC/AArch64/SME2p1/fadd.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s 
--check-prefix=CHECK-UNKNOWN
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \
 // RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
+// RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 faddza.h[w8, 0, vgx2], {z0.h, z1.h}  // 1101-10100100-00011100-
diff --git a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
index 2f0dccb57c907..c31b54fc05dea 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
@@ -66,7 +66,7 @@ fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
index 3ff09321e3436..2deb18186eafc 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
@@ -66,7 +66,7 @@ fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fsub.s 
b/llvm/test/MC/AArch64/SME2p1/fsub.s
index 66410008eb11d..e42a819e0d415 100644
--- a/llvm/test/MC/AArch64/SME2p1/fsub.s
+++ b/llvm/test/MC/AArch64/SME2p1/fsub.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 //

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-29 Thread via cfe-commits


https://github.com/Lukacma updated 
https://github.com/llvm/llvm-project/pull/93202

>From a1750b2b5658f8ced700bbf010019703fc52f126 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Mon, 15 Apr 2024 13:31:00 +
Subject: [PATCH 1/7] [LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16

According to the latest ISA Spec release[1] all instructions under:
 HasSME2p1 and HasSMEF16F16
should now only require:
HasSMEF16F16

[1]https://developer.arm.com
---
 llvm/test/MC/AArch64/SME2p1/fadd.s | 8 
 llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s | 2 +-
 llvm/test/MC/AArch64/SME2p1/fsub.s | 8 
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/llvm/test/MC/AArch64/SME2p1/fadd.s 
b/llvm/test/MC/AArch64/SME2p1/fadd.s
index bdb769093c838..ec4f27e021a00 100644
--- a/llvm/test/MC/AArch64/SME2p1/fadd.s
+++ b/llvm/test/MC/AArch64/SME2p1/fadd.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
+// RUN:| llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s 
--check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \
 // RUN:| llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s 
--check-prefix=CHECK-UNKNOWN
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| sed '/.text/d' | sed 's/.*encoding: //g' \
 // RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
+// RUN:| llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble 
-show-encoding \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 faddza.h[w8, 0, vgx2], {z0.h, z1.h}  // 1101-10100100-00011100-
diff --git a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
index 2f0dccb57c907..c31b54fc05dea 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
@@ -66,7 +66,7 @@ fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s 
b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
index 3ff09321e3436..2deb18186eafc 100644
--- a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
@@ -66,7 +66,7 @@ fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // Invalid Register Suffix
 
 fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected 
suffix .h
 // CHECK-NEXT: fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
diff --git a/llvm/test/MC/AArch64/SME2p1/fsub.s 
b/llvm/test/MC/AArch64/SME2p1/fsub.s
index 66410008eb11d..e42a819e0d415 100644
--- a/llvm/test/MC/AArch64/SME2p1/fsub.s
+++ b/llvm/test/MC/AArch64/SME2p1/fsub.s
@@ -1,16 +1,24 @@
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \
+// RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \
 // RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:| FileCheck %s --check-prefix=CHECK-ERROR
 //

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

2024-05-29 Thread via cfe-commits


https://github.com/Lukacma closed 
https://github.com/llvm/llvm-project/pull/93202
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

[clang] [llvm] [SME] Add intrinsics for FCVT(wid.) and FCVTL (PR #93202)

10 matches

Site Navigation

Mail list logo

Footer information