[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
https://github.com/jroelofs closed https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
https://github.com/ahmedbougacha approved this pull request. https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -1010,6 +1034,9 @@ def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, [TuneAppleA17]>; +def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4, jroelofs wrote: https://github.com/llvm/llvm-project/pull/95579 https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -1010,6 +1034,9 @@ def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, [TuneAppleA17]>; +def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4, mstorsjo wrote: Ah, right - sorry I forgot about that distinction. (I guess it'll end up in macs at some point too, and I know you can't comment on that - so until then this is indeed the right sorting.) https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -1010,6 +1034,9 @@ def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, [TuneAppleA17]>; +def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4, jroelofs wrote: We should probably rearrange them to remove that distinction though, so that aliases that share the same `ProcessorFeatures.AppleA*` are together. I'll do that in a follow-up commit. https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -1010,6 +1034,9 @@ def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, [TuneAppleA17]>; +def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4, jroelofs wrote: No, it is an iPad CPU: https://www.apple.com/newsroom/2024/05/apple-introduces-m4-chip/ https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -521,7 +521,14 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_SHA3, AArch64::AEK_FP16,
AArch64::AEK_FP16FML})},
-
+// Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as
+// requiring SVE, which is optional according to the Arm ARM and not
+// supported by the core. ARMv8.7a is the next closest choice.
jroelofs wrote:
Let's do that as a separate change _after_ this one. That order will ensure
this is still correct (as it can be) even after the revert, without the author
of the revert having to think about this.
https://github.com/llvm/llvm-project/pull/95478
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[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -521,7 +521,14 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_SHA3, AArch64::AEK_FP16,
AArch64::AEK_FP16FML})},
-
+// Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as
+// requiring SVE, which is optional according to the Arm ARM and not
+// supported by the core. ARMv8.7a is the next closest choice.
tmatheson-arm wrote:
>From the Arm ARM:
> FEAT_SVE2 is OPTIONAL from Armv9.0.
In LLVM, SVE2 is an `Implied` (read: mandatory) feature of 9.0-a (wrong), and
SVE and SVE2 are both on by default for the architecture:
```
def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
[HasV8_5aOps, FeatureMEC, FeatureSVE2],
!listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,
FeatureSVE2])>;
```
It should be possible to remove SVE2 from the `Implied` list while keeping it
in the list of default extensions, which would avoid any user-facing changes.
I'm not sure why FEAT_MEC is enabled there either.
> FEAT_MEC is OPTIONAL from Armv9.2.
https://github.com/llvm/llvm-project/pull/95478
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[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
tschuett wrote: It is a problem that is worth fixing long term. How to correctly model release versions and their optional dependencies. Furthermore, for the BTI example how remove features. https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
@@ -1010,6 +1034,9 @@ def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16, [TuneAppleA16]>; def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17, [TuneAppleA17]>; +def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4, mstorsjo wrote: Shouldn't this go below, under `// Mac CPUs`? https://github.com/llvm/llvm-project/pull/95478 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [llvm][AArch64] Support -mcpu=apple-m4 (PR #95478)
https://github.com/jroelofs updated
https://github.com/llvm/llvm-project/pull/95478
>From 1461be872bf26e2e0f2572f688a45af795421432 Mon Sep 17 00:00:00 2001
From: Jon Roelofs
Date: Thu, 13 Jun 2024 10:27:52 -0700
Subject: [PATCH 1/2] [llvm][AArch64] Support -mcpu=apple-m4
---
.../llvm/TargetParser/AArch64TargetParser.h | 9 +-
llvm/lib/Target/AArch64/AArch64Processors.td | 31 +--
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 2 ++
.../TargetParser/TargetParserTest.cpp | 17 +-
4 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index df8e685eb6667..c1a68a0ec5c19 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -521,7 +521,14 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
AArch64::AEK_SHA3, AArch64::AEK_FP16,
AArch64::AEK_FP16FML})},
-
+// Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as
+// requiring SVE, which is optional according to the Arm ARM and not
+// supported by the core. ARMv8.7a is the next closest choice.
+{"apple-m4", ARMV8_7A,
+ AArch64::ExtensionBitset(
+ {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
+ AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_SME,
+ AArch64::AEK_SME2, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64})},
{"apple-s4", ARMV8_3A,
AArch64::ExtensionBitset(
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_FP16})},
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index c04c20c78e8eb..57df6b85ab11d 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -398,6 +398,22 @@ def TuneAppleA17 : SubtargetFeature<"apple-a17",
"ARMProcFamily", "AppleA17",
FeatureZCRegMove,
FeatureZCZeroing]>;
+def TuneAppleM4 : SubtargetFeature<"apple-m4", "ARMProcFamily", "AppleM4",
+ "Apple M4", [
+ FeatureAlternateSExtLoadCVTF32Pattern,
+ FeatureArithmeticBccFusion,
+ FeatureArithmeticCbzFusion,
+ FeatureDisableLatencySchedHeuristic,
+ FeatureFuseAddress,
+ FeatureFuseAES,
+ FeatureFuseArithmeticLogic,
+ FeatureFuseCCSelect,
+ FeatureFuseCryptoEOR,
+ FeatureFuseLiterals,
+ FeatureZCRegMove,
+ FeatureZCZeroing
+ ]>;
+
def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
"Samsung Exynos-M3 processors",
[FeatureExynosCheapAsMoveHandling,
@@ -784,6 +800,14 @@ def ProcessorFeatures {
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureHCX];
+ // Technically apple-m4 is ARMv9.2. See the corresponding comment in
+ // AArch64TargetParser.h.
+ list AppleM4 = [HasV8_7aOps, FeatureCrypto, FeatureFPARMv8,
+FeatureNEON, FeaturePerfMon, FeatureSHA3,
+FeatureFullFP16, FeatureFP16FML,
+FeatureAES, FeatureBF16,
+FeatureSME2,
+FeatureSMEF64F64, FeatureSMEI16I64];
list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
FeaturePerfMon];
list ExynosM4 = [HasV8_2aOps, FeatureCrypto,
FeatureDotProd,
@@ -1010,6 +1034,9 @@ def : ProcessorModel<"apple-a16", CycloneModel,
ProcessorFeatures.AppleA16,
[TuneAppleA16]>;
def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
[TuneAppleA17]>;
+def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4,
+ [TuneAppleM4]>;
+
// Mac CPUs
def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
[TuneAppleA14]>;
@@ -1025,8 +1052,8 @@ def : ProcessorModel<"apple-s5", CycloneModel,
ProcessorFeatures.AppleA12,
[TuneAppleA12]>;
// Alias for the latest Apple processor model supported by LLVM.
-def :
