[clang] [llvm] Revert "[AArch64] Add intrinsics for multi-vector to ZA array vector accumulators" (PR #91597)
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-llvm-ir
Author: Momchil Velikov (momchil-velikov)
Changes
Reverts llvm/llvm-project#88266 due to test failures
error: 'expected-error' diagnostics seen but not expected:
(frontend): '-fsyntax-only' action ignored; '-emit-llvm' action specified
previously
---
Patch is 31.61 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/91597.diff
6 Files Affected:
- (modified) clang/include/clang/Basic/arm_sme.td (-10)
- (removed) clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
(-193)
- (removed) clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
(-29)
- (modified) llvm/include/llvm/IR/IntrinsicsAArch64.td (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td (+8-8)
- (removed) llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll (-148)
``diff
diff --git a/clang/include/clang/Basic/arm_sme.td
b/clang/include/clang/Basic/arm_sme.td
index 000bd97a4b25d..1ac6d5170ea28 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -298,16 +298,6 @@ multiclass ZAAddSub {
def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2",
"vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming,
IsInOutZA], []>;
def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4",
"vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming,
IsInOutZA], []>;
}
-
- let TargetGuard = "sme-f16f16|sme-f8f16" in {
-def NAME # _ZA16_VG1X2_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2",
"vm2", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming,
IsInOutZA], []>;
-def NAME # _ZA16_VG1X4_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4",
"vm4", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming,
IsInOutZA], []>;
- }
-
- let TargetGuard = "sme2,b16b16" in {
-def NAME # _ZA16_VG1X2_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2",
"vm2", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming,
IsInOutZA], []>;
-def NAME # _ZA16_VG1X4_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4",
"vm4", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming,
IsInOutZA], []>;
- }
}
defm SVADD : ZAAddSub<"add">;
diff --git
a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
deleted file mode 100644
index d98427fac610b..0
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
+++ /dev/null
@@ -1,193 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
-// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1-x c++ -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s -check-prefix CHECK-CXX
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS-fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s -check-prefix CHECK-CXX
-
-// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -o /dev/null
-
-// REQUIRES: aarch64-registered-target
-
-#include
-
-#ifdef SVE_OVERLOADED_FORMS
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3
-#endif
-
-// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x2_f16(
-// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call
@llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0)
-// CHECK-NEXT:[[TMP1:%.*]] = tail call
@llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8)
-// CHECK-NEXT:tail call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32
[[SLICE]], [[TMP0]], [[TMP1]])
-// CHECK-NEXT:ret void
-//
-// CHECK-CXX-LABEL: define dso_local void
@_Z25test_svadd_za16_vg1x2_f16j13svfloat16x2_t(
-// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]
[clang] [llvm] Revert "[AArch64] Add intrinsics for multi-vector to ZA array vector accumulators" (PR #91597)
https://github.com/momchil-velikov closed https://github.com/llvm/llvm-project/pull/91597 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Revert "[AArch64] Add intrinsics for multi-vector to ZA array vector accumulators" (PR #91597)
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/91597
Reverts llvm/llvm-project#88266 due to test failures
error: 'expected-error' diagnostics seen but not expected:
(frontend): '-fsyntax-only' action ignored; '-emit-llvm' action specified
previously
>From 0f71196108d1c3c1bb44305a3a8392f406ae71e9 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 9 May 2024 15:01:53 +0100
Subject: [PATCH] =?UTF-8?q?Revert=20"[AArch64]=20Add=20intrinsics=20for=20?=
=?UTF-8?q?multi-vector=20to=20ZA=20array=20vector=20accumula=E2=80=A6"?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This reverts commit e88ba6d975d887ca001cae30bfa0c53d91165148.
---
clang/include/clang/Basic/arm_sme.td | 10 -
.../acle_sme2_add_sub_za16.c | 193 --
.../acle_sme2_add_sub_za16.c | 29 ---
llvm/include/llvm/IR/IntrinsicsAArch64.td | 2 +-
.../lib/Target/AArch64/AArch64SMEInstrInfo.td | 16 +-
.../AArch64/sme2-intrinsics-add-sub-za16.ll | 148 --
6 files changed, 9 insertions(+), 389 deletions(-)
delete mode 100644
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
delete mode 100644
clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
delete mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll
diff --git a/clang/include/clang/Basic/arm_sme.td
b/clang/include/clang/Basic/arm_sme.td
index 000bd97a4b25d..1ac6d5170ea28 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -298,16 +298,6 @@ multiclass ZAAddSub {
def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2",
"vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming,
IsInOutZA], []>;
def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4",
"vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming,
IsInOutZA], []>;
}
-
- let TargetGuard = "sme-f16f16|sme-f8f16" in {
-def NAME # _ZA16_VG1X2_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2",
"vm2", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming,
IsInOutZA], []>;
-def NAME # _ZA16_VG1X4_F16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4",
"vm4", "h", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming,
IsInOutZA], []>;
- }
-
- let TargetGuard = "sme2,b16b16" in {
-def NAME # _ZA16_VG1X2_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x2",
"vm2", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x2", [IsStreaming,
IsInOutZA], []>;
-def NAME # _ZA16_VG1X4_BF16 : Inst<"sv" # n_suffix # "_za16[_{d}]_vg1x4",
"vm4", "b", MergeNone, "aarch64_sme_" # n_suffix # "_za16_vg1x4", [IsStreaming,
IsInOutZA], []>;
- }
}
defm SVADD : ZAAddSub<"add">;
diff --git
a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
deleted file mode 100644
index d98427fac610b..0
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add_sub_za16.c
+++ /dev/null
@@ -1,193 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
-// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1-x c++ -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s -check-prefix CHECK-CXX
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS-fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f8f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -emit-llvm -o - %s |
FileCheck %s -check-prefix CHECK-CXX
-
-// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall -o /dev/null
-
-// REQUIRES: aarch64-registered-target
-
-#include
-
-#ifdef SVE_OVERLOADED_FORMS
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3
-#endif
-
-// CHECK-LABEL: define dso_local void @test_svadd_za16_vg1x2_f16(
-// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]])
local_unnamed_addr #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call
@llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64
